Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 161025

Article: 161025
Subject: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 14 Jan 2019 11:54:32 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

I cannot understand the following paper:
"Efficient Multi-Ported Memories for FPGAs" 

http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf

FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.

The paper essence for 2 write ports and 2 read ports is:
There are 2 memory blocks each having 1 write port and 2 read ports.

The 2 memory blocks provide 2 write ports to write independently.

There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.

Example:

simultaneously:
Write through port 1 with address 3; --- no problem

Write through port 0 with address 2;

simultaneously:
0 --> LVT(2); 
1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?

If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.

Thank you.

Weng 




Article: 161026
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for
From: HT-Lab <hans64@htminuslab.com>
Date: Mon, 14 Jan 2019 21:22:58 +0000
Links: << >>  << T >>  << A >>
On 14/01/2019 19:54, Weng Tianxiang wrote:
> Hi,
> 
> I cannot understand the following paper:
> "Efficient Multi-Ported Memories for FPGAs"
> 
> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> 
> FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
> 
> The paper essence for 2 write ports and 2 read ports is:
> There are 2 memory blocks each having 1 write port and 2 read ports.
> 
> The 2 memory blocks provide 2 write ports to write independently.
> 
> There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
> 
> Example:
> 
> simultaneously:
> Write through port 1 with address 3; --- no problem
> 
> Write through port 0 with address 2;
> 
> simultaneously:
> 0 --> LVT(2);
> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
> 
> If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
> 
> Thank you.
> 
> Weng
> 

Hi Weng,

It is quite a simple scheme, assume you have 2 write ports each writing 
into their own blockram. If port0 write to address 0x12 and port1 writes 
to address 0x15 then the LVT (single bit array in this case) will store 
array[12]=0 and array[15]=1.
Then if a read port read from address 15 the LVT array will set the mux 
to 1 which connect the second blockram to the output.

I use the XOR variant in my processor for a 8w8r block.

Good luck,
Hans
www.ht-lab.com





Article: 161027
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 14 Jan 2019 13:40:52 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 1:23:01 PM UTC-8, HT-Lab wrote:
> On 14/01/2019 19:54, Weng Tianxiang wrote:
> > Hi,
> > 
> > I cannot understand the following paper:
> > "Efficient Multi-Ported Memories for FPGAs"
> > 
> > http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> > 
> > FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
> > 
> > The paper essence for 2 write ports and 2 read ports is:
> > There are 2 memory blocks each having 1 write port and 2 read ports.
> > 
> > The 2 memory blocks provide 2 write ports to write independently.
> > 
> > There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
> > 
> > Example:
> > 
> > simultaneously:
> > Write through port 1 with address 3; --- no problem
> > 
> > Write through port 0 with address 2;
> > 
> > simultaneously:
> > 0 --> LVT(2);
> > 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
> > 
> > If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
> > 
> > Thank you.
> > 
> > Weng
> > 
> 
> Hi Weng,
> 
> It is quite a simple scheme, assume you have 2 write ports each writing 
> into their own blockram. If port0 write to address 0x12 and port1 writes 
> to address 0x15 then the LVT (single bit array in this case) will store 
> array[12]=0 and array[15]=1.
> Then if a read port read from address 15 the LVT array will set the mux 
> to 1 which connect the second blockram to the output.
> 
> I use the XOR variant in my processor for a 8w8r block.
> 
> Good luck,
> Hans
> www.ht-lab.com

Hi Hans,

"If port0 write to address 0x12 and port1 writes 
to address 0x15 then the LVT (single bit array in this case) will store 
array[12]=0 and array[15]=1. "

How do you do: 0 --> array[12], 1 --> array[15] on the same cycle?

Thank you.

Weng

Article: 161028
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: gnuarm.deletethisbit@gmail.com
Date: Mon, 14 Jan 2019 14:42:33 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 4:23:01 PM UTC-5, HT-Lab wrote:
> On 14/01/2019 19:54, Weng Tianxiang wrote:
> > Hi,
> >=20
> > I cannot understand the following paper:
> > "Efficient Multi-Ported Memories for FPGAs"
> >=20
> > http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> >=20
> > FPGA has a structure with 1 write port and 2 read port memory block: 2 =
memory blocks sharing the same write port and each of 2 blocks can be read =
individually by 2 different read.
> >=20
> > The paper essence for 2 write ports and 2 read ports is:
> > There are 2 memory blocks each having 1 write port and 2 read ports.
> >=20
> > The 2 memory blocks provide 2 write ports to write independently.
> >=20
> > There is another memory block, called LVT (Live Value Table), with 2 wr=
ite ports and 2 read ports, each cell of which stores the port number which=
 holds the latest write data.
> >=20
> > Example:
> >=20
> > simultaneously:
> > Write through port 1 with address 3; --- no problem
> >=20
> > Write through port 0 with address 2;
> >=20
> > simultaneously:
> > 0 --> LVT(2);
> > 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycl=
e?
> >=20
> > If above 2 simultaneously write operation are feasible, 2 read operatio=
ns can read from LVT first to get proper port number, and then get the corr=
ect latest data read from the port number.
> >=20
> > Thank you.
> >=20
> > Weng
> >=20
>=20
> Hi Weng,
>=20
> It is quite a simple scheme, assume you have 2 write ports each writing=
=20
> into their own blockram. If port0 write to address 0x12 and port1 writes=
=20
> to address 0x15 then the LVT (single bit array in this case) will store=
=20
> array[12]=3D0 and array[15]=3D1.
> Then if a read port read from address 15 the LVT array will set the mux=
=20
> to 1 which connect the second blockram to the output.
>=20
> I use the XOR variant in my processor for a 8w8r block.

Our patent seeking friend fails to understand the very basic issue of how a=
 multi-write port RAM can operate.  The paper describes how you can fake a =
multi-write port RAM using multiple single-write port RAMs using a smaller =
word size multi-write port RAM.  This smaller RAM can be constructed from l=
ogic in the FPGA fabric which is clearly explained in the paper.=20

Sometimes you need to actually understand the field you are trying to seek =
patents in.  Or you can just use a shotgun approach and obtain many patents=
 hoping someday one of them ends up paying off. =20

  Rick C.

  - Get 6 months of free supercharging
  - Tesla referral code - https://ts.la/richard11209

Article: 161029
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Mon, 14 Jan 2019 15:15:13 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 5:42:37 PM UTC-5, gnuarm.del...@gmail.com wrote:
> Our patent seeking friend fails to understand the very basic issue
> of how a multi-write port RAM can operate.

Always there with a pure heart of kindness, one given to teaching,
apt to help compensate when someone is perhaps less than they should
be.  Always accommodating, always uplifting, always at the ready to
improve another's life, eh Rick?

-- 
Rick C. Hodgin

Article: 161030
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for
From: Rob Gaddi <rgaddi@highlandtechnology.invalid>
Date: Mon, 14 Jan 2019 15:38:30 -0800
Links: << >>  << T >>  << A >>
On 1/14/19 1:22 PM, HT-Lab wrote:
> On 14/01/2019 19:54, Weng Tianxiang wrote:
>> Hi,
>>
>> I cannot understand the following paper:
>> "Efficient Multi-Ported Memories for FPGAs"
>>
>> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
>>
>> FPGA has a structure with 1 write port and 2 read port memory block: 2 
>> memory blocks sharing the same write port and each of 2 blocks can be 
>> read individually by 2 different read.
>>
>> The paper essence for 2 write ports and 2 read ports is:
>> There are 2 memory blocks each having 1 write port and 2 read ports.
>>
>> The 2 memory blocks provide 2 write ports to write independently.
>>
>> There is another memory block, called LVT (Live Value Table), with 2 
>> write ports and 2 read ports, each cell of which stores the port 
>> number which holds the latest write data.
>>
>> Example:
>>
>> simultaneously:
>> Write through port 1 with address 3; --- no problem
>>
>> Write through port 0 with address 2;
>>
>> simultaneously:
>> 0 --> LVT(2);
>> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
>>
>> If above 2 simultaneously write operation are feasible, 2 read 
>> operations can read from LVT first to get proper port number, and then 
>> get the correct latest data read from the port number.
>>
>> Thank you.
>>
>> Weng
>>
> 
> Hi Weng,
> 
> It is quite a simple scheme, assume you have 2 write ports each writing 
> into their own blockram. If port0 write to address 0x12 and port1 writes 
> to address 0x15 then the LVT (single bit array in this case) will store 
> array[12]=0 and array[15]=1.
> Then if a read port read from address 15 the LVT array will set the mux 
> to 1 which connect the second blockram to the output.
> 
> I use the XOR variant in my processor for a 8w8r block.
> 
> Good luck,
> Hans
> www.ht-lab.com
> 

Although the kicker with this paper is in simultaneous reads.  They 
gloss pretty hard over the fact that (per the end of 5.3 and 5.4), for N 
write ports and M read ports, you need N*M redundant BRAMs.  For their 
example of a 4-write, 8-read RAM they're using 32-fold the actual RAM 
requirements.  Can't even take advantage of BRAM packing, since they use 
both ports of each RAM to keep one dedicated write port and one 
dedicated read.  32x is a hell of a multiplier to be fighting against; 
it'll chew up all the RAM in a cheap FPGA before you can bat an eye.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 161031
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: gnuarm.deletethisbit@gmail.com
Date: Mon, 14 Jan 2019 16:01:51 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 6:15:17 PM UTC-5, Rick C. Hodgin wrote:
> On Monday, January 14, 2019 at 5:42:37 PM UTC-5, gnuarm.del...@gmail.com =
wrote:
> > Our patent seeking friend fails to understand the very basic issue
> > of how a multi-write port RAM can operate.
>=20
> Always there with a pure heart of kindness, one given to teaching,
> apt to help compensate when someone is perhaps less than they should
> be.  Always accommodating, always uplifting, always at the ready to
> improve another's life, eh Rick?

I am happy to answer questions and provide advice to those who ask for it. =
 Sometimes the person finds it useful other times not.  I am not alone in o=
ffering the same sort of help to more than one person in this group.  But i=
t is often declined presumably because the person asking for help doesn't r=
eally want help as much as getting others to do their work for them. =20

  Rick C.

  + Get 6 months of free supercharging
  + Tesla referral code - https://ts.la/richard11209

Article: 161032
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: gnuarm.deletethisbit@gmail.com
Date: Mon, 14 Jan 2019 16:11:44 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 6:38:35 PM UTC-5, Rob Gaddi wrote:
> On 1/14/19 1:22 PM, HT-Lab wrote:
> > On 14/01/2019 19:54, Weng Tianxiang wrote:
> >> Hi,
> >>
> >> I cannot understand the following paper:
> >> "Efficient Multi-Ported Memories for FPGAs"
> >>
> >> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> >>
> >> FPGA has a structure with 1 write port and 2 read port memory block: 2=
=20
> >> memory blocks sharing the same write port and each of 2 blocks can be=
=20
> >> read individually by 2 different read.
> >>
> >> The paper essence for 2 write ports and 2 read ports is:
> >> There are 2 memory blocks each having 1 write port and 2 read ports.
> >>
> >> The 2 memory blocks provide 2 write ports to write independently.
> >>
> >> There is another memory block, called LVT (Live Value Table), with 2=
=20
> >> write ports and 2 read ports, each cell of which stores the port=20
> >> number which holds the latest write data.
> >>
> >> Example:
> >>
> >> simultaneously:
> >> Write through port 1 with address 3; --- no problem
> >>
> >> Write through port 0 with address 2;
> >>
> >> simultaneously:
> >> 0 --> LVT(2);
> >> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cyc=
le?
> >>
> >> If above 2 simultaneously write operation are feasible, 2 read=20
> >> operations can read from LVT first to get proper port number, and then=
=20
> >> get the correct latest data read from the port number.
> >>
> >> Thank you.
> >>
> >> Weng
> >>
> >=20
> > Hi Weng,
> >=20
> > It is quite a simple scheme, assume you have 2 write ports each writing=
=20
> > into their own blockram. If port0 write to address 0x12 and port1 write=
s=20
> > to address 0x15 then the LVT (single bit array in this case) will store=
=20
> > array[12]=3D0 and array[15]=3D1.
> > Then if a read port read from address 15 the LVT array will set the mux=
=20
> > to 1 which connect the second blockram to the output.
> >=20
> > I use the XOR variant in my processor for a 8w8r block.
> >=20
> > Good luck,
> > Hans
> > www.ht-lab.com
> >=20
>=20
> Although the kicker with this paper is in simultaneous reads.  They=20
> gloss pretty hard over the fact that (per the end of 5.3 and 5.4), for N=
=20
> write ports and M read ports, you need N*M redundant BRAMs.  For their=20
> example of a 4-write, 8-read RAM they're using 32-fold the actual RAM=20
> requirements.  Can't even take advantage of BRAM packing, since they use=
=20
> both ports of each RAM to keep one dedicated write port and one=20
> dedicated read.  32x is a hell of a multiplier to be fighting against;=20
> it'll chew up all the RAM in a cheap FPGA before you can bat an eye.

I'm not sure what your point is.  That is the nature of multiport memories.=
  If you need it, you need it.  They can be the performance limiting portio=
n of a design and so they would be very welcome at nearly any cost. =20

I seem to recall when Xilinx block rams had true quad port capability in th=
at they could read and write from two ports all at the same time.  There ma=
y have only been two address buses, I can't recall.  But the two write port=
s could operate simultaneously.  The only limitation was both ports could n=
ot write to the same address.=20

  Rick C.

  -- Get 6 months of free supercharging
  -- Tesla referral code - https://ts.la/richard11209

Article: 161033
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Mon, 14 Jan 2019 21:13:59 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 7:01:55 PM UTC-5, gnuarm.del...@gmail.com wr=
ote:
> On Monday, January 14, 2019 at 6:15:17 PM UTC-5, Rick C. Hodgin wrote:
> > On Monday, January 14, 2019 at 5:42:37 PM UTC-5, gnuarm.del...@gmail.co=
m wrote:
> > > Our patent seeking friend fails to understand the very basic issue
> > > of how a multi-write port RAM can operate.
> >=20
> > Always there with a pure heart of kindness, one given to teaching,
> > apt to help compensate when someone is perhaps less than they should
> > be.  Always accommodating, always uplifting, always at the ready to
> > improve another's life, eh Rick?
>=20
> I am happy to answer questions and provide advice to those who ask for it=
.  Sometimes the person finds it useful other times not.  I am not alone in=
 offering the same sort of help to more than one person in this group.  But=
 it is often declined presumably because the person asking for help doesn't=
 really want help as much as getting others to do their work for them. =20

Whoosh!

--=20
Rick C. Hodgin

Article: 161034
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for
From: HT-Lab <hans64@htminuslab.com>
Date: Tue, 15 Jan 2019 08:10:08 +0000
Links: << >>  << T >>  << A >>
On 14/01/2019 21:40, Weng Tianxiang wrote:
> On Monday, January 14, 2019 at 1:23:01 PM UTC-8, HT-Lab wrote:
>> On 14/01/2019 19:54, Weng Tianxiang wrote:
>>> Hi,
>>>
>>> I cannot understand the following paper:
>>> "Efficient Multi-Ported Memories for FPGAs"
>>>
>>> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
>>>
>>> FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
>>>
>>> The paper essence for 2 write ports and 2 read ports is:
>>> There are 2 memory blocks each having 1 write port and 2 read ports.
>>>
>>> The 2 memory blocks provide 2 write ports to write independently.
>>>
>>> There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
>>>
>>> Example:
>>>
>>> simultaneously:
>>> Write through port 1 with address 3; --- no problem
>>>
>>> Write through port 0 with address 2;
>>>
>>> simultaneously:
>>> 0 --> LVT(2);
>>> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
>>>
>>> If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
>>>
>>> Thank you.
>>>
>>> Weng
>>>
>>
>> Hi Weng,
>>
>> It is quite a simple scheme, assume you have 2 write ports each writing
>> into their own blockram. If port0 write to address 0x12 and port1 writes
>> to address 0x15 then the LVT (single bit array in this case) will store
>> array[12]=0 and array[15]=1.
>> Then if a read port read from address 15 the LVT array will set the mux
>> to 1 which connect the second blockram to the output.
>>
>> I use the XOR variant in my processor for a 8w8r block.
>>
>> Good luck,
>> Hans
>> www.ht-lab.com
> 
> Hi Hans,
> 
> "If port0 write to address 0x12 and port1 writes
> to address 0x15 then the LVT (single bit array in this case) will store
> array[12]=0 and array[15]=1. "
> 
> How do you do: 0 --> array[12], 1 --> array[15] on the same cycle?
> 
Hi Weng,

The LVT array is not a blockram but just a bank of FF's, so you can set 
multiple bits at the same time.

Regards,
Hans.



> Thank you.
> 
> Weng
> 


Article: 161035
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 15 Jan 2019 07:11:35 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

Here is my perfect answer to my question in VHDL and it has one copy and is capable for doing N writes and N reads at the same time:

signal R0, R1, ..., Rn_1 : std_logic_vector(BITS-1 downto 0);
  type NR_NW_TYPE : (0 to N-1) of unsigned(BITS-1 downto 0);
alias NR_NW : NR_NW_TYPE := (R0, R1, ..., Rn_1);

Now one can do N writes to any data and N reads from any data of NR_NW on the same cycle.

   A1 <= NR_NW(j); --> A1 <= Rj;

   NR_NW(j) <= B1; --> Rj <= B1;

Weng

Article: 161036
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 15 Jan 2019 07:18:15 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, January 15, 2019 at 7:11:39 AM UTC-8, Weng Tianxiang wrote:
> Hi,
> 
> Here is my perfect answer to my question in VHDL and it has one copy and is capable for doing N writes and N reads at the same time:
> 
> signal R0, R1, ..., Rn_1 : std_logic_vector(BITS-1 downto 0);
>   type NR_NW_TYPE : (0 to N-1) of unsigned(BITS-1 downto 0);
> alias NR_NW : NR_NW_TYPE := (R0, R1, ..., Rn_1);
> 
> Now one can do N writes to any data and N reads from any data of NR_NW on the same cycle.
> 
>    A1 <= NR_NW(j); --> A1 <= Rj;
> 
>    NR_NW(j) <= B1; --> Rj <= B1;
> 
> Weng

There are no limits on the number of reading and writing:

If 2 writes are for the same address one must arrange them in a same if-statement.

Weng 

Article: 161037
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Kevin Neilson <kevin.neilson@xilinx.com>
Date: Tue, 15 Jan 2019 08:25:15 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 12:54:36 PM UTC-7, Weng Tianxiang wrote:
> Hi,
> 
> I cannot understand the following paper:
> "Efficient Multi-Ported Memories for FPGAs" 
> 
> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> 
> FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
> 
> The paper essence for 2 write ports and 2 read ports is:
> There are 2 memory blocks each having 1 write port and 2 read ports.
> 
> The 2 memory blocks provide 2 write ports to write independently.
> 
> There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
> 
> Example:
> 
> simultaneously:
> Write through port 1 with address 3; --- no problem
> 
> Write through port 0 with address 2;
> 
> simultaneously:
> 0 --> LVT(2); 
> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
> 
> If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
> 
> Thank you.
> 
> Weng

There is another thread on this topic:  https://groups.google.com/forum/#!searchin/comp.arch.fpga/quad-port%7Csort:date/comp.arch.fpga/Xrj3m2V2GyY/t_MX_tf_DwAJ

I have a diagram here which shows how to make a 4-port RAM (2 writes, 2 reads) that keeps the semaphores in blockRAMs:  https://imgur.com/a/NhNr0

The diagram might be easier to understand than a long explanation. 

Article: 161038
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Kevin Neilson <kevin.neilson@xilinx.com>
Date: Tue, 15 Jan 2019 08:28:34 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 4:38:35 PM UTC-7, Rob Gaddi wrote:
> On 1/14/19 1:22 PM, HT-Lab wrote:
> > On 14/01/2019 19:54, Weng Tianxiang wrote:
> >> Hi,
> >>
> >> I cannot understand the following paper:
> >> "Efficient Multi-Ported Memories for FPGAs"
> >>
> >> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> >>
> >> FPGA has a structure with 1 write port and 2 read port memory block: 2 
> >> memory blocks sharing the same write port and each of 2 blocks can be 
> >> read individually by 2 different read.
> >>
> >> The paper essence for 2 write ports and 2 read ports is:
> >> There are 2 memory blocks each having 1 write port and 2 read ports.
> >>
> >> The 2 memory blocks provide 2 write ports to write independently.
> >>
> >> There is another memory block, called LVT (Live Value Table), with 2 
> >> write ports and 2 read ports, each cell of which stores the port 
> >> number which holds the latest write data.
> >>
> >> Example:
> >>
> >> simultaneously:
> >> Write through port 1 with address 3; --- no problem
> >>
> >> Write through port 0 with address 2;
> >>
> >> simultaneously:
> >> 0 --> LVT(2);
> >> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
> >>
> >> If above 2 simultaneously write operation are feasible, 2 read 
> >> operations can read from LVT first to get proper port number, and then 
> >> get the correct latest data read from the port number.
> >>
> >> Thank you.
> >>
> >> Weng
> >>
> > 
> > Hi Weng,
> > 
> > It is quite a simple scheme, assume you have 2 write ports each writing 
> > into their own blockram. If port0 write to address 0x12 and port1 writes 
> > to address 0x15 then the LVT (single bit array in this case) will store 
> > array[12]=0 and array[15]=1.
> > Then if a read port read from address 15 the LVT array will set the mux 
> > to 1 which connect the second blockram to the output.
> > 
> > I use the XOR variant in my processor for a 8w8r block.
> > 
> > Good luck,
> > Hans
> > www.ht-lab.com
> > 
> 
> Although the kicker with this paper is in simultaneous reads.  They 
> gloss pretty hard over the fact that (per the end of 5.3 and 5.4), for N 
> write ports and M read ports, you need N*M redundant BRAMs.  For their 
> example of a 4-write, 8-read RAM they're using 32-fold the actual RAM 
> requirements.  Can't even take advantage of BRAM packing, since they use 
> both ports of each RAM to keep one dedicated write port and one 
> dedicated read.  32x is a hell of a multiplier to be fighting against; 
> it'll chew up all the RAM in a cheap FPGA before you can bat an eye.
> 
> -- 
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
> Email address domain is currently out of order.  See above to fix.

I needed a 4-port RAM to do 2 read-modify-writes per cycle.  This quadrupled the blockRAM requirement.  It was totally worth it for that design.  It's not always worth it.

Article: 161039
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: gnuarm.deletethisbit@gmail.com
Date: Tue, 15 Jan 2019 08:36:02 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, January 15, 2019 at 10:18:19 AM UTC-5, Weng Tianxiang wrote:
> On Tuesday, January 15, 2019 at 7:11:39 AM UTC-8, Weng Tianxiang wrote:
> > Hi,
> > 
> > Here is my perfect answer to my question in VHDL and it has one copy and is capable for doing N writes and N reads at the same time:
> > 
> > signal R0, R1, ..., Rn_1 : std_logic_vector(BITS-1 downto 0);
> >   type NR_NW_TYPE : (0 to N-1) of unsigned(BITS-1 downto 0);
> > alias NR_NW : NR_NW_TYPE := (R0, R1, ..., Rn_1);
> > 
> > Now one can do N writes to any data and N reads from any data of NR_NW on the same cycle.
> > 
> >    A1 <= NR_NW(j); --> A1 <= Rj;
> > 
> >    NR_NW(j) <= B1; --> Rj <= B1;
> > 
> > Weng
> 
> There are no limits on the number of reading and writing:
> 
> If 2 writes are for the same address one must arrange them in a same if-statement.
> 
> Weng

I would like to see that code.  BTW, what is the point of the alias in your above description?  Why bother with the Rj notation at all? 

  Rick C.

  ++ Get 6 months of free supercharging
  ++ Tesla referral code - https://ts.la/richard11209

Article: 161040
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Kevin Neilson <kevin.neilson@xilinx.com>
Date: Tue, 15 Jan 2019 08:37:16 -0800 (PST)
Links: << >>  << T >>  << A >>
On Monday, January 14, 2019 at 5:11:48 PM UTC-7, gnuarm.del...@gmail.com wr=
ote:
> On Monday, January 14, 2019 at 6:38:35 PM UTC-5, Rob Gaddi wrote:
> > On 1/14/19 1:22 PM, HT-Lab wrote:
> > > On 14/01/2019 19:54, Weng Tianxiang wrote:
> > >> Hi,
> > >>
> > >> I cannot understand the following paper:
> > >> "Efficient Multi-Ported Memories for FPGAs"
> > >>
> > >> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> > >>
> > >> FPGA has a structure with 1 write port and 2 read port memory block:=
 2=20
> > >> memory blocks sharing the same write port and each of 2 blocks can b=
e=20
> > >> read individually by 2 different read.
> > >>
> > >> The paper essence for 2 write ports and 2 read ports is:
> > >> There are 2 memory blocks each having 1 write port and 2 read ports.
> > >>
> > >> The 2 memory blocks provide 2 write ports to write independently.
> > >>
> > >> There is another memory block, called LVT (Live Value Table), with 2=
=20
> > >> write ports and 2 read ports, each cell of which stores the port=20
> > >> number which holds the latest write data.
> > >>
> > >> Example:
> > >>
> > >> simultaneously:
> > >> Write through port 1 with address 3; --- no problem
> > >>
> > >> Write through port 0 with address 2;
> > >>
> > >> simultaneously:
> > >> 0 --> LVT(2);
> > >> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same c=
ycle?
> > >>
> > >> If above 2 simultaneously write operation are feasible, 2 read=20
> > >> operations can read from LVT first to get proper port number, and th=
en=20
> > >> get the correct latest data read from the port number.
> > >>
> > >> Thank you.
> > >>
> > >> Weng
> > >>
> > >=20
> > > Hi Weng,
> > >=20
> > > It is quite a simple scheme, assume you have 2 write ports each writi=
ng=20
> > > into their own blockram. If port0 write to address 0x12 and port1 wri=
tes=20
> > > to address 0x15 then the LVT (single bit array in this case) will sto=
re=20
> > > array[12]=3D0 and array[15]=3D1.
> > > Then if a read port read from address 15 the LVT array will set the m=
ux=20
> > > to 1 which connect the second blockram to the output.
> > >=20
> > > I use the XOR variant in my processor for a 8w8r block.
> > >=20
> > > Good luck,
> > > Hans
> > > www.ht-lab.com
> > >=20
> >=20
> > Although the kicker with this paper is in simultaneous reads.  They=20
> > gloss pretty hard over the fact that (per the end of 5.3 and 5.4), for =
N=20
> > write ports and M read ports, you need N*M redundant BRAMs.  For their=
=20
> > example of a 4-write, 8-read RAM they're using 32-fold the actual RAM=
=20
> > requirements.  Can't even take advantage of BRAM packing, since they us=
e=20
> > both ports of each RAM to keep one dedicated write port and one=20
> > dedicated read.  32x is a hell of a multiplier to be fighting against;=
=20
> > it'll chew up all the RAM in a cheap FPGA before you can bat an eye.
>=20
> I'm not sure what your point is.  That is the nature of multiport memorie=
s.  If you need it, you need it.  They can be the performance limiting port=
ion of a design and so they would be very welcome at nearly any cost. =20
>=20
> I seem to recall when Xilinx block rams had true quad port capability in =
that they could read and write from two ports all at the same time.  There =
may have only been two address buses, I can't recall.  But the two write po=
rts could operate simultaneously.  The only limitation was both ports could=
 not write to the same address.=20
>=20
>   Rick C.
>=20
>   -- Get 6 months of free supercharging
>   -- Tesla referral code - https://ts.la/richard11209

You could consider the Xilinx BRAMs true quad port, if you set both ports t=
o READ_FIRST, with the limitation that there are only 2 address buses and y=
ou have to read from the same address to which you are writing.  Most of th=
e time you want to read from some address other than the one to which you a=
re writing.

When I was trying to make a true quad port (4 addresses) I found a Xilinx a=
pp note (XAPP228) on making a BRAM-based quad port.  I was excited I wouldn=
't have to design one from scratch.  I opened the app note and saw it descr=
ibed how to double the clock and use timeslicing to make extra virtual port=
s.  Thanks, Xilinx!  Like I needed an app note for that.  No problem; I'll =
just double my 350MHz clock to 700MHz.

Article: 161041
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Tue, 15 Jan 2019 09:04:24 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, January 15, 2019 at 11:29:49 AM UTC-5, gnuarm.del...@gmail.com wrote:
> On Tuesday, January 15, 2019 at 7:58:15 AM UTC-5, Rick C. Hodgin wrote:
> > That was the sound of my point in the prior post flying right past you.
> 
> [snip]

My point is ... be nice and respectful of people, even if you think
they are not what they should be in terms of knowledge or ability.

-- 
Rick C. Hodgin

Article: 161042
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: gnuarm.deletethisbit@gmail.com
Date: Tue, 15 Jan 2019 09:58:23 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, January 15, 2019 at 12:04:28 PM UTC-5, Rick C. Hodgin wrote:
> On Tuesday, January 15, 2019 at 11:29:49 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Tuesday, January 15, 2019 at 7:58:15 AM UTC-5, Rick C. Hodgin wrote:
> > > That was the sound of my point in the prior post flying right past you.
> > 
> > [snip]
> 
> My point is ... be nice and respectful of people, even if you think
> they are not what they should be in terms of knowledge or ability.

Yes, you might take your own advice.  That is the thing about you Hodgin's.  You sincerely believe you are holier than thou.  Try looking at the world through other people's glasses and you will see that you yourself are the troll here.  

Just consider the purpose of your first post in this thread.  Clearly it wasn't for the benefit of anyone else.  Tell us what benefit you hoped to gain by it? 

If you could just lose the pious attitude you might be able to learn something here. 

  Rick C.

  --- Get 6 months of free supercharging
  --- Tesla referral code - https://ts.la/richard11209

Article: 161043
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: "Rick C. Hodgin" <rick.c.hodgin@gmail.com>
Date: Tue, 15 Jan 2019 11:43:19 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, January 15, 2019 at 2:21:34 PM UTC-5, gnuarm.del...@gmail.com wrote:
> ... The simple fact that you judge me shows you feel you are a
> "better" person than I am.

No, sir.  We are called to teach people where they are, and what
it means.

https://tinyurl.com/ybrnwljs

-- 
Rick C. Hodgin

Article: 161044
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 15 Jan 2019 12:32:37 -0800 (PST)
Links: << >>  << T >>  << A >>

> My point is ... be nice and respectful of people, even if you think
> they are not what they should be in terms of knowledge or ability.
> 
> -- 
> Rick C. Hodgin

Hi Rick C. Hodgin,

1. I am standing for your opinion: be nice and respectful of people!

2. And I appreciate your 3 excellent references very much. 

By your 3 references I think everyone who read this post really learned from you and fully understands the solution to my post.

Thank you.

Weng


Article: 161045
Subject: Re: initializing a small array in Verilog
From: David Bridgham <dab@froghouse.org>
Date: Tue, 15 Jan 2019 15:45:13 -0500
Links: << >>  << T >>  << A >>
On 1/13/19 12:28 PM, Kevin Neilson wrote:

> 
> That does not look like it should work.  If you set the tool to SystemVeriliog mode you should be able to initialize the reg like this:
> 
>    reg [1:0] ip_list [0:3] = '{ 2'd2, 2'd1, 2'd0, 2'd1 };  // note extra tick
> 
> In Verilog-2005 mode, I think you should only be able to set the unpacked elements individually or with $readmemh.

Neither $readmemh nor setting the entries individually are particularly
appealing so I guess it's time to learn about SystemVerilog.

And, in fact, I've been reading up on it since seeing your response.
Enums and structs, I should have looked into this before.  I could like
this language.

So that extra single quote you added, what are the semantics of that?  I
see it often enough in examples when I'm reading about SystemVerilog but
I have yet to find anything that describes what it actually means.

Thanks,
Dave


Article: 161046
Subject: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 15 Jan 2019 14:22:33 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

Kevin Neilson's suggestion leads to a very good paper on the subject:

http://ece.ubc.ca/~ameer/publications/Abdelhadi-Journal-2015Jul-TRETSCode20=
14-SwitchedMultiportedRAM.pdf

"Modular Switched Multi-ported SRAM-based Memories"

"In this paper, to reduce this area overhead, two methods of constructing S=
RAM-based LVTs are described. The methodology of constructing SRAM-based LV=
Ts is also generalized. To the authors=E2=80=99 best knowledge this is the =
first attempt to build an LVT out of SRAM blocks only"

The paper provides a lot of schematic diagrams which make reading much easi=
er and faster for understanding the paper's essence.

Weng




Article: 161047
Subject: Re: initializing a small array in Verilog
From: Kevin Neilson <kevin.neilson@xilinx.com>
Date: Wed, 16 Jan 2019 12:03:33 -0800 (PST)
Links: << >>  << T >>  << A >>
SystemVerilog is great if your tools support it.  Most synthesis tools have=
 at least some support.  Unfortunately the stuff I write has to be support =
a lot of different tools, some of which are very primitive, so I'm stuck wi=
th Verilog-2005 and sometimes even that is too advanced.

I think the extra tick is to show that you are referring to an "unpacked" d=
imension (one specified on the right of the variable name).  You can also i=
nitialize multiple unpacked dimensions, something like this:

  reg [1:0] ip_list [0:1][0:3] =3D '{  '{2'd2, 2'd1, 2'd0, 2'd1 }, '{2'd2, =
2'd1, 2'd0, 2'd1 } };  // tick for each unpacked group

I don't think you need to specify the size of the packed elements since the=
y will be sized to the packed dimension:

  reg [1:0] ip_list [0:1][0:3] =3D '{  '{2, 1, 0, 1 }, '{2, 1, 0, 1 } };  /=
/ packed elements resized to 2 bits

There is also an unordered syntax that lets you specify just some elements =
and in whatever order you'd like.  It's something like this:

  reg [1:0] ip_list [0:3] =3D '{1:2, 3:2, default:0}; // ip_list[1]=3D2, ip=
_list[3]=3D2, others=3D0


Article: 161048
Subject: Altera Cyclone replacement
From: Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid>
Date: Fri, 25 Jan 2019 15:58:54 +0100
Links: << >>  << T >>  << A >>
Hi,

We got an old design with an Altera Cyclone FPGA (EP1C12F324).
These are probably obsolete (Can't find any info on them on the Intel
site, Farnell is out of stock, etc.). Currently active are the Cyclone-IV
and Cyclone-V if I understood correctly.

Is a design from a Cyclone portable to a Cyclone-IV/V? What kind of
changes should I expect to code and board? Design includes NIOS.

Or alternatively, are their sources for these old Cyclone chips?
(We actually would need 3 different types :-( )


-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

There is never time to do it right, but always time to do it over.

Article: 161049
Subject: Re: Altera Cyclone replacement
From: HT-Lab <hans64@htminuslab.com>
Date: Fri, 25 Jan 2019 15:56:18 +0000
Links: << >>  << T >>  << A >>
On 25/01/2019 14:58, Stef wrote:
> Hi,
> 
> We got an old design with an Altera Cyclone FPGA (EP1C12F324).
> These are probably obsolete (Can't find any info on them on the Intel
> site, Farnell is out of stock, etc.). Currently active are the Cyclone-IV
> and Cyclone-V if I understood correctly.
> 
> Is a design from a Cyclone portable to a Cyclone-IV/V? What kind of
> changes should I expect to code and board? Design includes NIOS.
> 
> Or alternatively, are their sources for these old Cyclone chips?
> (We actually would need 3 different types :-( )
> 
> 
Hi Stef,

Try www.octopart.com, there are several distributors that still have 
some types in stock.

Good luck,
Hans
www.ht-lab.com




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search