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There's a spectrum of implementations, but one methodology is: - code in HDL, simulate, etc. - hand layout the crucial parts - register banks, ALUs, etc. - extract the circuit and timing from the hand layout and check for equivalence. Hand layout is expensive even with good tooling, circuit extraction ditto, so getting as much as possible to go automatically from HDL to silicon matters to most companies. On 02/07/2019 16:34, Benjamin Couillard wrote: > I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. > > For example, if they implement an ALU. Do they implement the ALU on an RTL-level or do they instantiate hand-optimized components (adder, barrel shifter, multiplier). > > Basically, does the synthesizer actually do something or does it only connect hand-optimized components? > > Regards >Article: 161401
I normally work in fields like GF(2^8) or GF(2^11) (or, for AES, GF(2^128))= but all the operations decompose into GF(2) operations. For example, to d= o a x b =3D c in GF(2^8), all these values are 8-bit vectors. You can expa= nd b into an 8x8-bit matrix B in which b is the bottom row, b*alpha is the = next row up, and b*alpha**7 is the top row, where alpha is the primitive el= ement of the field. Then you multiply a x B using GF(2) to get the bits of= c. So all the operations of a characteristic-2 field (based on a power of= 2) can be broken down into GF(2) operations. I always break down matrices in larger fields to GF(2) matrices to make it = easier on the synthesizer. It can get bogged down otherwise.Article: 161402
On 06/07/2019 17:38, Kevin Neilson wrote: > I normally work in fields like GF(2^8) or GF(2^11) (or, for AES, > GF(2^128)) but all the operations decompose into GF(2) operations. > For example, to do a x b = c in GF(2^8), all these values are 8-bit > vectors. You can expand b into an 8x8-bit matrix B in which b is the > bottom row, b*alpha is the next row up, and b*alpha**7 is the top > row, where alpha is the primitive element of the field. Then you > multiply a x B using GF(2) to get the bits of c. So all the > operations of a characteristic-2 field (based on a power of 2) can be > broken down into GF(2) operations. > > I always break down matrices in larger fields to GF(2) matrices to > make it easier on the synthesizer. It can get bogged down > otherwise. > Thanks for that information. I did not know GF(2^8) calculations could be done by matrices over GF(2) like that, but it makes sense. I have only used the field in software - it is key to RAID6 and higher RAID versions - and there you do the multiplication and division using log tables.Article: 161403
I could see how the log tables might be better in software, but in hardware= a pair of log/antilog lookup tables (and a mod 2**m-1 adder) will normally= be bigger and slower than a hardware multiplier, especially as m gets bigg= er (where the field is GF(2**m)). I do use lookup tables for reciprocals, = but above some m, tables become inefficient for that as well.Article: 161404
On Monday, October 20, 2008 at 10:54:20 AM UTC-7, Mike Treseler wrote: > Jan wrote: > > Dear all, > > > > What are the smartest way to make a solo FPGA project capable of field > > updates? I'm very new in the FPGA world so I don't much about the > > practical use of them. Normally when I uses microcontrollers I make them > > updateble via USB, serial or SD cards. > > That's the way to do it. > Save multiple images in flash. > The uP handles networking and > loading images to flash and fpga. > > > What techniques are possible when I want to avoid having a uP in the > > project. > > You could put the project > on a pci[e] card and have > the host pc do the updates. > > -- Mike Treseler There are small FPGAs with dual flash that simplify the field upgrade. Look at Lattice MachXO2 or Intel MAX10.Article: 161405
FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules?Article: 161406
On Mon, 08 Jul 2019 09:40:49 -0700, camil.matiska wrote: > On Monday, October 20, 2008 at 10:54:20 AM UTC-7, Mike Treseler wrote: >> Jan wrote: >> > Dear all, >> > >> > What are the smartest way to make a solo FPGA project capable of >> > field updates? Xilinx FPGAs can be loaded by serial EPROMS with no external circuits. Xilinx's own SPROMS are really expensive but I use the SST family, I think now sold by Atmel. The 1 mbit one I use is $0.89 in small quantity. One downside is they don't make a DIP version, so I solder them to a little adapter board, that fits an 8-pin DIP socket. Of course, you can use an external flash ROM or something like the Spartan 3 AN with internal flash chip. These can be programmed via a JTAG tap. JonArticle: 161407
On 2019-07-08 camil.matiska@gmail.com wrote in comp.arch.fpga: > FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules? In my experience FPGAs don't have very good optical properties, but YMMV. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) One family builds a wall, two families enjoy it.Article: 161408
Altera had a prototype of FPGA with fiber connection to the silicon. <camil.matiska@gmail.com> wrote in message news:bff76d67-6c88-4255-a170-7f91f52a7359@googlegroups.com... > FPGAs are used in a wide variety of applications from automotive to > computing and space. Why are they not used inside optical modules?Article: 161409
It looks like Lattice has announced a new FPGA product that suits my needs.= I've always preferred non-BGA devices because they complicate the PCB fab= rication with the need for fine pitch and very small vias. These devices s= eem to be aimed at products requiring high security, but the other aspects = suit me to a tee. =20 There are two size devices, about 4000 LUTs and about 9000 LUTs. Both devi= ces are available in a 72 pin QFP with 0.5 mm pitch. =20 I've asked for pricing and schedule.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209Article: 161410
Hi, for field update we use the FPGA Programmer from FPGA Cores: http://www.fpga-cores.com/ We have used this for Spartan 6 and Artix.Article: 161411
On Monday, 8 July 2019 19:45:26 UTC+1, camil....@gmail.com wrote: > FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules? They are used in SFPs, eg https://www.embrionix.com/Article: 161412
On Thursday, July 25, 2019 at 6:41:58 AM UTC-4, Edward Moore wrote: > On Monday, 8 July 2019 19:45:26 UTC+1, camil....@gmail.com wrote: > > FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules? > > They are used in SFPs, eg https://www.embrionix.com/ Are SFPs used for interfaces other than fiber? I see in Wikipedia that 1000 and 100BASE copper is supported. What about other such as T1/E1 or serial port circuits? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209Article: 161413
On Tuesday, July 9, 2019 at 2:45:26 AM UTC+8, camil....@gmail.com wrote: > FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules? What do you think about PYNQ? Zynq can be used easily for machine learning. http://www.pynq.io/mlArticle: 161414
Rick C <gnuarm.deletethisbit@gmail.com> wrote: > Are SFPs used for interfaces other than fiber? I see in Wikipedia that 1000 and 100BASE copper is supported. What about other such as T1/E1 or serial port circuits? SFPs are ethernet PHYs. There are PHYs for twisted pair (RJ45), and passive direct attach copper cables (SFP on each end). T1/E1 and serial ports aren't ethernet. I suppose in principle someone could do a 10BASE2 or 10BASE5 SFP, but they don't seem to exist. TheoArticle: 161415
On Fri, 26 Jul 2019 12:23:57 +0100, Theo wrote: > Rick C <gnuarm.deletethisbit@gmail.com> wrote: >> Are SFPs used for interfaces other than fiber? I see in Wikipedia that >> 1000 and 100BASE copper is supported. What about other such as T1/E1 >> or serial port circuits? > > SFPs are ethernet PHYs. There are PHYs for twisted pair (RJ45), and > passive direct attach copper cables (SFP on each end). T1/E1 and serial > ports aren't ethernet. > > I suppose in principle someone could do a 10BASE2 or 10BASE5 SFP, but > they don't seem to exist. > > Theo Pffft. SFPs, as defined by their SFF, are independent of Ethernet. The vast majority of SFPs are little more than a laser, a photodiode, amplifiers and a control/monitoring circuit. This makes them protocol agnostic, and they work quite well for any optical protocol, such as SONET or Fibrechannel within their bitrate range. Some SFPs (they're in the minority) contain active electronics that will terminate Ethernet (in the form of SGMII, 1000Base-X or 10GBase-X) protocol on the electrical interface side, and convert it to something else. There are many "something elses". I've used ones that convert to: E1 DS3 1000Base-T N-Base-T 10GBase-T There are also SFPs that convert digital video to Ethernet. See this company for example: https://www.embrionix.com/ Let's not forget Pasive DACs (Direct Attach Cables). These are basically two twinax cables with an SFP on each end (and also AC coupling caps, an EEPROM, but typically no microcontroller). The range is limited to a couple of meters or so at 10Gb/s, but they're the cheapest way to link equipment in a rack. Active DACs are like passive DACs but contain amplifiers, to attain more range (some meters). Regards, AllanArticle: 161416
On Friday, July 26, 2019 at 7:24:03 AM UTC-4, Theo wrote: > Rick C <gnuarm.deletethisbit@gmail.com> wrote: > > Are SFPs used for interfaces other than fiber? I see in Wikipedia that 1000 and 100BASE copper is supported. What about other such as T1/E1 or serial port circuits? > > SFPs are ethernet PHYs. There are PHYs for twisted pair (RJ45), and passive > direct attach copper cables (SFP on each end). T1/E1 and serial ports > aren't ethernet. > > I suppose in principle someone could do a 10BASE2 or 10BASE5 SFP, but they > don't seem to exist. I could be mistaken but I thought a colleague showed me a unit that brought in T1/E1. I could be mistaken. 10BASE2 and 10BASE5 are older technologies that are not so widely used. 10/100BASE-T is much more common and SFP units are available. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209Article: 161417
On Thursday, 25 July 2019 17:24:24 UTC+1, Rick C wrote: > On Thursday, July 25, 2019 at 6:41:58 AM UTC-4, Edward Moore wrote: > > On Monday, 8 July 2019 19:45:26 UTC+1, camil....@gmail.com wrote: > > > FPGAs are used in a wide variety of applications from automotive to computing and space. Why are they not used inside optical modules? > > > > They are used in SFPs, eg https://www.embrionix.com/ > > Are SFPs used for interfaces other than fiber? I see in Wikipedia that 1000 and 100BASE copper is supported. What about other such as T1/E1 or serial port circuits? > > -- > > Rick C. > > - Get 1,000 miles of free Supercharging > - Tesla referral code - https://ts.la/richard11209 The company i mentioned do SFPs for SDI over copper, using mini-BNC or DIN connectors. The idea being that you can start off with cheap copper and transition to more expensive fibre. They also do SDI to HDMI SFPs.Article: 161418
Rick C <gnuarm.deletethisbit@gmail.com> writes: >On Friday, July 26, 2019 at 7:24:03 AM UTC-4, Theo wrote: >> Rick C <gnuarm.deletethisbit@gmail.com> wrote: >> > Are SFPs used for interfaces other than fiber? I see in Wikipedia that 1000 and 100BASE copper is supported. What about other such as T1/E1 or serial port circuits? >> >> SFPs are ethernet PHYs. There are PHYs for twisted pair (RJ45), and passive >> direct attach copper cables (SFP on each end). T1/E1 and serial ports >> aren't ethernet. >> >> I suppose in principle someone could do a 10BASE2 or 10BASE5 SFP, but they >> don't seem to exist. >I could be mistaken but I thought a colleague showed me a unit that brought in T1/E1. I could be mistaken. https://www.rad.com/products/Pluggable-PNFs-SFPs/MiRICi-E1-T1-MiRICi-E3-T3-Miniature-Ethernet-to-E3-T3-Remote-Bridge >10BASE2 and 10BASE5 are older technologies that are not so widely used. Not so widely used? I'd dare say they are extinct. Of course one might actually find either used in the field, but it'll be a million-to-one find. Sort of like finding that Amiga still controlling the school's HVAC or whatever. Average time of a T connector on a 10BASE2 networking flaking out was measured in months, it would be miraculous if you found a complete network working. -- Doug McIntyre doug@themcintyres.usArticle: 161419
Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to wait by a clock period to get a compile-time integer. https://www.xilinx.com/support/answers/57964.html is from 2014. Five years. In five years, Xilinx has remained unable to perform simple division. Absolutely embarrassing. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 161420
On Friday, August 9, 2019 at 1:49:59 PM UTC-4, Rob Gaddi wrote: > Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado > remains unable to successfully divide an amount of time you want to wait by a > clock period to get a compile-time integer. > > https://www.xilinx.com/support/answers/57964.html is from 2014. Five years. In > five years, Xilinx has remained unable to perform simple division. Absolutely > embarrassing. Obviously Xilinx customers aren't asking for it. After all, Xilinx is very responsive to their customers, no? Any other limitations that are issues? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209Article: 161421
Why differences between Merly-type and Moore-type clock-gated state machines are important on how to stop clocking? I need help to understand a puzzle: Merly-type state machine generates outputs which depend on inputs to the state machine and the current states of the state machine, while Moore-type state machine generates outputs which depend only on the current states of the state machine. Am I right if I treat a Merly-type state machine as a Moore-type state machine plus an independent combinational logic which has the same inputs to the state machine and the Moore-type state machine's state outputs? If I am right, why the paper "Automatic synthesis of lower power gated-clock finite state machine" https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss6Jun96pg630.pdf says (p.632, 2nd column, last section) "The knowledge of the state and the input is not sufficient to individuate the conditions when the clock can be stopped." Thank you. WengArticle: 161422
On Friday, August 9, 2019 at 4:53:12 PM UTC-4, Weng Tianxiang wrote: > Why differences between Merly-type and Moore-type clock-gated state machi= nes are important on how to stop clocking? >=20 > I need help to understand a puzzle: >=20 > Merly-type state machine generates outputs which depend on inputs to the = state machine and the current states of the state machine, while Moore-type= state machine generates outputs which depend only on the current states of= the state machine.=20 > Am I right if I treat a Merly-type state machine as a Moore-type state m= achine plus an independent combinational logic which has the same inputs to= the state machine and the Moore-type state machine's state outputs?=20 > If I am right, why the paper "Automatic synthesis of lower power gated-cl= ock finite state machine"=20 > https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss6J= un96pg630.pdf=20 > says (p.632, 2nd column, last section) "The knowledge of the state and th= e input is not sufficient to individuate the conditions when the clock can = be stopped." I believe any Moore type FSM can be converted to any Mealy type FSM and vic= e versa. That would imply that the two types of FSM should be equivalent i= n this consideration. =20 However, your question actually has nothing to do with the distinction of t= he two types of FSM. =20 I would also point out the definition of the Mealy type FSM is often not we= ll specified. While they define it as having outputs dependent on the inpu= ts as well as the state, I find they are usually implemented with registere= d outputs. This effectively makes them Moore type FSM even if those output= s are not provided as inputs to the FSM logic. =20 The paper PDF file does not allow copying of text, so I won't go into this = much, but this paper has fundamental errors I believe. For one, they menti= on there are "conditions such that the outputs and next state do not change= ". Then they go on to say stopping the clock will save power in the combin= ational logic because the outputs of registers are prevented from changing.= What registers would those be??? If the outputs and registers are not ch= anging, what would be changing that would make the combinational logic cons= ume power???=20 Finally, I would submit it is very easy to determine if a FF should be cloc= ked or not. Simply compare the D input to the Q output. If they are the s= ame, gate the clock. If they are different enable the clock. BTW, this ef= fectively turns the D FF into a toggle FF.=20 Isn't this whole thing a bit of a DUH! Not very patentable since it is obv= ious to anyone skilled in the field. =20 BTW, how is the wave pipelining thing going?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209Article: 161423
On Friday, August 9, 2019 at 3:32:29 PM UTC-7, Rick C wrote: > On Friday, August 9, 2019 at 4:53:12 PM UTC-4, Weng Tianxiang wrote: > > Why differences between Merly-type and Moore-type clock-gated state mac= hines are important on how to stop clocking? > >=20 > > I need help to understand a puzzle: > >=20 > > Merly-type state machine generates outputs which depend on inputs to th= e state machine and the current states of the state machine, while Moore-ty= pe state machine generates outputs which depend only on the current states = of the state machine.=20 > > Am I right if I treat a Merly-type state machine as a Moore-type state= machine plus an independent combinational logic which has the same inputs = to the state machine and the Moore-type state machine's state outputs?=20 > > If I am right, why the paper "Automatic synthesis of lower power gated-= clock finite state machine"=20 > > https://si2.epfl.ch/~demichel/publications/archive/1996/CADICSvol15iss= 6Jun96pg630.pdf=20 > > says (p.632, 2nd column, last section) "The knowledge of the state and = the input is not sufficient to individuate the conditions when the clock ca= n be stopped." >=20 > I believe any Moore type FSM can be converted to any Mealy type FSM and v= ice versa. That would imply that the two types of FSM should be equivalent= in this consideration. =20 >=20 > However, your question actually has nothing to do with the distinction of= the two types of FSM. =20 >=20 > I would also point out the definition of the Mealy type FSM is often not = well specified. While they define it as having outputs dependent on the in= puts as well as the state, I find they are usually implemented with registe= red outputs. This effectively makes them Moore type FSM even if those outp= uts are not provided as inputs to the FSM logic. =20 >=20 > The paper PDF file does not allow copying of text, so I won't go into thi= s much, but this paper has fundamental errors I believe. For one, they men= tion there are "conditions such that the outputs and next state do not chan= ge". Then they go on to say stopping the clock will save power in the comb= inational logic because the outputs of registers are prevented from changin= g. What registers would those be??? If the outputs and registers are not = changing, what would be changing that would make the combinational logic co= nsume power???=20 >=20 > Finally, I would submit it is very easy to determine if a FF should be cl= ocked or not. Simply compare the D input to the Q output. If they are the= same, gate the clock. If they are different enable the clock. BTW, this = effectively turns the D FF into a toggle FF.=20 >=20 > Isn't this whole thing a bit of a DUH! Not very patentable since it is o= bvious to anyone skilled in the field. =20 >=20 > BTW, how is the wave pipelining thing going?=20 >=20 > --=20 >=20 > Rick C. >=20 > - Get 1,000 miles of free Supercharging > - Tesla referral code - https://ts.la/richard11209 Hi Rick, Thank you very much! I fully agree with your opinion, especially your follo= wing opinion: >Simply compare the D input to the Q output. If they are the same, gate th= e clock. If they are different enable the clock. BTW, this effectively tu= rns the D FF into a toggle FF.=20 WengArticle: 161424
On Friday, August 9, 2019 at 1:49:59 PM UTC-4, Rob Gaddi wrote: > Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Viva= do=20 > remains unable to successfully divide an amount of time you want to wait = by a=20 > clock period to get a compile-time integer. >=20 Well, when the numbers get too big apparently... > https://www.xilinx.com/support/answers/57964.html is from 2014. Five yea= rs. In=20 > five years, Xilinx has remained unable to perform simple division. Absol= utely=20 > embarrassing. You're not representing that post accurately. The post showed four example= s of time divided by time and it appears that three of the four did synthes= ize properly. Only in the fourth case, 1000000 ns / 25 ns is a warning gen= erated by the tool and the synthesis fails. That would hardly qualify as "= remained unable to perform simple division" in my book. They do go on to say "Using time for integer calculations should be avoided= and is not a recommended coding style supported by Vivado Synthesis.". Th= e stated rationale is "Vivado Synthesis has a limitation to the precision t= hat is supported for time that goes in accordance with the LRM" but it's no= t clear what part of the LRM they are discussing or which range of time Viv= ado does accept. At least they do recognize it as a deficiency, they are k= icking out a warning message so kudos there. But I agree that the suggeste= d work around is weak. The lack of a defined time range that is supported = is also weak (unless it is mentioned in the documentation, I'm only looking= at the post). It's also not clear either whether if it had been written 'smaller' numbers= if it would have worked (such as 1 sec / 25 ns) but I'm guessing not. Kevin Jennings
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