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> Not so easy as you think as the content of the ROM has a very strong influence on the result. > > Assume a simple ROM content with 50% '0' and 50% '1' > > Bit 3210 > ------------- > Adr 000: 0000 > Adr 001: 1010 > Adr 010: 1100 > Adr 011: 1110 > Adr 100: 1000 > Adr 101: 1010 > Adr 110: 1100 > Adr 111: 1111 Maybe I should have specified that depth D is large. A formula will not be accurate for tiny ROMs but should be as D increases.Article: 160926
To all: May your year finish well, and your 2019 be even brighter. Merry Christmas / Happy Holidays to all who celebrate this time of year. -- Rick C. HodginArticle: 160927
On 12/21/2018 11:44 AM, Rick C. Hodgin wrote: > To all: > > May your year finish well, and your 2019 be even brighter. > > Merry Christmas / Happy Holidays to all who celebrate this time of year. > Merry Christmas Rick. :^)Article: 160928
On Sunday, December 16, 2018 at 9:16:40 AM UTC-5, KJ wrote: > On Saturday, December 15, 2018 at 11:28:47 PM UTC-5, gnuarm.del...@gmail.= com=20 > >=20 > > I have no idea what "cut off" means. =20 > >=20 > Weng is upset that his original three state machine can actually be imple= mented with a single state. States 'S1' and 'S2' in that sense were cut of= f because they were useless. >=20 > >=20 > > If you are actually talking about the next_state equations rather than = what appeared to be an intermediate signal that may or may not exist in any= given design, what are your questions exactly?=20 > >=20 > I don't think he has any actual questions. Weng tends to present claims = that tend to be false but insists they are true. That's his delusion to re= solve. >=20 > Weng also tends to post code that is not representative of the code that = he bases his claim upon. That was the case here where he based his claim o= n code that did not have the "elsif C2" branch in it. Take that branch out= and you have a one-hot encoded single input state machine which has alread= y been pointed out to him to be the special case where his statement is in = some sense true. However, the 'S0_C1' signal that he crows about is really= just the next state...so what? Isn't Weng the same guy who couldn't understand that for wave pipelining to= work delays had to be bracketed rather than the max spec they give in FPGA= s? =20 I seem to recall a fairly long argument about that fact. I wonder if he ev= er got any sort of a patent out of that?=20 Rick C.=20 Tesla referral code --+ https://ts.la/richard11209 Get 6 months of free superchargingArticle: 160929
On Thursday, December 6, 2018 at 6:02:25 PM UTC-5, Kevin Neilson wrote: > I've searched for this but to no avail. I'd like a function f(D,W), wher= e D=3Ddepth and W=3Dwidth, which provides an estimate of the gate count of = a lookup ROM implemented in ASIC gates. >=20 > Yes, I know it's dependent on the contents. However, if half the bits ar= e ones and the contents are randomly distributed, a formula should be prett= y accurate. >=20 > It's easy for me to figure out an upper limit. A basic ROM is an AND-OR = array. The D address decoders (comprising ANDs/NOTs) can be shared amongst= the W columns. Each of the W columns would require D/2-1 OR gates if half= the ROM bits in each column are 1. >=20 > What I don't know is how many gates can be eliminated by sharing terms. = As W increases, term sharing should go up. Again, I'm looking for a *formu= la*. That would be pretty easy. Consider the costs of a D wide multiplexer with= 1 or 0 on each input. That would be an upper bound in any case. =20 I believe my text book of many years ago used one of the input variables in= either true or inverted form combined with 1s and 0s as choices for inputs= which simplified the mux by one address input. =20 Rick C.=20 Tesla referral code - https://ts.la/richard11209 Get 6 months of free superchargingArticle: 160930
Hi Thomas, > S0_C1 <=3D not SINI and WState =3D S0 and C1;=20 "This equivalent code will not necessarily generate a signal "xx <=3D not S= INI and WState =3D S0 and C1" after synthesis. It will have this signal in = an synthesis intermediate state but after logic optimisation this signal ca= n be removed in favor of simplified functionality depending on the complete= FSM transition logic. " You are right. I never say the S0_C1 will be the final logic, but says that= the signal must appear during the synthesization. Rick, 1. Systematic method of coding wave-pipelined circuits in HDL Patent #: 9-747-252 B2 Issue date: 2017-08-29 Allowance date: 2017-06-27 Filing data: 02/05/2016 2. Apparatus of wave-pipelined circuits Patent #: 9-575-929 B2 Issue date: 2017-02-21 Allowance date: 2016-12-21 Filing data: 02/05/2016 3. Systematic method of synthesizing wave-pipelined circuits in HDL Patent #: 9-734-127 B2 Issue date: 2017-08-15 Allowance date: 2017-06-19 Filing data: 02/05/2016 I think someday they will be introduced into HDL standard. Google reviewed the applications since 2015/02/18, and finally made a rejec= tion for the offer on 2018/03/16, 7 months after they became patents. WengArticle: 160931
On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote: > Hi Thomas, >=20 > > S0_C1 <=3D not SINI and WState =3D S0 and C1;=20 >=20 > "This equivalent code will not necessarily generate a signal "xx <=3D not= SINI and WState =3D S0 and C1" after synthesis. It will have this signal i= n an synthesis intermediate state but after logic optimisation this signal = can be removed in favor of simplified functionality depending on the comple= te FSM transition logic. " >=20 > You are right. I never say the S0_C1 will be the final logic, but says th= at the signal must appear during the synthesization. >=20 > Rick, >=20 > 1. Systematic method of coding wave-pipelined circuits in HDL >=20 > Patent #: 9-747-252 B2 > Issue date: 2017-08-29 > Allowance date: 2017-06-27 > Filing data: 02/05/2016 >=20 > 2. Apparatus of wave-pipelined circuits > Patent #: 9-575-929 B2 > Issue date: 2017-02-21 > Allowance date: 2016-12-21 > Filing data: 02/05/2016 >=20 > 3. Systematic method of synthesizing wave-pipelined circuits in HDL >=20 > Patent #: 9-734-127 B2 > Issue date: 2017-08-15 > Allowance date: 2017-06-19 > Filing data: 02/05/2016 >=20 > I think someday they will be introduced into HDL standard. >=20 > Google reviewed the applications since 2015/02/18, and finally made a rej= ection for the offer on 2018/03/16, 7 months after they became patents. I'm not interested in reading the patents. But if you wish to explain the = point of your patents, the utility as it were, in a way that we can underst= and, I would like to hear it. From the discussions we had you didn't under= stand the futility of trying to use these patents in FPGAs. While they may= be useful in ASICs, I don't believe you ever explained what you were actua= lly patenting. =20 Rick C.=20 Tesla referral code -+- https://ts.la/richard11209 Get 6 months of free superchargingArticle: 160932
Rick, Here are the main points about my inventions on wave-pipelining circuits: 1. All wave-pipelining circuits will be written in such a code if they were one-cycle logic. 2. Use a link statement linking your wave-pipeling circuit with one of 3 entities I have developed as a wave-pipelining circuit library. 3. A synthesizer generates the wave-pipelined circuit with one or two determined wave-constants passing to the entity. 4. There is no other logic to write. 5. It is specially useful for FPGA if the new HDL rules are accepted into new HDL standard. 6. Theory base: all wave-pipelining circuits are different in their 1-cycle logic, but other logic relating to the wave-pipelining parts are the same and classified into 3 categories that leads to 3 entities. 7. Example circuits: FFT-16; floating A*B --> C; WengArticle: 160933
On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote: > Rick, >=20 > Here are the main points about my inventions on wave-pipelining circuits: >=20 > 1. All wave-pipelining circuits will be written in such a code if they we= re one-cycle logic. >=20 > 2. Use a link statement linking your wave-pipeling circuit with one of 3 = entities I have developed as a wave-pipelining circuit library. >=20 > 3. A synthesizer generates the wave-pipelined circuit with one or two det= ermined wave-constants passing to the entity. >=20 > 4. There is no other logic to write. >=20 > 5. It is specially useful for FPGA if the new HDL rules are accepted into= new HDL standard. >=20 > 6. Theory base: all wave-pipelining circuits are different in their 1-cyc= le logic, but other logic relating to the wave-pipelining parts are the sam= e and classified into 3 categories that leads to 3 entities. >=20 > 7. Example circuits: FFT-16; floating A*B --> C; >=20 > Weng So what software handles the timing analysis and balances the delays???=20 If you are expecting the synthesis software to do the heavy lifting of timi= ng analysis, what exactly do your libraries do? What are your three entiti= es?=20 BTW, do you realize the synthesis software doesn't actually know the timing= of an FPGA circuit??? Timing is determined as much by the routing as it i= s the logic elements. So it is up to the chip vendor's place and route too= ls to get that right. This would not be an easy task to accomplish. =20 And of course all of this ignores the fact that minimum delays are just as = important as maximum delays in FPGA logic. It is hard to tell if you could= ever get this to work across the three variables of timing, process, volta= ge and temperature. Every chip will vary. Each board with slightly differ= ent PS voltages will vary. Every operating temperature will vary. For a w= ave pipeline to work all of the inputs to the delay equation have to result= in a very small window of delay variation.=20 How do you plan to control any of that?=20 Rick C. Tesla referral code -++ https://ts.la/richard11209 Get 6 months of free supercharging -++Article: 160934
On 15/12/2018 16:07, Weng Tianxiang wrote: .. > > It is the latest INFORMATION of GHDL: > > The current version of GHDL does not contain any graphical viewer: you cannot see signal waves. > > You can still check the behavior of your design with a test bench. > > Moreover, the current version can produce a GHW, VCD or FST files which can be viewed with a waveform viewer, such as GtkWave. > > GHDL aims at implementing VHDL as defined by IEEE 1076. It supports the 1987, 1993 and 2002 revisions and, partially, the latest, 2008. PSL is also partially supported. This is really good as none of the restricted free commercial versions supports PSL. > > Several third party projects are supported: VUnit, OSVVM, cocotb (through the VPI interface), . . . > > Now I know why GHDL is not populous, the basic reason is it has no waveform viewer! Build-in waveform viewer, but I agree with you this is a major obstacle. The waveform display is the number one debugging window. It doesn't matter if you design an AND gate or the latest billion gate machine learning chip the waveform window is always king. For this reason EDA vendors have added all sorts of enhancements such as virtual signals/functions, transaction display, analogue display, multiple panes, group/combine functions, scripting etc. GHW+Sigasi improves the situation but it is still not as smooth or capable as the free restricted Modelsim or ActiveHDL versions. > > But for a free version, it still has its values: Definitely, I hope GHDL will be the first simulator to fully support the 2018 standard. > 1. It can be used to correct all VHDL grammar errors, playing the same rule as Modelsim does. > > 2. It can be used to test a pre-issued product playing the same rule as Modelsim does, but it should be faster than Modelsim PE or SE. Hum? why should it be faster? I give all kudos to Tristan (et al.) as he wrote an amazing piece of software but it is definitely not faster than Modelsim. I ran two of my test cases again to see if anything has changed and GHDL was still 6x slower than Modelsim 10.7c. This is no surprise as Mentor has an army of engineers trying to squeeze the last fs from the simulation time. Modelsim SE has been obsolete for at least 8 years (replaced by Questa). Hans www.ht-lab.com > > 3. At least it provides files to communicate with third party software to view the waveform. > > I will be comfortable with this method: As an experienced VHDL designer, I spent most of time running Modelsim until an error showed up. The speed is very important factor to get all bugs discovered. > > Weng > >Article: 160935
> > 2. It can be used to test a pre-issued product playing the same rule as Modelsim does, but it should be faster than Modelsim PE or SE. > Hum? why should it be faster? I give all kudos to Tristan (et al.) as he > wrote an amazing piece of software but it is definitely not faster than > Modelsim. I ran two of my test cases again to see if anything has > changed and GHDL was still 6x slower than Modelsim 10.7c. This is no > surprise as Mentor has an army of engineers trying to squeeze the last > fs from the simulation time. > Modelsim SE has been obsolete for at least 8 years (replaced by Questa). > > Hans > www.ht-lab.com Hi Hans, I appreciate your sharing experiences with us. I desplayed Youtube "Getting Started With VHDL on Windows (GHDL & GTKWave)" https://www.youtube.com/watch?v=H2GyAIYwZbw&t=946s I asked one Modelsim seller who offers to sell Modelsim DE. Do you have any experiences with different versions of Modelsim and their prices? It seems to me that buying a Modelsim perpetual use of PE, or other advanced version may be my best option. Thank you. WengArticle: 160936
On Saturday, December 22, 2018 at 10:34:01 PM UTC-8, gnuarm.del...@gmail.co= m wrote: > On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote: > > Rick, > >=20 > > Here are the main points about my inventions on wave-pipelining circuit= s: > >=20 > > 1. All wave-pipelining circuits will be written in such a code if they = were one-cycle logic. > >=20 > > 2. Use a link statement linking your wave-pipeling circuit with one of = 3 entities I have developed as a wave-pipelining circuit library. > >=20 > > 3. A synthesizer generates the wave-pipelined circuit with one or two d= etermined wave-constants passing to the entity. > >=20 > > 4. There is no other logic to write. > >=20 > > 5. It is specially useful for FPGA if the new HDL rules are accepted in= to new HDL standard. > >=20 > > 6. Theory base: all wave-pipelining circuits are different in their 1-c= ycle logic, but other logic relating to the wave-pipelining parts are the s= ame and classified into 3 categories that leads to 3 entities. > >=20 > > 7. Example circuits: FFT-16; floating A*B --> C; > >=20 > > Weng >=20 > So what software handles the timing analysis and balances the delays???= =20 >=20 > If you are expecting the synthesis software to do the heavy lifting of ti= ming analysis, what exactly do your libraries do? What are your three enti= ties?=20 >=20 > BTW, do you realize the synthesis software doesn't actually know the timi= ng of an FPGA circuit??? Timing is determined as much by the routing as it= is the logic elements. So it is up to the chip vendor's place and route t= ools to get that right. This would not be an easy task to accomplish. =20 >=20 > And of course all of this ignores the fact that minimum delays are just a= s important as maximum delays in FPGA logic. It is hard to tell if you cou= ld ever get this to work across the three variables of timing, process, vol= tage and temperature. Every chip will vary. Each board with slightly diff= erent PS voltages will vary. Every operating temperature will vary. For a= wave pipeline to work all of the inputs to the delay equation have to resu= lt in a very small window of delay variation.=20 >=20 > How do you plan to control any of that?=20 >=20 > Rick C. >=20 > Tesla referral code -++ https://ts.la/richard11209 > Get 6 months of free supercharging -++ Rick, Intel first finished its 8087 chip using the wave-pipelining technology. No= wadays every company has the technology. Based on my knowledge, even Chines= e Huawei cellphone company uses the technology comfortably. You are right that Xilinx and Altera also have the potential to control the= technology. Nowadays any variations of temperatures, routine delays and vo= ltages are well known and calculated. WengArticle: 160937
On 23/12/2018 13:47, Weng Tianxiang wrote: > >>> 2. It can be used to test a pre-issued product playing the same rule as Modelsim does, but it should be faster than Modelsim PE or SE. >> Hum? why should it be faster? I give all kudos to Tristan (et al.) as he >> wrote an amazing piece of software but it is definitely not faster than >> Modelsim. I ran two of my test cases again to see if anything has >> changed and GHDL was still 6x slower than Modelsim 10.7c. This is no >> surprise as Mentor has an army of engineers trying to squeeze the last >> fs from the simulation time. >> Modelsim SE has been obsolete for at least 8 years (replaced by Questa). >> >> Hans >> www.ht-lab.com > > Hi Hans, > > I appreciate your sharing experiences with us. > > I desplayed Youtube "Getting Started With VHDL on Windows (GHDL & GTKWave)" > > https://www.youtube.com/watch?v=H2GyAIYwZbw&t=946s Nice tutorial although I would forget about the VCD format as it is not well suited for VHDL. There is e.g. no support for enumerated types (I suspect GTKwave will allow you to add them afterwards with some virtual functions). If you want to use GHDL use GHW+GTKWave together with Sigasi: https://youtu.be/thenLKSynO8 > > I asked one Modelsim seller who offers to sell Modelsim DE. > > Do you have any experiences with different versions of Modelsim and their prices? Have a look at this comparison chart: https://www.innofour.com/1015/eda/fpga-design/simulation-verification/modelsim-edition-comparison The main difference is that Modelsim DE will give you full support for PSL/SVA which is great for functional verification. You also get access to the FLI (VHDL C/C++ I/F) and full 64bits Windows support to name a few. If you don't need any of these just ask for Modelsim PE. > > It seems to me that buying a Modelsim perpetual use of PE, or other advanced version may be my best option. If you need it for commercial work then yes Modelsim is a great product. For personal use it is too expensive. Intel has a $1995 version (for Intel FPGA's only) but I think it is for 1 year only (non perpetual) and has lower performance than Modelsim. Good luck, Hans www.ht-lab.com > > Thank you. > > Weng >Article: 160938
On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote: >=20 > You are right. I never say the S0_C1 will be the final logic, but says th= at the signal must appear during the synthesization. >=20 Again you are mistaken except for the special case of a one-hot encoded sin= gle input state machine. Post the source code for something other than tha= t type of state machine that you have actually used along with the synthesi= s result that produces the S0_C1 signal to provide evidence otherwise you'r= e just making baseless, incorrect statements again. KevinArticle: 160939
On Sunday, December 23, 2018 at 6:52:58 AM UTC-5, HT-Lab wrote: > On 15/12/2018 16:07, Weng Tianxiang wrote: > .. > >=20 > > It is the latest INFORMATION of GHDL: > >=20 > > The current version of GHDL does not contain any graphical viewer: you = cannot see signal waves. > >=20 > > You can still check the behavior of your design with a test bench. > >=20 > > Moreover, the current version can produce a GHW, VCD or FST files which= can be viewed with a waveform viewer, such as GtkWave. > >=20 > > GHDL aims at implementing VHDL as defined by IEEE 1076. It supports the= 1987, 1993 and 2002 revisions and, partially, the latest, 2008. PSL is als= o partially supported. >=20 > This is really good as none of the restricted free commercial versions=20 > supports PSL. > >=20 > > Several third party projects are supported: VUnit, OSVVM, cocotb (throu= gh the VPI interface), . . . > >=20 > > Now I know why GHDL is not populous, the basic reason is it has no wave= form viewer! > Build-in waveform viewer, but I agree with you this is a major obstacle.= =20 > The waveform display is the number one debugging window. It doesn't=20 > matter if you design an AND gate or the latest billion gate machine=20 > learning chip the waveform window is always king. For this reason EDA=20 > vendors have added all sorts of enhancements such as virtual=20 > signals/functions, transaction display, analogue display, multiple=20 > panes, group/combine functions, scripting etc. > GHW+Sigasi improves the situation but it is still not as smooth or=20 > capable as the free restricted Modelsim or ActiveHDL versions. > >=20 > > But for a free version, it still has its values: > Definitely, I hope GHDL will be the first simulator to fully support the= =20 > 2018 standard. >=20 > > 1. It can be used to correct all VHDL grammar errors, playing the same = rule as Modelsim does. > >=20 > > 2. It can be used to test a pre-issued product playing the same rule as= Modelsim does, but it should be faster than Modelsim PE or SE. > Hum? why should it be faster? I give all kudos to Tristan (et al.) as he= =20 > wrote an amazing piece of software but it is definitely not faster than= =20 > Modelsim. I ran two of my test cases again to see if anything has=20 > changed and GHDL was still 6x slower than Modelsim 10.7c. This is no=20 > surprise as Mentor has an army of engineers trying to squeeze the last=20 > fs from the simulation time. It could be faster than Modelsim because Modelsim is intentionally crippled= unless you pay for the fastest version. So if GHDL picks up the same sort= s of speed enhancements as commercial packages it won't require that the hi= gher speeds be enabled.=20 > Modelsim SE has been obsolete for at least 8 years (replaced by Questa). Personally I wouldn't know. I use the ActiveHDL that comes free with Latti= ce tools. I gave up paying for this sort of software. I didn't feel I was= getting anything for my money. Support is not good. It seems most suppor= t comes from the community, in both commercial and open source packages. S= o why pay for commercial stuff? =20 Rick C. - Get 6 months of free supercharging=20 - Tesla referral code - https://ts.la/richard11209Article: 160940
On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote: > > I think someday they will be introduced into HDL standard. > Even if the patents are useful they wouldn't make it into any language standard...because they are patented. You don't understand how language standards happen, they are not going to take in anything claimed as proprietary. > Google reviewed the applications since 2015/02/18, and finally made a rejection for the offer on 2018/03/16, 7 months after they became patents. > So you're saying that Google reviewed your patents and did not find any value for them as a company. If the patents are so useful shouldn't you be mentioning which companies DID license your patents? KevinArticle: 160941
On 23/12/2018 15:18, gnuarm.deletethisbit@gmail.com wrote: > On Sunday, December 23, 2018 at 6:52:58 AM UTC-5, HT-Lab wrote: .. >> Hum? why should it be faster? I give all kudos to Tristan (et al.) as he >> wrote an amazing piece of software but it is definitely not faster than >> Modelsim. I ran two of my test cases again to see if anything has >> changed and GHDL was still 6x slower than Modelsim 10.7c. This is no >> surprise as Mentor has an army of engineers trying to squeeze the last >> fs from the simulation time. > > It could be faster than Modelsim because Modelsim is intentionally crippled unless you pay for the fastest version. True, but Modelsim's OEM versions are about 40% of the speed of Modelsim which means they are still faster than GHDL (base on my limited testing). Of course this is true until you reach the instance limit in which case Modelsim OEM grinds to a halt. It would be great if GHDL was faster than Modelsim as for some of my designs I don't need to log any signals, just sockets I/O. >So if GHDL picks up the same sorts of speed enhancements as commercial packages it won't require that the higher speeds be enabled. How can GHDL pick up the same sorts of speed enhancements? I am sure all EDA vendors keep their optimisers a close secret. > > >> Modelsim SE has been obsolete for at least 8 years (replaced by Questa). > > Personally I wouldn't know. I do. >I use the ActiveHDL that comes free with Lattice tools. Right and that version is not crippled? >I gave up paying for this sort of software. I didn't feel I was getting anything for my money. Support is not good. for you...., doesn't mean it is bad for everybody. > It seems most support comes from the community, in both commercial and open source packages. So why pay for commercial stuff? Because if you work on a commercial product and you find an issue you want to pick up the phone and get help immediately. They are required to help you as you are paying expensive maintenance, if they don't help you you switch products. Also for a complex product you can not rely on the free versions as they are too limited in their capabilities. I guess you are happy with the free ActiveHDL version as your designs are not that large. Regards, Hans. www.ht-lab.com > > Rick C. > > - Get 6 months of free supercharging > - Tesla referral code - https://ts.la/richard11209 >Article: 160942
On 23/12/2018 06:33, gnuarm.deletethisbit@gmail.com wrote: > On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote: >> Rick, .. > > So what software handles the timing analysis and balances the delays??? > > If you are expecting the synthesis software to do the heavy lifting of timing analysis, what exactly do your libraries do? What are your three entities? > > BTW, do you realize the synthesis software doesn't actually know the timing of an FPGA circuit??? To do a bit of nitpicking, they do (have to for timing optimisations) and I am not talking about a wire-load model. High-end synthesis tool offer what is called Physical Aware Synthesis (PAS). What they do is to run an internal placer (or use the P&R vendors version) and use that to estimate the timing to a surprising degree of accuracy. Apparently they do not need to run the actual routing as this is not required for a good estimate. >Timing is determined as much by the routing as it is the logic elements. I would say that for modern FPGA's the routing is normally the timing killer (on my designs routing delay >2x logic delay). I guess this is the reason products like Plunify (no affiliation) are so successful. >So it is up to the chip vendor's place and route tools to get that right. This would not be an easy task to accomplish. > > And of course all of this ignores the fact that minimum delays are just as important as maximum delays in FPGA logic. It is hard to tell if you could ever get this to work across the three variables of timing, process, voltage and temperature. Every chip will vary. Each board with slightly different PS voltages will vary. Every operating temperature will vary. For a wave pipeline to work all of the inputs to the delay equation have to result in a very small window of delay variation. > > How do you plan to control any of that? > > Rick C. > > Tesla referral code -++ https://ts.la/richard11209 > Get 6 months of free supercharging -++ > Regards, Hans www.ht-lab.comArticle: 160943
On Sunday, December 23, 2018 at 11:09:00 AM UTC-5, HT-Lab wrote: > On 23/12/2018 15:18, gnuarm.deletethisbit@gmail.com wrote: > > On Sunday, December 23, 2018 at 6:52:58 AM UTC-5, HT-Lab wrote: > .. > >> Hum? why should it be faster? I give all kudos to Tristan (et al.) as he > >> wrote an amazing piece of software but it is definitely not faster than > >> Modelsim. I ran two of my test cases again to see if anything has > >> changed and GHDL was still 6x slower than Modelsim 10.7c. This is no > >> surprise as Mentor has an army of engineers trying to squeeze the last > >> fs from the simulation time. > > > > It could be faster than Modelsim because Modelsim is intentionally crippled unless you pay for the fastest version. > > True, but Modelsim's OEM versions are about 40% of the speed of Modelsim > which means they are still faster than GHDL (base on my limited > testing). Of course this is true until you reach the instance limit in > which case Modelsim OEM grinds to a halt. It would be great if GHDL was > faster than Modelsim as for some of my designs I don't need to log any > signals, just sockets I/O. > > > >So if GHDL picks up the same sorts of speed enhancements as commercial packages it won't require that the higher speeds be enabled. > > How can GHDL pick up the same sorts of speed enhancements? I am sure all > EDA vendors keep their optimisers a close secret. > > > > > > >> Modelsim SE has been obsolete for at least 8 years (replaced by Questa). > > > > Personally I wouldn't know. > > I do. > > >I use the ActiveHDL that comes free with Lattice tools. > > Right and that version is not crippled? > > >I gave up paying for this sort of software. I didn't feel I was getting anything for my money. Support is not good. > > for you...., doesn't mean it is bad for everybody. > > > It seems most support comes from the community, in both commercial and open source packages. So why pay for commercial stuff? > > Because if you work on a commercial product and you find an issue you > want to pick up the phone and get help immediately. They are required to > help you as you are paying expensive maintenance, if they don't help you > you switch products. Also for a complex product you can not rely on the > free versions as they are too limited in their capabilities. I guess you > are happy with the free ActiveHDL version as your designs are not that > large. My use of the free tools is post having paid for tools and gotten a lot less than I would have liked. What gets support is buying lots of chips, not support dollars. Support dollars are chump change in the budget of the chip makers. Rick C. -- Get 6 months of free supercharging -- Tesla referral code - https://ts.la/richard11209Article: 160944
On Sunday, December 23, 2018 at 8:58:36 AM UTC-5, Weng Tianxiang wrote: > On Saturday, December 22, 2018 at 10:34:01 PM UTC-8, gnuarm.del...@gmail.= com wrote: > > On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote= : > > > Rick, > > >=20 > > > Here are the main points about my inventions on wave-pipelining circu= its: > > >=20 > > > 1. All wave-pipelining circuits will be written in such a code if the= y were one-cycle logic. > > >=20 > > > 2. Use a link statement linking your wave-pipeling circuit with one o= f 3 entities I have developed as a wave-pipelining circuit library. > > >=20 > > > 3. A synthesizer generates the wave-pipelined circuit with one or two= determined wave-constants passing to the entity. > > >=20 > > > 4. There is no other logic to write. > > >=20 > > > 5. It is specially useful for FPGA if the new HDL rules are accepted = into new HDL standard. > > >=20 > > > 6. Theory base: all wave-pipelining circuits are different in their 1= -cycle logic, but other logic relating to the wave-pipelining parts are the= same and classified into 3 categories that leads to 3 entities. > > >=20 > > > 7. Example circuits: FFT-16; floating A*B --> C; > > >=20 > > > Weng > >=20 > > So what software handles the timing analysis and balances the delays???= =20 > >=20 > > If you are expecting the synthesis software to do the heavy lifting of = timing analysis, what exactly do your libraries do? What are your three en= tities?=20 > >=20 > > BTW, do you realize the synthesis software doesn't actually know the ti= ming of an FPGA circuit??? Timing is determined as much by the routing as = it is the logic elements. So it is up to the chip vendor's place and route= tools to get that right. This would not be an easy task to accomplish. = =20 > >=20 > > And of course all of this ignores the fact that minimum delays are just= as important as maximum delays in FPGA logic. It is hard to tell if you c= ould ever get this to work across the three variables of timing, process, v= oltage and temperature. Every chip will vary. Each board with slightly di= fferent PS voltages will vary. Every operating temperature will vary. For= a wave pipeline to work all of the inputs to the delay equation have to re= sult in a very small window of delay variation.=20 > >=20 > > How do you plan to control any of that?=20 > >=20 > > Rick C. > >=20 > > Tesla referral code -++ https://ts.la/richard11209 > > Get 6 months of free supercharging -++ >=20 > Rick, >=20 > Intel first finished its 8087 chip using the wave-pipelining technology. = Nowadays every company has the technology. Based on my knowledge, even Chin= ese Huawei cellphone company uses the technology comfortably. >=20 > You are right that Xilinx and Altera also have the potential to control t= he technology. Nowadays any variations of temperatures, routine delays and = voltages are well known and calculated. The 8087 is not an FPGA. Nothing you have said addresses the fundamental l= imitations to using wave-pipelining in FPGAs. It doesn't matter if you can= calculate the delay variation from PVT or routing. Knowing it isn't the p= roblem, controlling it is. There is nothing the user can do about PVT so i= t is a variable that blurs the arrival time of the signal to the actual FF.= When that blurring becomes wider than a clock cycle you have to slow the = clock. Processing variations will likely be the largest contributor and th= ere is nothing to be done about it until they start binning chips for a spe= ed range rather than just maximums. =20 The other issue that has been pointed out to you is that in FPGAs there are= typically an excess of FFs RIGHT NEXT to the LUTs. So if you save FFs by = wave-pipelining you have done little if anything. Perhaps a small amount o= f power.=20 Rick C. - Get 6 months of free supercharging - Tesla referral code - https://ts.la/richard11209Article: 160945
On Sunday, December 23, 2018 at 11:43:29 AM UTC-5, HT-Lab wrote: > On 23/12/2018 06:33, gnuarm.deletethisbit@gmail.com wrote: > > On Sunday, December 23, 2018 at 12:10:28 AM UTC-5, Weng Tianxiang wrote= : > >> Rick, > .. > >=20 > > So what software handles the timing analysis and balances the delays??? > >=20 > > If you are expecting the synthesis software to do the heavy lifting of = timing analysis, what exactly do your libraries do? What are your three en= tities? > >=20 > > BTW, do you realize the synthesis software doesn't actually know the ti= ming of an FPGA circuit??? =20 >=20 > To do a bit of nitpicking, they do (have to for timing optimisations)=20 > and I am not talking about a wire-load model. High-end synthesis tool=20 > offer what is called Physical Aware Synthesis (PAS). What they do is to= =20 > run an internal placer (or use the P&R vendors version) and use that to= =20 > estimate the timing to a surprising degree of accuracy. Apparently they= =20 > do not need to run the actual routing as this is not required for a good= =20 > estimate. I'd love to know more about that. If they don't know the routing in the en= d design how can they know the timing? I don't know how you would "estimat= e" the timing. In particular, the timing required by wave-pipelining would= be much more detailed than in regular design requiring limits on the minim= um AND maximum delays of *each path*, not just logic. =20 I can't see how this would be possible, much less practical in any real wor= ld design other than regular structures like multipliers, etc. =20 > >Timing is determined as much by the routing as it is the logic elements.= =20 >=20 > I would say that for modern FPGA's the routing is normally the timing=20 > killer (on my designs routing delay >2x logic delay). I guess this is=20 > the reason products like Plunify (no affiliation) are so successful. >=20 > >So it is up to the chip vendor's place and route tools to get that right= . This would not be an easy task to accomplish. > >=20 > > And of course all of this ignores the fact that minimum delays are just= as important as maximum delays in FPGA logic. It is hard to tell if you c= ould ever get this to work across the three variables of timing, process, v= oltage and temperature. Every chip will vary. Each board with slightly di= fferent PS voltages will vary. Every operating temperature will vary. For= a wave pipeline to work all of the inputs to the delay equation have to re= sult in a very small window of delay variation. > > > How do you plan to control any of that? Rick C. + Get 6 months of free supercharging + Tesla referral code - https://ts.la/richard11209Article: 160946
On 23/12/2018 17:56, gnuarm.deletethisbit@gmail.com wrote: > On Sunday, December 23, 2018 at 11:43:29 AM UTC-5, HT-Lab wrote: .. >> To do a bit of nitpicking, they do (have to for timing optimisations) >> and I am not talking about a wire-load model. High-end synthesis tool >> offer what is called Physical Aware Synthesis (PAS). What they do is to >> run an internal placer (or use the P&R vendors version) and use that to >> estimate the timing to a surprising degree of accuracy. Apparently they >> do not need to run the actual routing as this is not required for a good >> estimate. > > I'd love to know more about that. If they don't know the routing in the end design how can they know the timing? Unfortunately I don't have much info on this, perhaps somebody else on this ng knows how it all works. I suspect that placement will allow you to identified the long tracks and congested areas, a wire-load model can then be used for final bits. >I don't know how you would "estimate" the timing. In particular, the timing required by wave-pipelining would be much more detailed than in regular design requiring limits on the minimum AND maximum delays of *each path*, not just logic. I agree, but I was not talking about wave-pipelining, just regular synthesis. Regards, Hans www.ht-lab.comArticle: 160947
On Saturday, December 22, 2018 at 12:14:43 PM UTC-7, gnuarm.del...@gmail.co= m wrote: > On Thursday, December 6, 2018 at 6:02:25 PM UTC-5, Kevin Neilson wrote: > > I've searched for this but to no avail. I'd like a function f(D,W), wh= ere D=3Ddepth and W=3Dwidth, which provides an estimate of the gate count o= f a lookup ROM implemented in ASIC gates. > >=20 > > Yes, I know it's dependent on the contents. However, if half the bits = are ones and the contents are randomly distributed, a formula should be pre= tty accurate. > >=20 > > It's easy for me to figure out an upper limit. A basic ROM is an AND-O= R array. The D address decoders (comprising ANDs/NOTs) can be shared among= st the W columns. Each of the W columns would require D/2-1 OR gates if ha= lf the ROM bits in each column are 1. > >=20 > > What I don't know is how many gates can be eliminated by sharing terms.= As W increases, term sharing should go up. Again, I'm looking for a *for= mula*. >=20 > That would be pretty easy. Consider the costs of a D wide multiplexer wi= th 1 or 0 on each input. That would be an upper bound in any case. =20 >=20 > I believe my text book of many years ago used one of the input variables = in either true or inverted form combined with 1s and 0s as choices for inpu= ts which simplified the mux by one address input. =20 >=20 > Rick C.=20 >=20 > Tesla referral code - https://ts.la/richard11209 > Get 6 months of free supercharging Thanks, but I am looking for an accurate estimate.Article: 160948
On Friday, December 28, 2018 at 2:49:37 PM UTC-5, Kevin Neilson wrote: > On Saturday, December 22, 2018 at 12:14:43 PM UTC-7, gnuarm.del...@gmail.= com wrote: > > On Thursday, December 6, 2018 at 6:02:25 PM UTC-5, Kevin Neilson wrote: > > > I've searched for this but to no avail. I'd like a function f(D,W), = where D=3Ddepth and W=3Dwidth, which provides an estimate of the gate count= of a lookup ROM implemented in ASIC gates. > > >=20 > > > Yes, I know it's dependent on the contents. However, if half the bit= s are ones and the contents are randomly distributed, a formula should be p= retty accurate. > > >=20 > > > It's easy for me to figure out an upper limit. A basic ROM is an AND= -OR array. The D address decoders (comprising ANDs/NOTs) can be shared amo= ngst the W columns. Each of the W columns would require D/2-1 OR gates if = half the ROM bits in each column are 1. > > >=20 > > > What I don't know is how many gates can be eliminated by sharing term= s. As W increases, term sharing should go up. Again, I'm looking for a *f= ormula*. > >=20 > > That would be pretty easy. Consider the costs of a D wide multiplexer = with 1 or 0 on each input. That would be an upper bound in any case. =20 > >=20 > > I believe my text book of many years ago used one of the input variable= s in either true or inverted form combined with 1s and 0s as choices for in= puts which simplified the mux by one address input. =20 > >=20 > > Rick C.=20 > >=20 > > Tesla referral code - https://ts.la/richard11209 > > Get 6 months of free supercharging >=20 > Thanks, but I am looking for an accurate estimate. I'm confused. Do you want an accurate measurement or an estimate? =20 Rick C. - Get 6 months of free supercharging=20 - Tesla referral code - https://ts.la/richard11209Article: 160949
On Saturday, December 29, 2018 at 9:53:20 AM UTC-7, gnuarm.del...@gmail.com= wrote: > On Friday, December 28, 2018 at 2:49:37 PM UTC-5, Kevin Neilson wrote: > > On Saturday, December 22, 2018 at 12:14:43 PM UTC-7, gnuarm.del...@gmai= l.com wrote: > > > On Thursday, December 6, 2018 at 6:02:25 PM UTC-5, Kevin Neilson wrot= e: > > > > I've searched for this but to no avail. I'd like a function f(D,W)= , where D=3Ddepth and W=3Dwidth, which provides an estimate of the gate cou= nt of a lookup ROM implemented in ASIC gates. > > > >=20 > > > > Yes, I know it's dependent on the contents. However, if half the b= its are ones and the contents are randomly distributed, a formula should be= pretty accurate. > > > >=20 > > > > It's easy for me to figure out an upper limit. A basic ROM is an A= ND-OR array. The D address decoders (comprising ANDs/NOTs) can be shared a= mongst the W columns. Each of the W columns would require D/2-1 OR gates i= f half the ROM bits in each column are 1. > > > >=20 > > > > What I don't know is how many gates can be eliminated by sharing te= rms. As W increases, term sharing should go up. Again, I'm looking for a = *formula*. > > >=20 > > > That would be pretty easy. Consider the costs of a D wide multiplexe= r with 1 or 0 on each input. That would be an upper bound in any case. =20 > > >=20 > > > I believe my text book of many years ago used one of the input variab= les in either true or inverted form combined with 1s and 0s as choices for = inputs which simplified the mux by one address input. =20 > > >=20 > > > Rick C.=20 > > >=20 > > > Tesla referral code - https://ts.la/richard11209 > > > Get 6 months of free supercharging > >=20 > > Thanks, but I am looking for an accurate estimate. >=20 > I'm confused. Do you want an accurate measurement or an estimate? =20 >=20 > Rick C. >=20 > - Get 6 months of free supercharging=20 > - Tesla referral code - https://ts.la/richard11209 Both. An estimate will be very close for large D,W. If I roll a die 1e6 t= imes, estimating there will be 5e5 heads is pretty accurate. Estimating th= ere will be less than or equal to the upper bound of 1e6 heads is correct b= ut not helpful.
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