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In article <5a65def4-8b0c-49f6-9642-15f52606832a@googlegroups.com>, Weng Tianxiang <wtxwtx@gmail.com> wrote: >Hi Mark, > >Here is the definition of a state machine introduced in my prior art part: > >[0003] Traditionally a deterministic finite state machine is mathematically defined as a set of 6-tuple M = (Σ, Δ, Q, q0, δ, λ), where Σ is a finite >set of input symbols, Δ /= 0 is a finite set of output symbols, Q /= 0 is a finite set of states, q0 є Q is the “reset” state, δ(q, a) : Q x Σ → Q >is the transfer function, and λ(q, a) : Q x Σ → Δ is the output function. >[0004] Conventional state machine theory has following State Machine Axiom: >[0005] State Machine Axiom A state machine has one and only one state being active on any cycle after the state machine is properly initialized. This definition matches all synchronous digital circuits. Regards, MarkArticle: 161001
Hi Mark, "This definition matches all synchronous digital circuits." Do you plan to retrieve the following claiming? "Weng - what you're completely missing what many have been telling you - your definition of a "state machine" is so broad that it's essentially meaningless." I really don't understand what you are saying. WengArticle: 161002
On Tuesday, January 8, 2019 at 4:47:13 PM UTC-5, Weng Tianxiang wrote: > On Tuesday, January 8, 2019 at 12:26:39 PM UTC-8, gtwrek wrote: > > In article <dd5eaff5-f99d-48f3-99bc-10dfda031747@googlegroups.com>, > > Weng Tianxiang <wtxwtx@gmail.com> wrote: > > >If 2 state machines as you suggested may be active on the same clock, = how do you handle it using your scheme? > >=20 > > Weng - I find your obsession with "state machines" a bit puzzling. I > > seem to recall an poster a few years ago asking about the "largest" > > state machine in current designs - was this you? It seems likely, in > > the event that you consider a CPU cache as a large number (~100,000) > > of state machines running in parallel. > >=20 > > I've not designed a CPU cache. But I can pretty much guarantee that > > whomever designed that CPU cache you're thinking about did NOT model=20 > > the design as such (a lot of state machines running in parallel). To > > be frank, I can see the entire design being done without implementing= =20 > > a "state machine" at all. > >=20 > > A state machine is simply a model to make it easier for humans to > > understand and design a circuit. It's not neccesary at all to apply > > this model to any or all digital circuits. =20 > >=20 > > One of my co-workers (for whatever reason) abhors "State machine"=20 > > design, and won't use them - at all. That's fine, he models things=20 > > differently. And he's a very productive engineer - not hindered one bi= t > > by his lack of use of "state machines".=20 > >=20 > > Conversely, one can model an entire ASIC (or FPGA) design as simply > > one large state machine. Or many smaller state machines running in > > parallel. (Assume a single clock for this analogy). It's just that a= =20 > > model to aid our (the designers) view of a design.=20 > >=20 > > Take a full schematic of any full ASIC. Draw a random blob around ANY > > set of 4-5 FFs. Include some parts of the fanin and fanout logic > > of those flip flops. Bam - there's a state machine. Repeat 20,000 > > times for all FF's in the design. Is this useful - not really - but it > > will meet any definition of "State Machine" that you can define. > >=20 > > Regard, > >=20 > > Mark >=20 > Hi Mark, >=20 > You really has good memory!!!=20 >=20 > I posted a post with title: "What is largest number of state machines in = a chip" at this FPGA group several years ago. >=20 > Here are tons of state machine patents about how to design a L2 cache. I = list only the search word "L2 cache inassignee:intel" and you can find thro= ugh Google there are 4,830 patents filed and issued by Intel, the search wo= rd "L2 cache state machine inassignee:intel" and it leads to 4,360, each of= them is related to a type of state machines.=20 >=20 > I believe that anyone cannot be accounted as a professional digital circu= it designer if he does not seriously consider or design a state machine. = =20 >=20 > One of my hobbies is to look at patents filed by Intel, IBM, AMD, Xilinx = and Altera. Reading Xilinx and Altera' patents gives me the knowledge on ho= w they design their FPGA chips. Reading Intel, IBM and AMD' patents gives m= e the knowledge on how they design something very complex and new technolog= y trend. And through the reading I find many topics for me to further devel= op.=20 >=20 > I disagree with your following opinion: > "I've not designed a CPU cache. But I can pretty much guarantee that=20 > whomever designed that CPU cache you're thinking about did NOT model=20 > the design as such (a lot of state machines running in parallel). To=20 > be frank, I can see the entire design being done without implementing=20 > a "state machine" at all. " >=20 > Here is an Intel patent: US8493397B1: "Circuit for placing a cache memory= into low power mode in response to special bus cycles executed on the bus" >=20 > https://patents.google.com/patent/US8493397?oq=3DL2+cache+state+machine >=20 > https://patents.google.com/patent/US20140156931?oq=3DL2+cache+state+machi= ne >=20 > I agree with your following opinion: > "a lot of state machines running in parallel". >=20 > After my invention all state machine design will be benefited to be in lo= wer power status, no matter what type of state machines is, and the logic r= esource usage is less than a conventional synthesizer would generate.=20 >=20 > Rick, > I disagree with your opinion: > "elsif WState /=3D WState_NS then=20 >=20 > This is not so trivial compared to the FSM itself, especially in an ASIC.= I would estimate it is approximately the same amount of logic in general.= " >=20 > In my invention there is no one single logic gate generated for compariso= n "WState /=3D WState_NS". Is it obvious to you?=20 >=20 > That is the best point of my invention. If you can perform an equality comparison without using gates, that will be= of tremendous value in logic design. Instead of using conventional gates = all logic can be decomposed to an expression using equality comparisons (th= e equivalent of the XOR applied to bits followed by an OR gate). So if you= can perform the not equal comparison on a multi-bit word without gates, th= en every digital logic design can be implemented with no logic gates at all= ! =20 By all means patent that and the world will beat a path to your door!!! =20 But obviously what you said is not true. So I must be misunderstanding you= . =20 Perhaps you can explain what you really mean.=20 Rick C. -+ Get 6 months of free supercharging -+ Tesla referral code - https://ts.la/richard11209Article: 161003
Hi Rick, First of all, I have to appreciate your following guessing: "If you can perform an equality comparison without using gates, that will b= e of tremendous value in logic design. Instead of using conventional gates= all logic can be decomposed to an expression using equality comparisons (t= he equivalent of the XOR applied to bits followed by an OR gate). So if yo= u can perform the not equal comparison on a multi-bit word without gates, t= hen every digital logic design can be implemented with no logic gates at al= l! " But You are wrong in guessing my invention without any logic bases. 1. There is no comparison at all. 2. I use another trick to avoid any comparison for a state machine circuit = and reach a conclusion that you need comparison to achieve. 3. The trick seems to be non-obvious to you now.=20 But don't worry, your conclusion is wrong too:=20 "obviously what you said is not true. So I must be misunderstanding you." WengArticle: 161004
In article <767950fd-cde7-4840-97d1-72013316e77a@googlegroups.com>, Weng Tianxiang <wtxwtx@gmail.com> wrote: >Hi Mark, > >"This definition matches all synchronous digital circuits." > >Do you plan to retrieve the following claiming? > >"Weng - what you're completely missing what many have been telling you - >your definition of a "state machine" is so broad that it's essentially >meaningless." Do you mean will I retract my statement? No I won't because it's consistent. The definition you listed in the grandparent post of a "state machine" has such a broad scope that EVERY synchronous digital circuit in existance fits the definition. You can prove me wrong by counter-example. I assert that your definition of "state machine" is so broad that any synchronous digital circuit will match your definition. If you can show/explain ANY synchronous digital circuit that does NOT match your definition of a "state machine" you'll have falsified my assertion. I can come at it from the opposite end and suggest a few example of synchronous digital circuits that one normally wouldn't think of as "state machines" but fit your definition none-the-less. But I think the excercise (of trying to come up with a counter-example) would help you understand what we've been trying to communicate to you. Regards, MarkArticle: 161005
On Wednesday, January 9, 2019 at 6:23:44 PM UTC-5, Weng Tianxiang wrote: >=20 > But You are wrong in guessing my invention without any logic bases. >=20 Perhaps Rick is wrong as you state (or maybe not), but I am not. You have = disclosed enough to discern what you think is the important idea to patent = (although I don't pretend to know all that you may claim from that idea). S= ince you cannot disclose until you hear about publication, I won't disclose= either. > 1. There is no comparison at all. >=20 > 2. I use another trick to avoid any comparison for a state machine circui= t and reach a conclusion that you need comparison to achieve. >=20 > 3. The trick seems to be non-obvious to you now.=20 >=20 But in fact the 'trick' as you call it is obvious and also, unfortunately f= or you, the idea is in fact old prior art that you are simply not recognizi= ng. But maybe the PTO won't pick up on it, or maybe you'll find someone to = part with $$ for what you will be marketing as a 'new' idea or maybe, if th= e patent is granted, you'll get challenged in court and lose. Time, as they= say, will tell. Kevin JenningsArticle: 161006
Kevin, Can you give me a link to the prior art idea?Article: 161007
Am Mittwoch, 9. Januar 2019 23:07:47 UTC+1 schrieb gtwrek: > Weng Tianxiang <wtxwtx@gmail.com> wrote: > >[0003] Traditionally a deterministic finite state machine is mathemat= ically defined as a set of 6-tuple M =3D (=CE=A3, =CE=94, Q, q0, =CE=B4, = =CE=BB), where =CE=A3 is a finite > >set of input symbols, =CE=94 /=3D 0 is a finite set of output symbols, Q= /=3D 0 is a finite set of states, q0 =D1=94 Q is the =E2=80=9Creset=E2=80= =9D state, =CE=B4(q, a) : Q x =CE=A3 =E2=86=92 Q > >is the transfer function, and =CE=BB(q, a) : Q x =CE=A3 =E2=86=92 =CE=94= is the output function. > >[0004] Conventional state machine theory has following State Machine = Axiom: > >[0005] State Machine Axiom A state machine has one and only one sta= te being active on any cycle after the state machine is properly initialize= d.=20 >=20 > This definition matches all synchronous digital circuits. Yes, that's true. A FSM could be a dedicated statemachine written in one HD= L module, but each counter is a simple FSM and each complete logic design c= an be seen as a statemachine. Every part of a statemachine containing at least 2 states and 1 input and o= utput is itself a statemachine and every combination of 2 statemachines is = one statemachine. FSM is just a model to describe a digital circuit with at= least one sequential element. best regards ThomasArticle: 161008
On 1/10/19 5:25 AM, Thomas Stanka wrote: > Am Mittwoch, 9. Januar 2019 23:07:47 UTC+1 schrieb gtwrek: >> Weng Tianxiang <wtxwtx@gmail.com> wrote: >>> [0003] Traditionally a deterministic finite state machine is mathematically defined as a set of 6-tuple M = (Σ, Δ, Q, q0, δ, λ), where Σ is a finite >>> set of input symbols, Δ /= 0 is a finite set of output symbols, Q /= 0 is a finite set of states, q0 є Q is the “reset” state, δ(q, a) : Q x Σ → Q >>> is the transfer function, and λ(q, a) : Q x Σ → Δ is the output function. >>> [0004] Conventional state machine theory has following State Machine Axiom: >>> [0005] State Machine Axiom A state machine has one and only one state being active on any cycle after the state machine is properly initialized. >> >> This definition matches all synchronous digital circuits. > > Yes, that's true. A FSM could be a dedicated statemachine written in one HDL module, but each counter is a simple FSM and each complete logic design can be seen as a statemachine. > > Every part of a statemachine containing at least 2 states and 1 input and output is itself a statemachine and every combination of 2 statemachines is one statemachine. FSM is just a model to describe a digital circuit with at least one sequential element. > > best regards Thomas > Perhaps some would call ANY synchronous digital circuit a state-machine, but the more classical definition would imply that it be a system with a single clock domain as it is the transformation from one 'State' to another 'State' on *The* clock edge, with the definition of the Next State being a function of the Previous State and the Inputs. The concept of previous and next imply a singular concept of time steps, thus a single clock domain (though clock gating/enables of that domain would be allowed). A system using multiple, not tightly related clocks, would fail that definition, and in the FSM view of the world would be multiple intertwined State Machines. Most digital system can be viewed as a set of coupled FSMs based on the number of clock domains in the system. Poly-Phase systems and system using wave phasing (multiple clocks between registers) stretch the concept of a State Machine a bit, but can probably be reasonably described as such. Some systems with Asynchronous bits can get harder to describe as a FSM.Article: 161009
In article <ugHZD.8990$nO2.5464@fx08.iad>, Richard Damon <Richard@Damon-Family.org> wrote: >On 1/10/19 5:25 AM, Thomas Stanka wrote: >> Am Mittwoch, 9. Januar 2019 23:07:47 UTC+1 schrieb gtwrek: >>> Weng Tianxiang <wtxwtx@gmail.com> wrote: >>>> [0003] Traditionally a deterministic finite state machine is mathematically defined as a set of 6-tuple M = (Σ, Δ, Q, q0, δ, λ), where Σ is a finite >>>> set of input symbols, Δ /= 0 is a finite set of output symbols, Q /= 0 is a finite set of states, q0 є Q is the “reset” state, δ(q, a) : Q x Σ → Q >>>> is the transfer function, and λ(q, a) : Q x Σ → Δ is the output function. >>>> [0004] Conventional state machine theory has following State Machine Axiom: >>>> [0005] State Machine Axiom A state machine has one and only one state being active on any cycle after the state machine is properly initialized. >>> >>> This definition matches all synchronous digital circuits. >> >> Yes, that's true. A FSM could be a dedicated statemachine written in one HDL module, but each counter is a simple FSM and each complete logic design can >be seen as a statemachine. >> >> Every part of a statemachine containing at least 2 states and 1 input and output is itself a statemachine and every combination of 2 statemachines is one >statemachine. FSM is just a model to describe a digital circuit with at least one sequential element. >> >> best regards Thomas >> > >Perhaps some would call ANY synchronous digital circuit a state-machine, >but the more classical definition would imply that it be a system with a >single clock domain as it is the transformation from one 'State' to >another 'State' on *The* clock edge, with the definition of the Next >State being a function of the Previous State and the Inputs. The concept >of previous and next imply a singular concept of time steps, thus a >single clock domain (though clock gating/enables of that domain would be >allowed). Yes, exactly. The qualification of a single clock - or as you note - related clocks is what I was trying to cover with the term SYNCHNRONOUS digitial circuits. In one of my post up the thread I mentioned a single clock - Kevin more correctly labeled the requirements as SYNCHRONOUS which I think summarizes the requirements better so I took that label. I'll say again, any SYNCHRONOUS digital circuit meets Weng's definition of a state machine. Regards, MarkArticle: 161010
On Wednesday, January 9, 2019 at 10:26:39 PM UTC-5, Weng Tianxiang wrote: > Kevin, Can you give me a link to the prior art idea? Sorry, I'm not going to prior art research for your patent application for you. However, I will suggest that you tend to take a very narrow view of some topic, such as a state machine, and appear to ignore applicable work that is more general, of which your 'state machine' is simply a subset. Kevin JenningsArticle: 161011
So much wrong. Any marginally competent cache designer understands that only one cache lin= e is accessed at a time. So the cache is designed as a RAM with data, tags,= and state. Each cycle the data, tags and state are read, and a single stat= e machine is used to generate the next state, which is written back into th= e RAM. There are plenty of papers on flip flop design that detects whether the new= data is different from the present state, and uses that to generate a cloc= k pulse only if necessary.=20 On Tuesday, January 8, 2019 at 6:12:43 PM UTC-5, Weng Tianxiang wrote: > Hi Mark, >=20 > "I assert (without eny evidence whatsoever) that whomever designed that C= PU=20 > cache memory at Intel did NOT model it (in his head or otherwise) as=20 > 100,000 or more state machines running in parallel. That's just crazy. " >=20 > Here are the facts, you are welcome and no matter whether you agree or no= t: > 1. 6M L2 cache, the largest L2 cache I can search for with a commercial C= PU;=20 >=20 > 2. Every 64 bytes in L2 cache constitute a cache line; >=20 > 3. Each L2 cache line works independently; >=20 > 4. Each L2 cache line has at least one state machine to control its data = or instructions in coherence. I will not be surprised that each L2 cache li= ne may have up to 8 state machines to control its working.=20 >=20 > 4. Each L2 cache line has at least one state machine to control its data = or instructions in coherence. I will not be surprised that each L2 cache li= ne may have up to 8 state machines to control its working. >=20 > 4. Each L2 cache line has at least one state machine to control its data = or instructions in coherence. I will not be surprised that each L2 cache li= ne may have up to 8 state machines to control its working. >=20 > 4. Each L2 cache line has at least one state machine to control its data = or instructions in coherence. I will not be surprised that each L2 cache li= ne may have up to 8 state machines to control its working. >=20 > 4. Each L2 cache line has at least one state machine to control its data = or instructions in coherence. I will not be surprised that each L2 cache li= ne may have up to 8 state machines to control its working. >=20 >=20 > 1. IBM: Cache-coherency protocol with upstream undefined state > https://patents.google.com/patent/US6374330 >=20 > 2. IBM: Cache-coherency protocol with recently read state for data and in= structions > https://patents.google.com/patent/US5996049 >=20 > 3. NVidia: State machine control for a pipelined L2 cache to implement me= mory transfers for a video processor. https://patents.google.com/patent/US8= 493397 >=20 > Thank you. >=20 > WengArticle: 161012
On Wednesday, January 9, 2019 at 6:23:44 PM UTC-5, Weng Tianxiang wrote: > Hi Rick, >=20 > First of all, I have to appreciate your following guessing: > "If you can perform an equality comparison without using gates, that will= be of tremendous value in logic design. Instead of using conventional gat= es all logic can be decomposed to an expression using equality comparisons = (the equivalent of the XOR applied to bits followed by an OR gate). So if = you can perform the not equal comparison on a multi-bit word without gates,= then every digital logic design can be implemented with no logic gates at = all! " >=20 > But You are wrong in guessing my invention without any logic bases. >=20 > 1. There is no comparison at all. >=20 > 2. I use another trick to avoid any comparison for a state machine circui= t and reach a conclusion that you need comparison to achieve. >=20 > 3. The trick seems to be non-obvious to you now.=20 >=20 > But don't worry, your conclusion is wrong too:=20 > "obviously what you said is not true. So I must be misunderstanding you.= " Ok, I am reading your code. So you are saying your code is not what you me= an. Got it.=20 Rick C. ++ Get 6 months of free supercharging ++ Tesla referral code - https://ts.la/richard11209Article: 161013
On Thursday, January 10, 2019 at 2:02:22 PM UTC-8, dlhe...@gmail.com wrote: > So much wrong. >=20 > Any marginally competent cache designer understands that only one cache l= ine is accessed at a time. So the cache is designed as a RAM with data, tag= s, and state. Each cycle the data, tags and state are read, and a single st= ate machine is used to generate the next state, which is written back into = the RAM. >=20 > There are plenty of papers on flip flop design that detects whether the n= ew data is different from the present state, and uses that to generate a cl= ock pulse only if necessary.=20 Congratulation! Your post is the best and most valuable post in this thread! Invincible! Marvelous! Smartest! Your post makes me shameful and speechless! Hope you join my later post. I will continue to pursue my next sets of inventions! Thank you. WengArticle: 161014
On Thursday, January 10, 2019 at 10:52:13 PM UTC-5, Weng Tianxiang wrote: > On Thursday, January 10, 2019 at 2:02:22 PM UTC-8, dlhe...@gmail.com wrot= e: > > So much wrong. > >=20 > > Any marginally competent cache designer understands that only one cache= line is accessed at a time. So the cache is designed as a RAM with data, t= ags, and state. Each cycle the data, tags and state are read, and a single = state machine is used to generate the next state, which is written back int= o the RAM. > >=20 > > There are plenty of papers on flip flop design that detects whether the= new data is different from the present state, and uses that to generate a = clock pulse only if necessary.=20 >=20 > Congratulation! >=20 > Your post is the best and most valuable post in this thread! >=20 > Invincible! Marvelous! Smartest! >=20 > Your post makes me shameful and speechless! >=20 > Hope you join my later post. >=20 > I will continue to pursue my next sets of inventions! >=20 > Thank you. >=20 > Weng LOL! So can you share your secret comparison using no gates?=20 Rick C. --- Get 6 months of free supercharging --- Tesla referral code - https://ts.la/richard11209Article: 161015
On 1/10/19 10:37 AM, gtwrek wrote: > In article <ugHZD.8990$nO2.5464@fx08.iad>, > Richard Damon <Richard@Damon-Family.org> wrote: >> On 1/10/19 5:25 AM, Thomas Stanka wrote: >>> Am Mittwoch, 9. Januar 2019 23:07:47 UTC+1 schrieb gtwrek: >>>> Weng Tianxiang <wtxwtx@gmail.com> wrote: >>>>> [0003] Traditionally a deterministic finite state machine is mathematically defined as a set of 6-tuple M = (Σ, Δ, Q, q0, δ, λ), where Σ is a finite >>>>> set of input symbols, Δ /= 0 is a finite set of output symbols, Q /= 0 is a finite set of states, q0 є Q is the “reset†state, δ(q, a) : Q x Σ → Q >>>>> is the transfer function, and λ(q, a) : Q x Σ → Δ is the output function. >>>>> [0004] Conventional state machine theory has following State Machine Axiom: >>>>> [0005] State Machine Axiom A state machine has one and only one state being active on any cycle after the state machine is properly initialized. >>>> >>>> This definition matches all synchronous digital circuits. >>> >>> Yes, that's true. A FSM could be a dedicated statemachine written in one HDL module, but each counter is a simple FSM and each complete logic design can >> be seen as a statemachine. >>> >>> Every part of a statemachine containing at least 2 states and 1 input and output is itself a statemachine and every combination of 2 statemachines is one >> statemachine. FSM is just a model to describe a digital circuit with at least one sequential element. >>> >>> best regards Thomas >>> >> >> Perhaps some would call ANY synchronous digital circuit a state-machine, >> but the more classical definition would imply that it be a system with a >> single clock domain as it is the transformation from one 'State' to >> another 'State' on *The* clock edge, with the definition of the Next >> State being a function of the Previous State and the Inputs. The concept >> of previous and next imply a singular concept of time steps, thus a >> single clock domain (though clock gating/enables of that domain would be >> allowed). > > Yes, exactly. The qualification of a single clock - or as you note - > related clocks is what I was trying to cover with the term SYNCHNRONOUS > digitial circuits. In one of my post up the thread I mentioned a > single clock - Kevin more correctly labeled the requirements as > SYNCHRONOUS which I think summarizes the requirements better so I took > that label. > > I'll say again, any SYNCHRONOUS digital circuit meets Weng's definition > of a state machine. > > Regards, > > Mark > > My terminology divided Synchronous (transitions happening on the edge of some 'global' clock) vs Asynchronous, where some device changes its state independant of the main clocks, perhaps with an asynchronous set/clear or being clocks by some input signal that isn't considered a system clock. Synchronous system can be divided into single domain and multi-clock domain systems, for which you seem to want to define 'Synchronous' as what I would consider 'Single Clock-Domain Synchronous'. Multi-clock domain synchronous system tend to not be define as *A* FSM, but can be as a set of FSMs that interact. Proper multi-clock domain systems need a bit of care at the domain boarders to avoid meta-stability issues, but this isn't really that hard to handle.Article: 161016
On 11/01/2019 15:12, Richard Damon wrote: > On 1/10/19 10:37 AM, gtwrek wrote: .. snip >> I'll say again, any SYNCHRONOUS digital circuit meets Weng's definition >> of a state machine. >> >> Regards, >> >> Mark >> >> > My terminology divided Synchronous (transitions happening on the edge of > some 'global' clock) vs Asynchronous, where some device changes its > state independant of the main clocks, perhaps with an asynchronous > set/clear or being clocks by some input signal that isn't considered a > system clock. > > Synchronous system can be divided into single domain and multi-clock > domain systems, for which you seem to want to define 'Synchronous' as > what I would consider 'Single Clock-Domain Synchronous'. Multi-clock > domain synchronous system tend to not be define as *A* FSM, but can be > as a set of FSMs that interact. > > Proper multi-clock domain systems need a bit of care at the domain > boarders to avoid meta-stability issues, but this isn't really that hard > to handle. > what? the opposite, it is really hard to handle unless you have a single signal moving from a slow to fast clock domain. Why do you think there are so many (quite expensive) CDC tools (Bluepearl, Spyglass, Questa CDC, Conformal, Meridian, ..) Have a look at past ASIC user surveys (like Wilson research group) and you will find that CDC errors are the number 2(!) reason for a respin, I would say that qualifies as a hard to handle issue given the cost of a respin nowadays. Trying to a find a deep convergence, reset or a CDC glitch problem in a 30 clock domain design (not that unique) is not for the faint-hearted and that is after identifying that it/they exists in the first place (simulation won't show you unless you use CDC-FF models from your CDC tool). Time to power cycle my TV box again as it got stuck yet again....;-) Hans www.ht-lab.comArticle: 161017
In article <Jn2_D.15781$375.3997@fx40.iad>, Richard Damon <Richard@Damon-Family.org> wrote: >My terminology divided Synchronous (transitions happening on the edge of >some 'global' clock) vs Asynchronous, where some device changes its >state independant of the main clocks, perhaps with an asynchronous >set/clear or being clocks by some input signal that isn't considered a >system clock. > >Synchronous system can be divided into single domain and multi-clock >domain systems, for which you seem to want to define 'Synchronous' as >what I would consider 'Single Clock-Domain Synchronous'. Multi-clock >domain synchronous system tend to not be define as *A* FSM, but can be >as a set of FSMs that interact. To be clear here - my definition of a "state machine" matches what I'm sure most of the other poster's here define it as. A small (less than 5-6 bits) number of states, operating on a single clock domain. Small enough such that a Synthesis Tools can apply a model to, where as the "state labels" can be disassociated from the actual bit encodings (and number of bits). Such a tool can then re-encode these bit encondings (and number of bits) in order to optimize the circuit, balancing such metrics as power, timing, area, soft-fault tolerance, and errant state detection. Such a re-encoding would preserve all state transitions, and output products - but change the underlying bit-encodings. Anything more than 5-6 bits (I don't think I've ever designed any with more than 4) would call (in my opinion) for some re-partitioning and redesign. In fact, I'd wouldn't be surprised that even with todays modern tools, a FSM optimizer would start choking when you reach 8-10 bits. Now, again this is all just a MODEL that we can apply as people to a digital, synchronous, single-clock domain circuit. Weng seems to be applying a looser definition of "state machine" that he's applying to model a CPU Cache circuit (with a ginormous number of states, or perhaps a ginoromous number of small, indepenent state machines all interacting). That's fine to model it as such, if there's some sort of benefit to having this model. (I think it's a silly model to make, without any benefit, but *shrug*) My only argument, which I still don't think he understands, is with his loose of a definition, one can apply his "state machine" model to ANY digital single-clock domain synchronous circuit. (I just wanted to avoid that last mouthful and just say "synchronous".) Weng further goes on and says, with this "state machine" model of a CPU cache, he can now apply some secret algorithm to optimize something. My (and other's) points here were that if his algorthim when applied under his "state machine" model for a CPU cache, would also apply to ANY other digital single-clock domain synchronous circuit. Many then would point out, that this would then all fit well within established prior art. Transformations of Clock Enable circuits to Gated Clocks are well understood to both the tools and designers. As per normal, the devil is all in the details of the cost/benefit metrics of making such transformations. (And also pointing out, I'm completely unclear as to what Weng's super snazzy algorithm is, under what conditions it could work, what it's cost could be, etc.) Some of his post seems to talk about low power and magic clock gating, but none of it is very clear.) Regards, MarkArticle: 161018
On Friday, January 11, 2019 at 3:04:01 PM UTC-5, HT-Lab wrote: > On 11/01/2019 15:12, Richard Damon wrote: > > On 1/10/19 10:37 AM, gtwrek wrote: > .. snip > >> I'll say again, any SYNCHRONOUS digital circuit meets Weng's definitio= n > >> of a state machine. > >> > >> Regards, > >> > >> Mark > >> > >> > > My terminology divided Synchronous (transitions happening on the edge o= f > > some 'global' clock) vs Asynchronous, where some device changes its > > state independant of the main clocks, perhaps with an asynchronous > > set/clear or being clocks by some input signal that isn't considered a > > system clock. > >=20 > > Synchronous system can be divided into single domain and multi-clock > > domain systems, for which you seem to want to define 'Synchronous' as > > what I would consider 'Single Clock-Domain Synchronous'. Multi-clock > > domain synchronous system tend to not be define as *A* FSM, but can be > > as a set of FSMs that interact. > >=20 > > Proper multi-clock domain systems need a bit of care at the domain > > boarders to avoid meta-stability issues, but this isn't really that har= d > > to handle. > >=20 > what? >=20 > the opposite, it is really hard to handle unless you have a single=20 > signal moving from a slow to fast clock domain. Why do you think there=20 > are so many (quite expensive) CDC tools (Bluepearl, Spyglass, Questa=20 > CDC, Conformal, Meridian, ..) Have a look at past ASIC user surveys=20 > (like Wilson research group) and you will find that CDC errors are the=20 > number 2(!) reason for a respin, I would say that qualifies as a hard to= =20 > handle issue given the cost of a respin nowadays. >=20 > Trying to a find a deep convergence, reset or a CDC glitch problem in a= =20 > 30 clock domain design (not that unique) is not for the faint-hearted=20 > and that is after identifying that it/they exists in the first place=20 > (simulation won't show you unless you use CDC-FF models from your CDC too= l). >=20 > Time to power cycle my TV box again as it got stuck yet again....;-) A customer asked me how I handle multiple clock domains and I told him that= unless there was reason to perform significant processing in multiple cloc= k domains I transition all I/Os to a single clock domain as quickly as poss= ible so that all interaction between circuits are then in that one clock do= main. The resulting domain transitions are limited and well defined making= them easy to debug.=20 Rick C. --+ Get 6 months of free supercharging --+ Tesla referral code - https://ts.la/richard11209Article: 161019
On 1/11/19 3:03 PM, HT-Lab wrote: > On 11/01/2019 15:12, Richard Damon wrote: >> On 1/10/19 10:37 AM, gtwrek wrote: > .. snip >>> I'll say again, any SYNCHRONOUS digital circuit meets Weng's definition >>> of a state machine. >>> >>> Regards, >>> >>> Mark >>> >>> >> My terminology divided Synchronous (transitions happening on the edge of >> some 'global' clock) vs Asynchronous, where some device changes its >> state independant of the main clocks, perhaps with an asynchronous >> set/clear or being clocks by some input signal that isn't considered a >> system clock. >> >> Synchronous system can be divided into single domain and multi-clock >> domain systems, for which you seem to want to define 'Synchronous' as >> what I would consider 'Single Clock-Domain Synchronous'. Multi-clock >> domain synchronous system tend to not be define as *A* FSM, but can be >> as a set of FSMs that interact. >> >> Proper multi-clock domain systems need a bit of care at the domain >> boarders to avoid meta-stability issues, but this isn't really that hard >> to handle. >> > what? > > the opposite, it is really hard to handle unless you have a single > signal moving from a slow to fast clock domain. Why do you think there > are so many (quite expensive) CDC tools (Bluepearl, Spyglass, Questa > CDC, Conformal, Meridian, ..) Have a look at past ASIC user surveys > (like Wilson research group) and you will find that CDC errors are the > number 2(!) reason for a respin, I would say that qualifies as a hard to > handle issue given the cost of a respin nowadays. > > Trying to a find a deep convergence, reset or a CDC glitch problem in a > 30 clock domain design (not that unique) is not for the faint-hearted > and that is after identifying that it/they exists in the first place > (simulation won't show you unless you use CDC-FF models from your CDC > tool). > > Time to power cycle my TV box again as it got stuck yet again....;-) > > Hans > www.ht-lab.com > > > Solving clock domains issues is fairly straight forward when they are identified at design time. You do need different strategies depending on the basic case you are working in, is it a single signal, or is it a bus, are we going fast to slow and need to make sure the signal gets across, etc. What is hard is to verify that you have detected all the cross domain transitions and performed the needed mitigations for it. They can also get harder if you are trying to squeeze every last drop of performance out of a cross domain connection. I suppose some things get mentally hard to shake, like making the assumption that your synchronous clear terminates simultaneously in all domains (instead of the idea that simultaneity isn't really a concept in a multi-clock domain system.) The other issue is that when you start to move to higher level abstractions the real RTL code, it becomes easier to miss the cross clock domain transfers or to miss some of the interactions between multiple instances of a given cross-domain transfer (Two signals that are together in clock domain 1 will not necessarily be together in clock domain 2 after transitioning, unless care is taken to keep them together).Article: 161020
On Friday, January 11, 2019 at 5:03:35 PM UTC-5, gtwrek wrote: >=20 > (And also pointing out, I'm completely unclear as to what Weng's super > snazzy algorithm is, under what conditions it could work, what it's cost > could be, etc.) Some of his post seems to talk about low power and magic > clock gating, but none of it is very clear.) This seems to be par for the course with patent seeking. The typical paten= t seeker is not proficient or even familiar with a given area of expertise,= has ill-conceived ideas of what the tools can do or how the tools work and= proposes poor solutions to issues no one else sees as problems.=20 I would be interested in learning of such a patent seeker's background and = what sorts of work they have done in the past.=20 Rick C. -+- Get 6 months of free supercharging -+- Tesla referral code - https://ts.la/richard11209Article: 161021
Hi Mark, Is there anywhere I said that "Weng seems to be applying a looser definition of "state machine" that he's applying to model a CPU Cache circuit (with a ginormous number of states, or perhaps a ginoromous number of small, indepenent state machines all interacting)." I only said that one L2 cache line has a state machine, and 6M L2 cache would need 100,000 state machines. And dlhe...@gmail.com resolved my problem accurately and excellently. Invincible! Marvelous! Smartest! Thank you, dlhe...@gmail.com. WengArticle: 161022
On 1/11/19 5:03 PM, gtwrek wrote: > In article <Jn2_D.15781$375.3997@fx40.iad>, > Richard Damon <Richard@Damon-Family.org> wrote: >> My terminology divided Synchronous (transitions happening on the edge of >> some 'global' clock) vs Asynchronous, where some device changes its >> state independant of the main clocks, perhaps with an asynchronous >> set/clear or being clocks by some input signal that isn't considered a >> system clock. >> >> Synchronous system can be divided into single domain and multi-clock >> domain systems, for which you seem to want to define 'Synchronous' as >> what I would consider 'Single Clock-Domain Synchronous'. Multi-clock >> domain synchronous system tend to not be define as *A* FSM, but can be >> as a set of FSMs that interact. > > To be clear here - my definition of a "state machine" matches what I'm > sure most of the other poster's here define it as. A small (less than > 5-6 bits) number of states, operating on a single clock domain. Small > enough such that a Synthesis Tools can apply a model to, where as the > "state labels" can be disassociated from the actual bit encodings (and > number of bits). Such a tool can then re-encode these bit encondings > (and number of bits) in order to optimize the circuit, balancing such > metrics as power, timing, area, soft-fault tolerance, and errant state > detection. Such a re-encoding would preserve all state transitions, and > output products - but change the underlying bit-encodings. > > Anything more than 5-6 bits (I don't think I've ever designed any with > more than 4) would call (in my opinion) for some re-partitioning and > redesign. In fact, I'd wouldn't be surprised that even with todays > modern tools, a FSM optimizer would start choking when you reach 8-10 > bits. > > Now, again this is all just a MODEL that we can apply as people to > a digital, synchronous, single-clock domain circuit. > > Weng seems to be applying a looser definition of "state machine" that > he's applying to model a CPU Cache circuit (with a ginormous number of > states, or perhaps a ginoromous number of small, indepenent state > machines all interacting). That's fine to model it as such, if there's > some sort of benefit to having this model. (I think it's a silly > model to make, without any benefit, but *shrug*) > > > Regards, > > Mark > The basic concept of a state machine is that given a state variable S (implemented with some number of bits and representing states like S0, S1, S2, ... Sn), and a set of inputs I, then we can say that we have the logic that at the clock signal S <= F(S, I) where F is a pure combinatorial function if its inputs. Technically, most single clock domain sychronous systems qualify by this definition, but I agree that 'arithmetic' and other data-path type structures are really state machines. I have designed state machines with perhaps as high as 100 state (slightly above your limit), and machines of that size that I have done tend to have a number of legs where once you get to state Sn, you automatically progress to state Sn+1, Sn+2 ... Sm and you could perhaps factor out a smaller state machine coupled to a counter. Based on the papers Weng pointed to, he is dealing with this sort of state machine, as they are presents as perhaps a dozen circles with conditions and outputs on the arrows between them, and a very large number of these in the system.Article: 161023
In my Verilog code I have this line:
reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 };
Both Icarus and Vivado seem happy with it and it does what I expect.
However, I recently discovered Verilator and its lint capability so I've
been running it over all my code to see if there is anything I ought to
clean up. Verilator does not like this code, it says the LHS only has 2
bits while the right is 8 bits, so I'm wondering if I should be writing
it differently. Maybe I've only been lucky so far that it's worked at
all and I'd rather have my code correct than lucky.
Thanks for any help,
Dave
Article: 161024
On Saturday, January 12, 2019 at 3:34:25 PM UTC-7, David Bridgham wrote:
> In my Verilog code I have this line:
>
> reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 };
>
> Both Icarus and Vivado seem happy with it and it does what I expect.
>
> However, I recently discovered Verilator and its lint capability so I've
> been running it over all my code to see if there is anything I ought to
> clean up. Verilator does not like this code, it says the LHS only has 2
> bits while the right is 8 bits, so I'm wondering if I should be writing
> it differently. Maybe I've only been lucky so far that it's worked at
> all and I'd rather have my code correct than lucky.
>
> Thanks for any help,
> Dave
That does not look like it should work. If you set the tool to SystemVeriliog mode you should be able to initialize the reg like this:
reg [1:0] ip_list [0:3] = '{ 2'd2, 2'd1, 2'd0, 2'd1 }; // note extra tick
In Verilog-2005 mode, I think you should only be able to set the unpacked elements individually or with $readmemh.
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