Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On 12/2/18 7:13 AM, David Brown wrote: > On 02/12/2018 01:18, gnuarm.deletethisbit@gmail.com wrote: > >> I'm sorry this thread ended this way. I was hoping to help him make >> some progress on his design and his understanding of how to design >> logic. But I can't say I am surprised. He seems to have difficulties >> in understanding how others think in general. So it shouldn't be a >> surprise that he had trouble understanding the concepts we tried to >> explain to him. I guess that is also why he hasn't learned very much >> from all the many sources available on the web and in books. >> > > Agreed. I have tried many times to help Rick (mostly in programming > groups, rather than this one). Sometimes it seems he learns a bit from > what I write, but sooner or later it ends with me or others telling him > he needs to learn more, or reduce the scope of his ambition, or re-think > the direction he is heading, and then we who help are declared to be > evil, negative influences, possessed by the devil (yes, apparently I am > possessed), or - as now - the worst sort of criminal. I see Rick a bit different. He has taken on an enormous mission, prompted by a blind faith that this is his calling and that by some supernatural power he will be able to succeed. He has learned enough about a lot of things, 'to be dangerous', but not enough to really have an expertise of the level really needed to succeed at his mission. He seems to refuse to learn from the mistakes of others, and doesn't look at history, perhaps due to his feeling of calling, and as such he is doomed to repeat most of the mistakes of the past, which will mean it will take him a long time to get to where he wants to get to. He somehow thinks that he will get the insight to bypass the issues that others had in those attempts, and somehow overlooked the answer. He also has the typical fanatical mindset that anyone trying to change his mind about anything remotely based on what he has taken of faith, must be from an evil source, since he can't be wrong.Article: 160826
On Sunday, 2 December 2018 20:23:36 UTC+1, Rick C. Hodgin wrote: > On Sunday, December 2, 2018 at 2:07:31 PM UTC-5, Julio Di Egidio wrote: > > And, as far as they are concerned, the US is the greatest nation in the > > Universe, bringing democracy and progress to us all. > > > > Can you see the pattern there? > > Julio, you and others here speak in generalizations. You blanket-categorize > someone like me into your own thinking Man, I wasn't replying to you... (and mine are not generalisations). JulioArticle: 160827
On Sunday, 2 December 2018 20:34:19 UTC+1, Julio Di Egidio wrote: > On Sunday, 2 December 2018 20:23:36 UTC+1, Rick C. Hodgin wrote: > > On Sunday, December 2, 2018 at 2:07:31 PM UTC-5, Julio Di Egidio wrote: > > > And, as far as they are concerned, the US is the greatest nation in the > > > Universe, bringing democracy and progress to us all. > > > > > > Can you see the pattern there? > > > > Julio, you and others here speak in generalizations. You blanket-categorize > > someone like me into your own thinking > > Man, I wasn't replying to you... (and mine are not generalisations). Plus you've snipped too much: it seems I am bashing the US, which was NOT the fucking point... JulioArticle: 160828
On 02/12/2018 20:37, Julio Di Egidio wrote: > On Sunday, 2 December 2018 20:34:19 UTC+1, Julio Di Egidio wrote: >> On Sunday, 2 December 2018 20:23:36 UTC+1, Rick C. Hodgin wrote: >>> On Sunday, December 2, 2018 at 2:07:31 PM UTC-5, Julio Di Egidio wrote: >>>> And, as far as they are concerned, the US is the greatest nation in the >>>> Universe, bringing democracy and progress to us all. >>>> >>>> Can you see the pattern there? >>> >>> Julio, you and others here speak in generalizations. You blanket-categorize >>> someone like me into your own thinking >> >> Man, I wasn't replying to you... (and mine are not generalisations). > > Plus you've snipped too much: it seems I am bashing the US, which was NOT the > fucking point... > Would you care to explain what your point was?Article: 160829
On Monday, December 3, 2018 at 7:17:19 AM UTC-5, gnuarm.del...@gmail.com wrote: > I am done talking with you in this thread. A reminder, Rick C. -- Rick C. HodginArticle: 160830
Smart locks are sure to become every homeowner=E2=80=99s favorite. They off= er the same level of security as typical mechanical door locks, but provide= a range of alternatives to the mechanical key, and a host of other feature= s. Digital locks are changing our lifestyle, leading us to a new digital er= a of keyless locking! Get Sample For Smart Lock: http://bit.ly/2RnrJL3=20 Authentication methods: PIN codes, Security tokens, Biometrics, Additional = Features, Multiple access solutions, Alarm integration Key Benefits 1. High Security Door Lock System Benefits Reduce Costs in the Long Run 2. High Security Door Lock Systems Can Be Customized to Meet Your Needs 3. Rekeyable Locks Allow You To Immediately Reset Locks 5. High Security Door Lock Systems Ensure SecurityArticle: 160831
Hi, I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation. Here is code defining the register array R: type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0); signal R : R_Type; alias P1 : it shows R array part of (DATA_BITS-1 downto 0); alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS); How to write the 2 alias statements in VHDL 2002 or 2008? Thank you. WengArticle: 160832
On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wrote: > Hi, > > I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation. > > Here is code defining the register array R: > type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0); > signal R : R_Type; > alias P1 : it shows R array part of (DATA_BITS-1 downto 0); > alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS); > > How to write the 2 alias statements in VHDL 2002 or 2008? > > Thank you. > > Weng Here is my version for the answer: type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); alias P1 : P1_Type := R(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); It should work on both 2002/2008 VHDL. Thank you. WengArticle: 160833
Hi,
I downloaded 11.0_modelsim_ase_windows.exe from https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html
Release Notes For ModelSim Altera 10.1b
Apr 26 2012
Copyright 1991-2012 Mentor Graphics Corporation
All rights reserved.
After installing the software, I cannot run it: Unable to checkout a licence. Modelsim-Altera uses the following environment variables to check the licence (listed in the order of preference)
1. MGLS_LICENCE_FILE
2. LM_LICENCE_FILE.
I don't know:
1. How to set the environment variables.
2. If the licence file is valid for me to free use?
Thank you.
Weng
Article: 160834Weng Tianxiang <wtxwtx@gmail.com> wrote: > Hi, > > I downloaded 11.0_modelsim_ase_windows.exe from > https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html > > Release Notes For ModelSim Altera 10.1b Why are you using a 7 year old version? > After installing the software, I cannot run it: Unable to checkout a > licence. Modelsim-Altera uses the following environment variables to > check the licence (listed in the order of preference) > > 1. MGLS_LICENCE_FILE > 2. LM_LICENCE_FILE. Modelsim-Altera should run without a licence for suitably small designs. However the older versions may have needed a licence server, which you probably don't have. TheoArticle: 160835
On 12/5/18 2:58 AM, Theo wrote: > Weng Tianxiang <wtxwtx@gmail.com> wrote: >> Hi, >> >> I downloaded 11.0_modelsim_ase_windows.exe from >> https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html >> >> Release Notes For ModelSim Altera 10.1b > > Why are you using a 7 year old version? > >> After installing the software, I cannot run it: Unable to checkout a >> licence. Modelsim-Altera uses the following environment variables to >> check the licence (listed in the order of preference) >> >> 1. MGLS_LICENCE_FILE >> 2. LM_LICENCE_FILE. > > Modelsim-Altera should run without a licence for suitably small designs. > However the older versions may have needed a licence server, which you > probably don't have. > > Theo > You need older versions of the software to generate designs for older chips, as the software drops support for older "obsolete" chips (even if you can still buy them). Even though it is listed as "free to use", you still need a license file, which you can apply for and get for free on the Altera web site. How to set the environment variables to point to the file you get will depend on your operating system, but it generally will be in the control panel.Article: 160836
On Tuesday, December 4, 2018 at 10:39:48 PM UTC-5, Weng Tianxiang wrote: > On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wrote: > > Hi, > > > > I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation. > > > > Here is code defining the register array R: > > type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0); > > signal R : R_Type; > > alias P1 : it shows R array part of (DATA_BITS-1 downto 0); > > alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS); > > > > How to write the 2 alias statements in VHDL 2002 or 2008? > > > > Thank you. > > > > Weng > > Here is my version for the answer: > type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); > > alias P1 : P1_Type := R(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); > > It should work on both 2002/2008 VHDL. "Should" work??? Haven't you tested it? Rick C. Tesla referral code - https://ts.la/richard11209Article: 160837
On Wednesday, December 5, 2018 at 5:37:26 AM UTC-8, gnuarm.del...@gmail.com wrote: > On Tuesday, December 4, 2018 at 10:39:48 PM UTC-5, Weng Tianxiang wrote: > > On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wrote: > > > Hi, > > > > > > I have a register array with each register having (pointer & data), now I hope to display each of two parts using 2 different names for easy reading in simulation. > > > > > > Here is code defining the register array R: > > > type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_BITS-1 downto 0); > > > signal R : R_Type; > > > alias P1 : it shows R array part of (DATA_BITS-1 downto 0); > > > alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BITS); > > > > > > How to write the 2 alias statements in VHDL 2002 or 2008? > > > > > > Thank you. > > > > > > Weng > > > > Here is my version for the answer: > > type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); > > > > alias P1 : P1_Type := R(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); > > > > It should work on both 2002/2008 VHDL. > > "Should" work??? Haven't you tested it? > > Rick C. > > Tesla referral code - https://ts.la/richard11209 Hi Rick, You have been the most famous contributor in FPGA and VHDL group for more than 10 years. If you answer, there is a problem. Here is a correction version: type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); alias P1 : P1_Type := R(0 to R_SIZE)(DATA_BITS-1 downto 0); Currently I have no Modelsim working and have no means to test. If you are kind enough, please test it. I think it SHOULD work. Thank you. WengArticle: 160838
On Wednesday, December 5, 2018 at 3:43:28 AM UTC-8, Richard Damon wrote: > On 12/5/18 2:58 AM, Theo wrote: > > Weng Tianxiang <wtxwtx@gmail.com> wrote: > >> Hi, > >> > >> I downloaded 11.0_modelsim_ase_windows.exe from > >> https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html > >> > >> Release Notes For ModelSim Altera 10.1b > > > > Why are you using a 7 year old version? > > > >> After installing the software, I cannot run it: Unable to checkout a > >> licence. Modelsim-Altera uses the following environment variables to > >> check the licence (listed in the order of preference) > >> > >> 1. MGLS_LICENCE_FILE > >> 2. LM_LICENCE_FILE. > > > > Modelsim-Altera should run without a licence for suitably small designs. > > However the older versions may have needed a licence server, which you > > probably don't have. > > > > Theo > > > > > You need older versions of the software to generate designs for older > chips, as the software drops support for older "obsolete" chips (even if > you can still buy them). > > Even though it is listed as "free to use", you still need a license > file, which you can apply for and get for free on the Altera web site. > > How to set the environment variables to point to the file you get will > depend on your operating system, but it generally will be in the control > panel. Hi Richard, Thank you for your response. My project does not need any chip, but a concept project, to make sure it works without linking to any FPGA chip. > Even though it is listed as "free to use", you still need a license > file, which you can apply for and get for free on the Altera web site. > I will try to get a licence file based on your advice, and am trying to buy a commercial one. WengArticle: 160839
On Wednesday, December 5, 2018 at 8:18:12 AM UTC-8, Weng Tianxiang wrote: > On Wednesday, December 5, 2018 at 3:43:28 AM UTC-8, Richard Damon wrote: > > On 12/5/18 2:58 AM, Theo wrote: > > > Weng Tianxiang <wtxwtx@gmail.com> wrote: > > >> Hi, > > >> > > >> I downloaded 11.0_modelsim_ase_windows.exe from > > >> https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html > > >> > > >> Release Notes For ModelSim Altera 10.1b > > > > > > Why are you using a 7 year old version? > > > > > >> After installing the software, I cannot run it: Unable to checkout a > > >> licence. Modelsim-Altera uses the following environment variables to > > >> check the licence (listed in the order of preference) > > >> > > >> 1. MGLS_LICENCE_FILE > > >> 2. LM_LICENCE_FILE. > > > > > > Modelsim-Altera should run without a licence for suitably small designs. > > > However the older versions may have needed a licence server, which you > > > probably don't have. > > > > > > Theo > > > > > > > > > You need older versions of the software to generate designs for older > > chips, as the software drops support for older "obsolete" chips (even if > > you can still buy them). > > > > Even though it is listed as "free to use", you still need a license > > file, which you can apply for and get for free on the Altera web site. > > > > How to set the environment variables to point to the file you get will > > depend on your operating system, but it generally will be in the control > > panel. > > Hi Richard, > > Thank you for your response. > > My project does not need any chip, but a concept project, to make sure it works without linking to any FPGA chip. > > > Even though it is listed as "free to use", you still need a license > > file, which you can apply for and get for free on the Altera web site. > > > > I will try to get a licence file based on your advice, and am trying to buy a commercial one. > > Weng Hi, May there be 3rd party FREE simulation tools in VHDL and Window 7/10 that are purely designed to do simulation only except Modelsim? Thank you. WengArticle: 160840
On 05/12/2018 17:18, Weng Tianxiang wrote: > On Wednesday, December 5, 2018 at 3:43:28 AM UTC-8, Richard Damon wrote: >> On 12/5/18 2:58 AM, Theo wrote: >>> Weng Tianxiang <wtxwtx@gmail.com> wrote: >>>> Hi, >>>> >>>> I downloaded 11.0_modelsim_ase_windows.exe from >>>> https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html >>>> >>>> Release Notes For ModelSim Altera 10.1b >>> >>> Why are you using a 7 year old version? >>> >>>> After installing the software, I cannot run it: Unable to checkout a >>>> licence. Modelsim-Altera uses the following environment variables to >>>> check the licence (listed in the order of preference) >>>> >>>> 1. MGLS_LICENCE_FILE >>>> 2. LM_LICENCE_FILE. >>> >>> Modelsim-Altera should run without a licence for suitably small designs. >>> However the older versions may have needed a licence server, which you >>> probably don't have. >>> >>> Theo >>> >> >> >> You need older versions of the software to generate designs for older >> chips, as the software drops support for older "obsolete" chips (even if >> you can still buy them). >> >> Even though it is listed as "free to use", you still need a license >> file, which you can apply for and get for free on the Altera web site. >> >> How to set the environment variables to point to the file you get will >> depend on your operating system, but it generally will be in the control >> panel. > > Hi Richard, > > Thank you for your response. > > My project does not need any chip, but a concept project, to make sure it works without linking to any FPGA chip. > >> Even though it is listed as "free to use", you still need a license >> file, which you can apply for and get for free on the Altera web site. >> > > I will try to get a licence file based on your advice, and am trying to buy a commercial one. > If you don't specifically need this old version of the software for handling old chips, then why not use newer and better versions, and save yourself the fuss with the licence files?Article: 160841
Richard Damon <Richard@damon-family.org> wrote: > You need older versions of the software to generate designs for older > chips, as the software drops support for older "obsolete" chips (even if > you can still buy them). Quartus yes, but not for Modelsim. (there may be some models of chip-specific logic cells if you want to simulate synthesised logic, but most users are simulating direct from HDL source code) > Even though it is listed as "free to use", you still need a license > file, which you can apply for and get for free on the Altera web site. That used to be true (hence why I queried using an older version), but is no longer. For recent Quartus and Modelsim, you don't need a licence for Quartus Lite and Modelsim-Intel FPGA Edition. Quartus prompts whether you want to ask for a 30 day trial licence, but it still works for a limited set of FPGAs and IP cores without. (eg Cyclone is included in Quartus Lite but Stratix needs Quartus Std with a paid licence) TheoArticle: 160842
David Brown <david.brown@hesbynett.no> wrote: > If you don't specifically need this old version of the software for > handling old chips, then why not use newer and better versions, and save > yourself the fuss with the licence files? There's a legitimate reason to use an old version when synthesising, because porting from one version of the tools to another is nontrivial (particularly with respect to supplied IP cores, which can change functionality in incompatible ways). So if somebody gives me a project built with a particular version, the first thing I do is try and build with that version, then port forward and see if it still works. Timing can often be markedly different between versions (not always for the better). However, I can't think of an instance when simulating where you might need to use an older version of the simulator. (give or take issues like 32 v 64 bit versions of tools and whatever your host OS supports) TheoArticle: 160843
On Wednesday, December 5, 2018 at 12:50:18 PM UTC-8, Theo wrote: > Richard Damon <Richard@damon-family.org> wrote: > > You need older versions of the software to generate designs for older > > chips, as the software drops support for older "obsolete" chips (even i= f > > you can still buy them). >=20 > Quartus yes, but not for Modelsim. > (there may be some models of chip-specific logic cells if you want to sim= ulate > synthesised logic, but most users are simulating direct from HDL source > code) >=20 > > Even though it is listed as "free to use", you still need a license > > file, which you can apply for and get for free on the Altera web site. >=20 > That used to be true (hence why I queried using an older version), but is= no > longer. For recent Quartus and Modelsim, you don't need a licence for > Quartus Lite and Modelsim-Intel FPGA Edition. >=20 > Quartus prompts whether you want to ask for a 30 day trial licence, but i= t > still works for a limited set of FPGAs and IP cores without. > (eg Cyclone is included in Quartus Lite but Stratix needs Quartus Std wit= h a > paid licence) >=20 > Theo Hi Theo, Where can I download Quartus Lite and Modelsim-Intel FPGA Edition? I downloaded from Intel website and got Altera_installer_12.1. I clicked t= he application Modelsim.10.1b and it immediately popped a window saying fat= al licence error.=20 After entering Intel website I really missed and don't know which is which. > For recent Quartus and Modelsim, you don't need a licence for > Quartus Lite and Modelsim-Intel FPGA Edition. If you are kind enough, please give me the exact address. I downloaded just= yesterday. So actually I downloaded a different version from yours. I ask for an old version, not because I use any old chip, but it is free. I= f it is true that "For recent Quartus and Modelsim, you don't need a licenc= e for Quartus Lite and Modelsim-Intel FPGA Edition", absolutely I would lik= e to download a 2008 VHDL version simulator. Writing code in VHDL 2008 is much easier than in VHDL 2002. Thank you. WengArticle: 160844
On Wednesday, December 5, 2018 at 11:07:50 AM UTC-5, Weng Tianxiang wrote: > On Wednesday, December 5, 2018 at 5:37:26 AM UTC-8, gnuarm.del...@gmail.c= om wrote: > > On Tuesday, December 4, 2018 at 10:39:48 PM UTC-5, Weng Tianxiang wrote= : > > > On Tuesday, December 4, 2018 at 12:37:54 PM UTC-8, Weng Tianxiang wro= te: > > > > Hi, > > > >=20 > > > > I have a register array with each register having (pointer & data),= now I hope to display each of two parts using 2 different names for easy r= eading in simulation. > > > >=20 > > > > Here is code defining the register array R: > > > > type R_Type is array(0 to R_SIZE) of unsigned(POINTER_BITS + DATA_B= ITS-1 downto 0);=20 > > > > signal R : R_Type; > > > > alias P1 : it shows R array part of (DATA_BITS-1 downto 0); > > > > alias P2 : it shows R array part of (POINTER_BITS-1 downto DATA_BI= TS); > > > >=20 > > > > How to write the 2 alias statements in VHDL 2002 or 2008? > > > >=20 > > > > Thank you. > > > >=20 > > > > Weng > > >=20 > > > Here is my version for the answer: > > > type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0); > > >=20 > > > alias P1 : P1_Type :=3D R(0 to R_SIZE) of unsigned(DATA_BITS-1 downt= o 0); > > >=20 > > > It should work on both 2002/2008 VHDL. > >=20 > > "Should" work??? Haven't you tested it?=20 > >=20 > > Rick C.=20 > >=20 > > Tesla referral code - https://ts.la/richard11209 >=20 > Hi Rick, >=20 > You have been the most famous contributor in FPGA and VHDL group for more= than 10 years. If you answer, there is a problem. First, don't assume that a "frequent" contributor means someone who knows a= nything. Then notice I only asked a question. I didn't say there was anyt= hing wrong. =20 > Here is a correction version: >=20 > type P1_Type array(0 to R_SIZE) of unsigned(DATA_BITS-1 downto 0);=20 >=20 > alias P1 : P1_Type :=3D R(0 to R_SIZE)(DATA_BITS-1 downto 0);=20 >=20 > Currently I have no Modelsim working and have no means to test. If you ar= e kind enough, please test it. I think it SHOULD work. You can download a copy of nearly any FPGA vendor's tools and use whichever= simulator they include. I would run it for you, but I am pretty busy at t= he moment. I'm with a friend who has gone through surgery and I have busin= ess tasks to deal with. Sorry I can't help more.=20 Rick C.=20 Tesla referral code + https://ts.la/richard11209Article: 160845
On Wednesday, December 5, 2018 at 11:18:12 AM UTC-5, Weng Tianxiang wrote: > On Wednesday, December 5, 2018 at 3:43:28 AM UTC-8, Richard Damon wrote: > > On 12/5/18 2:58 AM, Theo wrote: > > > Weng Tianxiang <wtxwtx@gmail.com> wrote: > > >> Hi, > > >> > > >> I downloaded 11.0_modelsim_ase_windows.exe from > > >> https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html > > >> > > >> Release Notes For ModelSim Altera 10.1b > > > > > > Why are you using a 7 year old version? > > > > > >> After installing the software, I cannot run it: Unable to checkout a > > >> licence. Modelsim-Altera uses the following environment variables to > > >> check the licence (listed in the order of preference) > > >> > > >> 1. MGLS_LICENCE_FILE > > >> 2. LM_LICENCE_FILE. > > > > > > Modelsim-Altera should run without a licence for suitably small designs. > > > However the older versions may have needed a licence server, which you > > > probably don't have. > > > > > > Theo > > > > > > > > > You need older versions of the software to generate designs for older > > chips, as the software drops support for older "obsolete" chips (even if > > you can still buy them). > > > > Even though it is listed as "free to use", you still need a license > > file, which you can apply for and get for free on the Altera web site. > > > > How to set the environment variables to point to the file you get will > > depend on your operating system, but it generally will be in the control > > panel. > > Hi Richard, > > Thank you for your response. > > My project does not need any chip, but a concept project, to make sure it works without linking to any FPGA chip. > > > Even though it is listed as "free to use", you still need a license > > file, which you can apply for and get for free on the Altera web site. > > > > I will try to get a licence file based on your advice, and am trying to buy a commercial one. You will find the same thing with Lattice. You need to obtain a free license to run their free tools. Not a big deal, but it runs out after a year and you need to get another free license. Rick C. Tesla referral code -- https://ts.la/richard11209Article: 160846
On 05/12/18 22:07, Theo wrote: > David Brown <david.brown@hesbynett.no> wrote: >> If you don't specifically need this old version of the software for >> handling old chips, then why not use newer and better versions, and save >> yourself the fuss with the licence files? > > There's a legitimate reason to use an old version when synthesising, because > porting from one version of the tools to another is nontrivial (particularly > with respect to supplied IP cores, which can change functionality in > incompatible ways). So if somebody gives me a project built with a particular > version, the first thing I do is try and build with that version, then port > forward and see if it still works. Timing can often be markedly different > between versions (not always for the better). Yes, I realise that - and I recommend not changing the tools for an existing project without extremely good reason. (I work mainly with embedded software, rather than programmable logic, but the same applies there.) However, my understanding is that the OP is doing tests and experiments with new code and a new design, so this does not apply. > > However, I can't think of an instance when simulating where you might need > to use an older version of the simulator. > > (give or take issues like 32 v 64 bit versions of tools and whatever your > host OS supports) > > Theo >Article: 160847
On 06/12/2018 01:03, Weng Tianxiang wrote: ..snip > > Hi Theo, > > Where can I download Quartus Lite and Modelsim-Intel FPGA Edition? > If you are a student then I would recommend the student edition which has far less limitations (instance limits) although for some unknown reason it is still single language only: https://www.mentor.com/company/higher_ed/modelsim-student-edition Mentor used to have lots of FPGA vendor OEM agreements (by my count at least 6), nowadays there are only 3(?) left: Intel: https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html Microchip: https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/prochip-designer Microchip(MicroSemi): https://www.microsemi.com/product-directory/dev-tools/4900-modelsim > > Writing code in VHDL 2008 is much easier than in VHDL 2002. So true, however, make sure your synthesis tool can handle 2008 as changing your code back from 2008 to 2002 is a real pain. Good luck, Hans. www.ht-lab.com > > Thank you. > > Weng >Article: 160848
Weng Tianxiang <wtxwtx@gmail.com> wrote: > Where can I download Quartus Lite and Modelsim-Intel FPGA Edition? https://dl.altera.com/ You'll need to login. The dropdowns allow you to select 'Lite' and whatever version you need. 18.1 is the most recent. I wouldn't use this for your first time, but because I end up deploying Quartus to servers a lot, I wrote a Python script to download and install the Linux version: https://github.com/CTSRD-CHERI/quartus-install This doesn't have a complete database of URLs, only the ones I've needed for particular jobs, and it has a few rough edges. Happy to take pull requests. (the URLs can be generated programmatically, but Altera kept changing the format between versions so I gave up and just pasted them all in) TheoArticle: 160849
Since my last post I have been working on my Logician tool. I currently ha= ve it modeling a simple bit storage device with four gates, two inputs, one= output, three other devices, and 13 bit lines. It provides a type of GtkW= ave output. I'm currently working on a true visualization of the circuits = along with a type of debugger environment for examining individual circuits= in local / watch windows, as well as a single-step debugger. Once it's all coded and validated, I'll move on to larger tests. I plan to= offer hot-swap DLL functions which replace large logic units once they're = validated, to replace their bits in and bits out with custom DLL code (for = faster simulations). Logician plans to be dynamic and extensible. When it is ready for a beta release, I'll post the Windows-based executable= and source code online along with a video and various examples explaining = how to use them. My first target will be the Scott CPU from the book "But = How Do It Know?" It is a simple 8-bit processor designed to teach people h= ow computers work fundamentally. It will be sufficient for a visualization= and operational demonstration of its features in real-time. I eventually plan to develop my CPUs in this tool, and to export the net it= creates to Verilog source code for use in a real FPGA. I could use help w= orking with Verilog and FPGA tools when that time comes. --=20 Rick C. Hodgin
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z