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On Monday, March 5, 2018 at 7:20:43 PM UTC+2, Rob Gaddi wrote: > On 03/03/2018 01:28 AM, HT-Lab wrote: > > In case anybody missed it: > > > > https://www10.edacafe.com/nbc/articles/1/1569384/Microchip-Technology-Acquire-Microsemi > > > > > > Hans > > www.ht-lab.com > > Man, Microchip has really come out of nowhere these last few year; they > definitely don't want to just be pidgeonholed into PIC anymore. > > On a larger note, is anyone else feeling like a good 2/3 of the > companies you've been doing business with for years have been acquired > in just the last few? Linear, National, Altera, Fairchild, Intersil, > IRF, Avago, Freescale, and that's just off the very top of my head. > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. Avago was not acquired. Avago acquired Broadcom and after that renamed themselves to more recognizable name.Article: 160551
I can't find it anywhere. No one carries Cyclone V SX/T, only plain E or Gx...Article: 160552
Dne sobota, 31. marec 2018 06.51.28 UTC+2 je oseba Brane2 napisala: > I can't find it anywhere. > > No one carries Cyclone V SX/T, only plain E or Gx... Errm, ignore that. Digikey has them under SoC, and others, I suspect, have similar bracket, too...Article: 160553
On Sunday, April 20, 2003 at 6:30:57 AM UTC-4, Ian Hickey wrote: > Does any manufacturer make a very small programmable logic device (with > FLASH storage) is say a SOIC-8 or similar. > > It's for a small home project that only has one output and only one input > (plus CLK) > > Thanks in advance. > > Ian I know this is many years since the original question, but... ...Times, they are a changin'... Here is an under $2 FPGA that sports 11 I/O pins in a tiny 4x4 BGA package (16 pins total). https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40UL1K-SWG16ITR50/220-1960-1-ND/5129490Article: 160554
On 3/22/2018 8:52 AM, John Larkin wrote: > On Thu, 22 Mar 2018 06:00:38 -0500, Paul Urbanus <urb@urbonix.com> > wrote: > >> On 3/16/2018 1:18 PM, John Larkin wrote: >>> I finally got a test case for my FPGA async one-shot idea, hacked into >>> a build for something else. >>> >>> I got 17 different one-shots, with various pin locations and >>> speed/drive strength settings. >>> >>> https://www.dropbox.com/s/4hxena27mpbpg54/FPGA_OS_1.JPG?raw=1 >>> <snipped> >>> >>> The Xilinx tools didn't approve of us doing this. >>> >> This was the circuit I used to generate 'synchronous' write enables >> for the LUT RAMs in the XC4000 family. This was the first Xilinx FPGA >> family that allowed the LUTs to be used as RAMs. The LUT RAM operation >> was all async, including the write enable, and I needed the RAM writes >> to occur in a single clock cycle. >> >> This was for a proof-of-concept (non-production) system and it worked >> flawlessly. >> > > Was that all internal to the FPGA, or did you loop through a pin? > > All internal, with the feedback routing being spatially local. Had some discussions with Xilinx engineering about this and whether the reset pulse would be too short to effect a reliable write if the LUT RAMs were slow. The concern was with the variation in timing due to process variation across the die. However, in this design the RAMs were close to the write pulse one-shot. The consensus was that since the write pulse generator and RAMs were relatively close together, process variation over that small area of (one-shot + LUT RAMS) was negligible. Thus a short/fast one-shot pulse was likely to be driving neighboring RAMs which were correspondingly fast. This was a video formatting application and the absence of artifacts on the display was deemed implicit confirmation of correction functionality.Article: 160555
I need an FPGA chip with about 100 GPIO pins and capable of hosting a CPU with an existing Linux port, mainly to run a web server. I would like to connect it to a 16-bit DRAM, so there should exist a memory controller with this feature, either a hard macro or a soft IP core. There should also be a fast ethernet MAC. Nothing fancy, but: 1. This is for a small non-profit project, so the IP cores must be free. Paying O(500) bucks for a Nios/MicroBlaze license is out of the question. Ditto about the MAC. As far as I know, neither Xiling nor Altera have a free/very cheap licensing option for non-profit applications, so the most obvious way is a no-go. Are there any *reasonable* open CPU/MAC/memory controller cores to use instead? $1000 per year is extremely cheap for commercial purposes, but a showstopper for hobby applications, where you can buy a bucket of STM32-class chips. 2. The chip must be hand-solderable and introduce no thermal strain problems. This excludes the BGA/chip scale packages and leaves only the QFP variants on the table. I don't care about the superior signal integrity benefits of the leadless packages, 50MHz is more than needed. But this requirement kills Zynq/Cyclone V, otherwise a perfect choice for this application. The PCB must be manufacturable in a cheap PCB shop and they can often do at most 4 layers. 3. The FPGA must be SRAM-based. 4. I don't want the SOM modules. The older Spartan 3Es (3S500E) or equivalent Cyclone 3 in PQFP208 would have been aa good choice here, but I seem to be blocked by the licenseing issues. I'd gladly stick to these platforms, but could you please recommend me any robust open-source IP cores which fit inside this class of FPGAs? Best regards, PiotrArticle: 160556
On Saturday, 14 April 2018 17:06:42 UTC+2, Piotr Wyderski wrote: > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: > > 1. This is for a small non-profit project, so the IP cores must be free. <snip> I'm playing with the Terasic DE1-SoC (sporting a dual core ARM aside a mid-range Cyclone V), pretty cheap and pretty cool. But in hindsight I should have gone for the one with no OpenCL support but the HDMI output instead... I mean, I thought OpenCL would be my way, as I was coming from pure software, then, after purchasing my board, I have realised the Intel OpenCL SDK isn't free and not even cheap. After learning the A of the ABC of digital design in Verilog, I am now playing with the Intel HLS compiler... A lot of (free) IP cores, and indeed there is a free toolchain: not possible to go supertech with it, such as you cannot do explicit placement or project partitioning, but otherwise no limitations. -- That said, I am seeing a lot of people around here rather talking of Xilinx, but I have no experience with those. JulioArticle: 160557
Julio Di Egidio wrote: > I'm playing with the Terasic DE1-SoC (sporting a dual core ARM aside a mid-range > Cyclone V), pretty cheap and pretty cool. But this is a ready-made FPGA development kit and one of the essential aspects of my projects is to create a working system from scratch, including custom board design and hand soldering by the advanced hobbyists. I don't want it to be pure Arduino-style software massaging. > That said, I am seeing a lot of people around here rather > talking of Xilinx, but I have no experience with those. Because Xilinx and Altera are the elite in this business. They have just forgotten about the hobbyists and charge them the same way as their industrial clients, despite the fact the hobby projects generate zero income. There used to be some exceptions for students, but not all hobbyists are students and even $500 for a yearly NIOSII license is more than the entire hobby budget. Same with MicroBlaze. The price is way too low for professional purchases and way too high for hobbyists, hence the problem. I don't understand this strategy of deterence, but it clearly works. Anyway, it's not my point, the manufacturers can set the price of their tools as high as they wish. I accept the situation and just ask: what cores/chips should I use instead? Best regards, PiotrArticle: 160558
On Saturday, 14 April 2018 18:30:45 UTC+2, Piotr Wyderski wrote: > Julio Di Egidio wrote: > > > I'm playing with the Terasic DE1-SoC (sporting a dual core ARM aside a mid-range > > Cyclone V), pretty cheap and pretty cool. > > But this is a ready-made FPGA development kit and one of the essential > aspects of my projects is to create a working system from scratch, > including custom board design and hand soldering by the advanced > hobbyists. I don't want it to be pure Arduino-style software massaging. I have no idea why you'd call it Arduino-style, but never mind, to each his requirement. > > That said, I am seeing a lot of people around here rather > > talking of Xilinx, but I have no experience with those. > > Because Xilinx and Altera are the elite in this business. They have > just forgotten about the hobbyists and charge them the same way as their > industrial clients, despite the fact the hobby projects generate > zero income. I don't see how you'd say that either, ~250 bucks for a development and prototyping board, plus indeed an industry level mind-set (not everything is so polished in fact, but that's another story) seems pretty cool to me. Anyway, I do come from the industry... Thanks for the feedback and good luck, JulioArticle: 160559
On Sat, 14 Apr 2018 17:06:37 +0200, Piotr Wyderski wrote: > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: > > 1. This is for a small non-profit project, so the IP cores must be free. > Paying O(500) bucks for a Nios/MicroBlaze license is out of the > question. Ditto about the MAC. As far as I know, neither Xiling nor > Altera have a free/very cheap licensing option for non-profit > applications, so the most obvious way is a no-go. Are there any > *reasonable* open CPU/MAC/memory controller cores to use instead? > $1000 per year is extremely cheap for commercial purposes, but > a showstopper for hobby applications, where you can buy a bucket > of STM32-class chips. > > 2. The chip must be hand-solderable and introduce no thermal strain > problems. This excludes the BGA/chip scale packages and leaves only > the QFP variants on the table. I don't care about the superior > signal integrity benefits of the leadless packages, 50MHz is more > than needed. But this requirement kills Zynq/Cyclone V, otherwise > a perfect choice for this application. The PCB must be manufacturable > in a cheap PCB shop and they can often do at most 4 layers. > > 3. The FPGA must be SRAM-based. > > 4. I don't want the SOM modules. > > The older Spartan 3Es (3S500E) or equivalent Cyclone 3 in PQFP208 > would have been aa good choice here, but I seem to be blocked by > the licenseing issues. I'd gladly stick to these platforms, but > could you please recommend me any robust open-source IP cores > which fit inside this class of FPGAs? > > Best regards, Piotr 100 GPIO + CPU + Ethernet + DRAM + Linux in non-BGA? Not likely I have not done an exhaustive search in a while but 144pin XC6SLX9 will give you 102 IO pins. You can get a Altera EP1C12Q240C7N in a QFP-240 with 173 IO. If this is a learning tool to program a FPGA I can see the need but I scoped out FPGA vs a SOM or Raspberrry PI Compute module and the latter always won. Even in quanity I cannot compete price wise with a SOM or Rpi CM. A XC6SLX9 will run you 16 bucks from Digi-Key and the EP1C12Q240C7N is $48. I dont think you will have enough resources in the FPGA to do a soft cpu, dram controller and ethernet block plus some gpio pins. You can buy a CM3 for $30. You will be hard pressed to make a board, get the FPGA, config memory, DRAM, Phy, etc for 30 bucks unless you are thinking mega quanity. No way you are gonna hand solder enough boards to get in that range. Granted you will have to have a carrier board/socket for the CM3 or SOM so that adds to the $30 cost. A uC with maybe a SPI or I2C port expander would give you more horse power and still be hand solderable. -- Chisolm Republic of TexasArticle: 160560
Julio Di Egidio wrote: > I have no idea why you'd call it Arduino-style, but never mind, to each > his requirement. By "Arduino-style" I mean buying a ready-made board and mixing existing code snippets without deeper understanding of the physical aspect of the device or even of the problem domain. I want to show how hard is to make such a board, solving all the problems on the way, and that it is finally doable. Anybody can buy any kit without understanding of the effort put into its creation and claim to be a hacker. My goal is to provide much deeper understanding of its *construction*, not *use*. IMHO one should be allowed to buy such a kit only after succesful completion of a DYI board. I mean, the kits are for professionals, because they offer significant development time (and money) saving. > I don't see how you'd say that either, ~250 bucks for a development and > prototyping board, plus indeed an industry level mind-set (not everything > is so polished in fact, but that's another story) seems pretty cool to me. > Anyway, I do come from the industry... I also come from the industry, but a different one. And it is perfectly normal to pay for the tools you earn your money with. Even as much as $50k per seat per year, been there, done that. But if a guy just wants to play with the technology involved and from the very beginning it is clear that he will make no money on that (come on, he wouldn't even afford the EMI testing required before product introduction to the market), it's not very wise to repel him with industrial-level charges, because you're most likely repelling your future user or at least a friendly advocate. This thread is an example of this situation, the message is: what should I use (i.e. learn and get used to) *instead of* Quartus/ISE. I don't have to understand this marketing policy, but I can certainly adapt to it. Professionally I'd probably get something from the Ultrascale line and wouldn't care about the complexity of the proper BGA package soldering, because it would be done by a machine anyway, a 10 layer board wouldn't be a problem because they are affordable in quantity. Fine, but it is not a professional application. And it seems that creating a simple web server on a custom FPGA board is not doable using the proper, vendor-approved tools, purely because of licensing costs. Crazy, but true. :-/ So the only option here is to get something working from opencores, but I can't say much about the quality of their particular implementations, hence the question. I need a GCC-supported CPU, a memory controller and a MAC. The budget is $10. :-) Best regards, PiotrArticle: 160561
Piotr Wyderski <peter.pan@neverland.mil> wrote: > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: What's the application that needs an on-FPGA CPU, rather than a CPU with attached FPGA? Could you use an existing CPU instead? eg a Beaglebone with FPGA wired to the PRU pins? Anything with a 16 bit DRAM (SDRAM?) isn't going to be very fast. > 1. This is for a small non-profit project, so the IP cores must be free. > Paying O(500) bucks for a Nios/MicroBlaze license is out of the > question. Ditto about the MAC. As far as I know, neither Xiling nor > Altera have a free/very cheap licensing option for non-profit > applications, so the most obvious way is a no-go. Are there any > *reasonable* open CPU/MAC/memory controller cores to use instead? > $1000 per year is extremely cheap for commercial purposes, but > a showstopper for hobby applications, where you can buy a bucket > of STM32-class chips. OpenRISC might be worth a look. There are some RISC-V cores but nothing I've seen stable enough to use for real Linux work. On all of these the Linux ports are a bit sketchy (you'll be managing your own toolchains and OS builds - no apt-get install here). For Linux you'll need an MMU, which will eat BRAMs. What storage will you be using for the OS and data? To save area, perhaps use an external ethernet MAC chip? You'll need an external chip for the PHY anyway. By the end of all this, you've built yourself a pretty cumbersome Linux system. I'd suggest trying to use a hard CPU in some way instead. > 2. The chip must be hand-solderable and introduce no thermal strain > problems. This excludes the BGA/chip scale packages and leaves only > the QFP variants on the table. I don't care about the superior > signal integrity benefits of the leadless packages, 50MHz is more > than needed. But this requirement kills Zynq/Cyclone V, otherwise > a perfect choice for this application. The PCB must be manufacturable > in a cheap PCB shop and they can often do at most 4 layers. The cheap Altera boards on ebay seem to be QFP Cyclone II and Cyclone IV, but they aren't very big. > The older Spartan 3Es (3S500E) or equivalent Cyclone 3 in PQFP208 > would have been aa good choice here, but I seem to be blocked by > the licenseing issues. I'd gladly stick to these platforms, but > could you please recommend me any robust open-source IP cores > which fit inside this class of FPGAs? Cyclones should build with the free Quartus Lite (formerly Web edition). I think NIOS and other bits of basic IP should be included, but I haven't confirmed that. TheoArticle: 160562
Joe Chisolm wrote: > 100 GPIO + CPU + Ethernet + DRAM + Linux in non-BGA? Not likely The number of GPIOs is just a rough estimate and not all of them must be created equal. There are dirt-cheap 16-bit SPI expander chips. The CPU and Linux running capabilities are not related to the specific packaging, it's just a legal (licensing) problem. On the market there are still the old Cyclones in PQ240, many chips from Altera and Xilinx are available in PQ208 and a horde of them is in PQ144. But even if you solder it succesfully to the board, you can't do much with it only because of the legal wall. I don't want to persuade Xilinx/Altera their policy is wrong, I don't even want to discuss it, as it is a pure waste of time of all the involved parties. I just consider this situation to be a law of nature and adapt to it by avoiding the quality implementations the vendors don't want to share. So I am open to the alternatives (Microsemi, Lattice, open-source IP cores, legacy chips). > If this is a learning tool to program a FPGA I can see the need > but I scoped out FPGA vs a SOM or Raspberrry PI Compute module and > the latter always won. Exactly, but the purpose is to learn building such a system from scratch, including PCB design, and it is beyond hobby capabilities to re-create even an RPi. > Even in quanity I cannot compete price wise > with a SOM or Rpi CM. It's not about competition, it's about learning this particular design process. Don't want it, don't play it, it has never been aimed at stealing the market share of the (good!) solutions you mention. > No way you are gonna hand solder > enough boards to get in that range. But it's not the goal. This price battle has already been lost, I'm perfectly aware of it. The goal is to build a decent, working FPGA system from the first principles. > A uC with maybe a SPI or I2C port expander would give you more horse > power and still be hand solderable. But there are no PLD resources, which are the main point here. The only solderable CPU with PLD I know of is PSOC5LP in TQ100, but it is way too small to host a Linux port and doesn't have a MAC on board. Best regards, PiotrArticle: 160563
Piotr Wyderski <peter.pan@neverland.mil> wrote: > But it's not the goal. This price battle has already been lost, > I'm perfectly aware of it. The goal is to build a decent, working FPGA > system from the first principles. If that's the goal, you have options: 1. Use a ready-made FPGA board (with a BGA part) 2. Use a system-on-module and your own carrier 3. Use separate CPU and FPGA chips 4. Be a microcontroller, don't run Linux If you've discounted those, you've constrained the problem so much that the only solution to your constraints is the empty set. TheoArticle: 160564
Theo Markettos wrote: > What's the application that needs an on-FPGA CPU, rather than a CPU with > attached FPGA? Could you use an existing CPU instead? eg a Beaglebone with > FPGA wired to the PRU pins? This is an option, but the CPU must be capable enough to run a decent OS, which means a fast ARM with MMU, which most likely means BGA again. So then it is better to use a Zynq/Cyclone V with such an ARM on chip. > Anything with a 16 bit DRAM (SDRAM?) isn't going to be very fast. The performance doesn't have to be stellar. > OpenRISC might be worth a look. There are some RISC-V cores but nothing > I've seen stable enough to use for real Linux work. On all of these the > Linux ports are a bit sketchy (you'll be managing your own toolchains and > OS builds - no apt-get install here). The compiler toolchain must be existing and stable, the hobbyists will not debug their custom GCC ports. > What storage will you be using for the OS and data? Probably a QSPI FLASH, maybe an SDHC card. > By the end of all this, you've built yourself a pretty cumbersome Linux > system. I'd suggest trying to use a hard CPU in some way instead. Is there anything solderable and still capable of running a pretty heavy OS? > Cyclones should build with the free Quartus Lite (formerly Web edition). I > think NIOS and other bits of basic IP should be included, but I haven't > confirmed that. There are evaluation versions of the mentioned IPs, but they work as long as the JTAG is connected. You'll not create a stand-alone device this way. Best regards, PiotrArticle: 160565
Piotr Wyderski <peter.pan@neverland.mil> wrote: > Theo Markettos wrote: > > > What's the application that needs an on-FPGA CPU, rather than a CPU with > > attached FPGA? Could you use an existing CPU instead? eg a Beaglebone > > with FPGA wired to the PRU pins? > > This is an option, but the CPU must be capable enough to run a decent > OS, which means a fast ARM with MMU, which most likely means BGA again. > So then it is better to use a Zynq/Cyclone V with such an ARM on chip. Well, there's things like the Ingenic X1000, which has a 1GHz single core MIPS and runs Linux. It has 64MB LPDDR in package. It's 0.8mm BGA, but you don't need to solder many of the balls to get it going, so you can do it with a simpler PCB. Though it doesn't have GPIO capability if you want that (and that would mean soldering more balls) > > OpenRISC might be worth a look. There are some RISC-V cores but nothing > > I've seen stable enough to use for real Linux work. On all of these the > > Linux ports are a bit sketchy (you'll be managing your own toolchains and > > OS builds - no apt-get install here). > > The compiler toolchain must be existing and stable, the hobbyists will > not debug their custom GCC ports. TBH it's no different from NIOS or Microblaze. The toolchains aren't custom, but aren't to the same level as ARM or MIPS. Yocto, Angstrom and similar make it a bit easier to build a distro for a custom platform. But expect glitches. > > What storage will you be using for the OS and data? > > Probably a QSPI FLASH, maybe an SDHC card. So you'll need IP cores for those too. There's an open source SD controller on OpenCores, but I'm not sure how well it works. I haven't looked at QSPI. Plus you'll need drivers (Linux+bootloader). > > By the end of all this, you've built yourself a pretty cumbersome Linux > > system. I'd suggest trying to use a hard CPU in some way instead. > > Is there anything solderable and still capable of running a pretty heavy OS? There's the older generation of parts with ARM7s and ARM9s in them - mostly QFP. Also the Allwinner A13 is a Cortex A8 in QFP. However you still need to attach DDR2/3 memory, which is BGA. You might be able to find DDR2 in TSOP perhaps? Apart from the goal of QFP-ness, do you actually need an FPGA for anything? Or would a suitable SoC in QFP fulfill your needs? > > Cyclones should build with the free Quartus Lite (formerly Web edition). I > > think NIOS and other bits of basic IP should be included, but I haven't > > confirmed that. > > There are evaluation versions of the mentioned IPs, but they work as > long as the JTAG is connected. You'll not create a stand-alone device > this way. Ah, understood. TheoArticle: 160566
Piotr Wyderski wrote: > The older Spartan 3Es (3S500E) or equivalent Cyclone 3 in PQFP208 > would have been aa good choice here, but I seem to be blocked by > the licenseing issues. I'd gladly stick to these platforms, but > could you please recommend me any robust open-source IP cores > which fit inside this class of FPGAs? http://plasmacpu.no-ip.org/cpu.htm All that you need in Public Domain...Article: 160567
On Saturday, April 14, 2018 at 12:02:09 PM UTC-5, Joe Chisolm wrote: > On Sat, 14 Apr 2018 17:06:37 +0200, Piotr Wyderski wrote: > > > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > > CPU with an existing Linux port, mainly to run a web server. I would > > like to connect it to a 16-bit DRAM, so there should exist a memory > > controller with this feature, either a hard macro or a soft IP core. > > There should also be a fast ethernet MAC. Nothing fancy, but: > > > > 1. This is for a small non-profit project, so the IP cores must be free. > > Paying O(500) bucks for a Nios/MicroBlaze license is out of the > > question. Ditto about the MAC. As far as I know, neither Xiling nor > > Altera have a free/very cheap licensing option for non-profit > > applications, so the most obvious way is a no-go. Are there any > > *reasonable* open CPU/MAC/memory controller cores to use instead? > > $1000 per year is extremely cheap for commercial purposes, but > > a showstopper for hobby applications, where you can buy a bucket > > of STM32-class chips. > > > > 2. The chip must be hand-solderable and introduce no thermal strain > > problems. This excludes the BGA/chip scale packages and leaves only > > the QFP variants on the table. I don't care about the superior > > signal integrity benefits of the leadless packages, 50MHz is more > > than needed. But this requirement kills Zynq/Cyclone V, otherwise > > a perfect choice for this application. The PCB must be manufacturable > > in a cheap PCB shop and they can often do at most 4 layers. > > > > 3. The FPGA must be SRAM-based. > > > > 4. I don't want the SOM modules. > > > > The older Spartan 3Es (3S500E) or equivalent Cyclone 3 in PQFP208 > > would have been aa good choice here, but I seem to be blocked by > > the licenseing issues. I'd gladly stick to these platforms, but > > could you please recommend me any robust open-source IP cores > > which fit inside this class of FPGAs? > > > > Best regards, Piotr > > 100 GPIO + CPU + Ethernet + DRAM + Linux in non-BGA? Not likely > > I have not done an exhaustive search in a while but 144pin XC6SLX9 > will give you 102 IO pins. You can get a Altera EP1C12Q240C7N in a > QFP-240 with 173 IO. > > If this is a learning tool to program a FPGA I can see the need > but I scoped out FPGA vs a SOM or Raspberrry PI Compute module and > the latter always won. Even in quanity I cannot compete price wise > with a SOM or Rpi CM. A XC6SLX9 will run you 16 bucks from > Digi-Key and the EP1C12Q240C7N is $48. I dont think you will have > enough resources in the FPGA to do a soft cpu, dram controller and > ethernet block plus some gpio pins. > > You can buy a CM3 for $30. You will be hard pressed to make a board, > get the FPGA, config memory, DRAM, Phy, etc for 30 bucks unless you > are thinking mega quanity. No way you are gonna hand solder > enough boards to get in that range. > > Granted you will have to have a carrier board/socket for the CM3 or > SOM so that adds to the $30 cost. > > A uC with maybe a SPI or I2C port expander would give you more horse > power and still be hand solderable. > > -- > Chisolm > Republic of Texas The Altera-Intel MAX X family is available in 144 pin flat-pack Jim BrakefieldArticle: 160568
Piotr Wyderski wrote: > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: > I don't think this is possible. The FPGAs that can support a Linux environment with a WEB SERVER are "serious" FPGAs. The lowest performance and capacity FPGAs that can support micro-style CPUs are not going to be able to handle a web server under Linux. Given that, the only ones that can are ALL going to be BGA-type packages. JonArticle: 160569
On 14/04/18 17:06, Piotr Wyderski wrote: > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: > > 1. This is for a small non-profit project, so the IP cores must be free. > Paying O(500) bucks for a Nios/MicroBlaze license is out of the > question. Ditto about the MAC. As far as I know, neither Xiling nor > Altera have a free/very cheap licensing option for non-profit > applications, so the most obvious way is a no-go. Are there any > *reasonable* open CPU/MAC/memory controller cores to use instead? > $1000 per year is extremely cheap for commercial purposes, but > a showstopper for hobby applications, where you can buy a bucket > of STM32-class chips. > > 2. The chip must be hand-solderable and introduce no thermal strain > problems. This excludes the BGA/chip scale packages and leaves only > the QFP variants on the table. I don't care about the superior > signal integrity benefits of the leadless packages, 50MHz is more > than needed. But this requirement kills Zynq/Cyclone V, otherwise > a perfect choice for this application. The PCB must be manufacturable > in a cheap PCB shop and they can often do at most 4 layers. > > 3. The FPGA must be SRAM-based. > > 4. I don't want the SOM modules. > > The older Spartan 3Es (3S500E) or equivalent Cyclone 3 in PQFP208 > would have been aa good choice here, but I seem to be blocked by > the licenseing issues. I'd gladly stick to these platforms, but > could you please recommend me any robust open-source IP cores > which fit inside this class of FPGAs? > > Best regards, Piotr > I think you might want to step back a little, and try to think what you are actually trying to achieve. What is the task at hand? What are the quantities? What is the target environment? Why are you looking for an FPGA - why are you even /considering/ making a board when you are talking about such small quantities that a $500 license fee is relevant? You say you need "a web server". That can range from something needing a multi-core multi-GHz processor, to something that can be done on a $5 microcontroller with a FreeRTOS or mbed demo program. At no stage in between is an FPGA a cost-effective way to run a web server application. You say you want 100 pins, but not what you are doing with them - perhaps they are mostly for the ram you think you need, the Ethernet interface, etc. What else do you want to do with these pins? You say you don't want SOM's or other modules - why not? They would reduce your development effort by orders of magnitude, and make certification, testing and production far simpler and cheaper. As far as I can see, your specifications here don't add up. It sounds like you have picked a "solution" of an FPGA without considering if it is the right tool for the job. And it sounds like you have a somewhat mixed up view of where the costs lie in going from vague idea to a produced product. (Most people have unrealistic views of costs - many will spend weeks of developer effort to "save" a few hundred dollars of license fees, without considering the cost of that developer time.)Article: 160570
On Sat, 14 Apr 2018 20:02:16 +0200, Piotr Wyderski wrote: > Joe Chisolm wrote: > >> 100 GPIO + CPU + Ethernet + DRAM + Linux in non-BGA? Not likely > > The number of GPIOs is just a rough estimate and not all of them > must be created equal. There are dirt-cheap 16-bit SPI expander chips. > The CPU and Linux running capabilities are not related to the specific > packaging, it's just a legal (licensing) problem. > > On the market there are still the old Cyclones in PQ240, many > chips from Altera and Xilinx are available in PQ208 and a horde > of them is in PQ144. But even if you solder it succesfully to > the board, you can't do much with it only because of the legal wall. > I don't want to persuade Xilinx/Altera their policy is wrong, I don't > even want to discuss it, as it is a pure waste of time of all the > involved parties. I just consider this situation to be a law of nature > and adapt to it by avoiding the quality implementations the vendors > don't want to share. So I am open to the alternatives (Microsemi, > Lattice, open-source IP cores, legacy chips). > >> If this is a learning tool to program a FPGA I can see the need >> but I scoped out FPGA vs a SOM or Raspberrry PI Compute module and >> the latter always won. > > Exactly, but the purpose is to learn building such a system from > scratch, including PCB design, and it is beyond hobby capabilities > to re-create even an RPi. It seems your goal is you want to do a DIY build of a system that uses a FPGA, or make the concept of the kit avilable to others so they can replicate what you have done. Design a board using a FPGA and make the FPGA do "something". That's all well and good but the board,fpga and hand solderable is a VERY small part of the equation. Where is the FPGA bit stream going to come from to "make it do something"? And no, I'm not asking about the config memory. You are going to have to be able to use the free versions of the FPGA tool chain of the vendor you choose. That's just one hurdle, the 2nd big one is getting today's hobbist to learn a HDL and how to use the tools - simulation and test bench, systhsis, P&R, build the bit stream, load it, test again. To be able to take something off of open cores and actually make it do something in your own FPGA is not a trivial task. You are not going to down load a "openrisc-v2.1.34-for-cyclone-v" bit stream and magically make it work. Just dealing with io placement will throw that off. I think it's a noble cause and I'd love to see more people know the down and dirty of how a box works but what you are asking is indeed difficult. If your hobbist target group is people doing digital design, maybe a uC with glue logic, etc is one thing but taking some person who's been doing python on linux and get them thinking hardware, VHDL or Verilog thinking, can be a rather large mountian to climb. [snip] -- Chisolm Republic of TexasArticle: 160571
Joe Chisolm <jchisolm6@earthlink.net> wrote: > I think it's a noble cause and I'd love to see more people know > the down and dirty of how a box works but what you are asking is > indeed difficult. If your hobbist target group is people doing > digital design, maybe a uC with glue logic, etc is one thing but > taking some person who's been doing python on linux and get them > thinking hardware, VHDL or Verilog thinking, can be a rather large > mountian to climb. Agreed 110%. What's more, a lot of this is out of the competence of people who do software. There's a huge pile of stuff built just to get to a shell prompt. But maybe your thing doesn't work. Is it a software bug, an OS bug, a compiler bug, a cache bug, a CPU bug, a peripheral bug, a memory bug, it failed to meet timing, you failed to constrain it properly, a signal integrity bug, a power supply bug...? The reason I suggested looking again at systems-on-module, particularly the ones with hard ARM cores in them, is that you have at least a working system that will reliably boot Linux, without too much in the way of dependencies on external infrastructure - just power and connectors. The OS works, the compiler is fairly well tested, the dev environment is familiar and tools like gdb work. All of these you have to build yourself from the ground up with a soft CPU. Then, if you wish, you can build your own CPU alongside in the FPGA soft-logic. Eventually you can turn off the ARM altogether if you want. But you always have the ARM as a familiar dependable environment to fall back on as a halfway house - and to debug your soft CPU. SOMs make custom PCB assembly easier, but also people can use off-the-shelf dev boards if they want. The only thing you lose is the ability to solder your own FPGA, which is not really an advantage to anyone unless you're selling in volume. Oh, did I also mention it's hard to buy FPGAs for sane prices if you're not selling in volume? TheoArticle: 160572
On 15/04/18 20:40, Joe Chisolm wrote: > I think it's a noble cause and I'd love to see more people know > the down and dirty of how a box works but what you are asking is > indeed difficult. If your hobbist target group is people doing > digital design, maybe a uC with glue logic, etc is one thing but > taking some person who's been doing python on linux and get them > thinking hardware, VHDL or Verilog thinking, can be a rather large > mountian to climb. > > That immediately brings to mind MyHDL - do the HDL design in Python. Putting a big cpu and logic for a Linux system in an FPGA is a complex task - even with a hard cpu core. I can't see how it adds anything to a "learn hardware design" board. I am not even convinced that a microcontroller beside the FPGA is worth the effort, but it could be fun to play with. Key features I would think for the system are: 1. An FPGA with some pins on LEDs, keys, etc., and some on headers. 2. An Arduino ARM compatible microcontroller and layout, with some pins on LEDs, keys, etc., and some to the FPGA. 3. A USB hub chip, with downstream components (FTDI devices or whatever) covering an FPGA interface compatible with a standard programmer for the FPGA device, a programmer interface for the Arduino chip, a serial port, and a connection to the FPGA for making your own USB device in programmable logic. 4. A few sensors, buzzers, etc. 5. Arduino compatible or Raspberry Pi compatible headers, but connected to the FPGA pins. And on the software side, a whole bunch of MyHDL examples and components for the board. Plus some in VHDL and some in Verilog, for more advanced stages.Article: 160573
Piotr Wyderski <peter.pan@neverland.mil> writes: > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: I think Lattice has the IP available for free. But no solderable FPGAs in the relevant families it seems. The other small player, Microsemi (or Microchip now) almost seems to have the FPGAs in the Igloo2 family, TQFP package with 84 I/O and a hard DDR2/DDR3 controller but I don't know about free IP. Or if the chips that are available in the TQFP are big enough for this (12k LEs, I think Altera's Max10 demo boards stuffed a Nios in their 8 k LE devices). Looks like Intel's Max 10 is the best bet for FPGA. EQFP package with 101 I/O and hard DDR2/3. > Are there any *reasonable* open CPU/MAC/memory controller cores to use > instead? For a soft CPU a RISC-V might be reasonable and a Linux port exists even if it's very new. RISC-V is an instruction set but as I understand it, there are loads of free implementations on Github. I don't know if decent ethernet MACs with Linux drivers are available for free. Maybe consider a separate chip? Microchip's ENC28J60 is probably one of the cheapest but it's 10 Mbps and SPI interface.Article: 160574
On Sat, 14 Apr 2018 17:06:37 +0200, Piotr Wyderski wrote: > I need an FPGA chip with about 100 GPIO pins and capable of hosting a > CPU with an existing Linux port, mainly to run a web server. I would > like to connect it to a 16-bit DRAM, so there should exist a memory > controller with this feature, either a hard macro or a soft IP core. > There should also be a fast ethernet MAC. Nothing fancy, but: > > 1. This is for a small non-profit project, so the IP cores must be free. > Paying O(500) bucks for a Nios/MicroBlaze license is out of the > question. Ditto about the MAC. As far as I know, neither Xiling nor > Altera have a free/very cheap licensing option for non-profit > applications, so the most obvious way is a no-go. Are there any > *reasonable* open CPU/MAC/memory controller cores to use instead? > $1000 per year is extremely cheap for commercial purposes, but a > showstopper for hobby applications, where you can buy a bucket of > STM32-class chips. Have you looked at the LM32 CPU core ?
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