Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Theo Markettos <theom+news@chiark.greenend.org.uk> wrote: (snip) >> The optimizer will remove the unusued logic just fine. > Except when it doesn't. > For instance, I have a toplevel model that defines some ports that are > driven by transceivers. The pins are configured with appropriate I/O > standards etc in the project configuration. > Let's say I change my PCIe port from 4x to 1x, which is a simple dropdown on > the PCIe core. If I have the ports on my toplevel module, but don't connect > them to anything, I get an error. If I remove the ports from my toplevel > module, but leave the transceiver settings alone, it compiles. This might depend on VHDL or veriog, but sometimes I assign Z to I/O ports, which will make the tools happy, and I can still use them as input ports. It might be that you can still also assign output values. Or you could use `ifdef or IF/GENERATE to assign them either the real value or a constant value. I usually assign constants instead of remove ports. (It makes it easier to add back later.) The one that keeps bothering me, is that you can't have lines in the UCF file for ports you aren't using. It would be really nice to include the whole UCF, and have it ignore the ports that your design didn't need (yet). -- glenArticle: 158001
On 6/23/2015 4:08 PM, glen herrmannsfeldt wrote: > Theo Markettos <theom+news@chiark.greenend.org.uk> wrote: > > (snip) > >>> The optimizer will remove the unusued logic just fine. > >> Except when it doesn't. > >> For instance, I have a toplevel model that defines some ports that are >> driven by transceivers. The pins are configured with appropriate I/O >> standards etc in the project configuration. > >> Let's say I change my PCIe port from 4x to 1x, which is a simple dropdown on >> the PCIe core. If I have the ports on my toplevel module, but don't connect >> them to anything, I get an error. If I remove the ports from my toplevel >> module, but leave the transceiver settings alone, it compiles. > A standard way to do this without `ifdef is to make the ports vectors and use a parameter to define the port width. At least that's how the xilinx cores do it, and it works for either VHDL or Verilog. It's a bit clunky to refer to a lane as TXn[3] / TXp[3] (one bit slice of each of two "vectors" to make a differential pair) but it works. > This might depend on VHDL or veriog, but sometimes I assign Z to I/O > ports, which will make the tools happy, and I can still use them as > input ports. It might be that you can still also assign output values. > > Or you could use `ifdef or IF/GENERATE to assign them either the > real value or a constant value. I usually assign constants instead > of remove ports. (It makes it easier to add back later.) > > > The one that keeps bothering me, is that you can't have lines in > the UCF file for ports you aren't using. > You can certainly leave constraints for unused ports in Xilinx tools. There's a couple of command line options, -aul and -aut IIRC to allow unmatched LOC constraints and unmatched timing constraints. In some versions of ISE, you can place all constraints for a port, LOC, IO Standard, Slew, Pullup, etc. on one line using | between constraints and the -aul will ignore the full line. In other versions the -aul just ignores some of the constraints and errors out on others. Oh, well... > It would be really nice to include the whole UCF, and have it ignore > the ports that your design didn't need (yet). > > -- glen > -- GaborArticle: 158002
Gabor <gabor@szakacs.org> wrote: (snip, I wrote) >> The one that keeps bothering me, is that you can't have lines in >> the UCF file for ports you aren't using. > You can certainly leave constraints for unused ports in Xilinx tools. > There's a couple of command line options, -aul and -aut IIRC to allow > unmatched LOC constraints and unmatched timing constraints. In some > versions of ISE, you can place all constraints for a port, LOC, IO > Standard, Slew, Pullup, etc. on one line using | between constraints > and the -aul will ignore the full line. In other versions the -aul > just ignores some of the constraints and errors out on others. > Oh, well... So far, I use the GUI, but sometime should switch to the command line version. Maybe the GUI allows it, too, but I didn't see where. -- glenArticle: 158003
Gabor <gabor@szakacs.org> wrote: > On 6/23/2015 4:08 PM, glen herrmannsfeldt wrote: > > Theo Markettos <theom+news@chiark.greenend.org.uk> wrote: > > > >> Let's say I change my PCIe port from 4x to 1x, which is a simple > >> dropdown on the PCIe core. If I have the ports on my toplevel module, > >> but don't connect them to anything, I get an error. If I remove the > >> ports from my toplevel module, but leave the transceiver settings > >> alone, it compiles. > > A standard way to do this without `ifdef is to make the ports vectors > and use a parameter to define the port width. At least that's how the > xilinx cores do it, and it works for either VHDL or Verilog. It's > a bit clunky to refer to a lane as TXn[3] / TXp[3] (one bit slice > of each of two "vectors" to make a differential pair) but it works. That works if I'm changing the width of a port, but what if I'm not using PCIe at all today? I don't believe you can do: `parameter PCIE_WIDTH -1 output [`PCIE_WIDTH:0] PCIE_TX_p; and hope that it'll delete PCIE_TX_p completely. > You can certainly leave constraints for unused ports in Xilinx tools. > There's a couple of command line options, -aul and -aut IIRC to allow > unmatched LOC constraints and unmatched timing constraints. In some > versions of ISE, you can place all constraints for a port, LOC, IO > Standard, Slew, Pullup, etc. on one line using | between constraints > and the -aul will ignore the full line. In other versions the -aul > just ignores some of the constraints and errors out on others. > Oh, well... Most of the time this works for Altera too, it's the case of transceivers where it doesn't. I have no idea why, it's arguably a bug in the tools. The tools don't like partitions or LogicLock regions which aren't associated with logic, but that's more likely to be a bug that you want to be alerted of. It's a pain when the list of modules in your design is configurable, though. TheoArticle: 158004
glen herrmannsfeldt wrote: > Gabor <gabor@szakacs.org> wrote: > > (snip, I wrote) >>> The one that keeps bothering me, is that you can't have lines in >>> the UCF file for ports you aren't using. > >> You can certainly leave constraints for unused ports in Xilinx tools. >> There's a couple of command line options, -aul and -aut IIRC to allow >> unmatched LOC constraints and unmatched timing constraints. In some >> versions of ISE, you can place all constraints for a port, LOC, IO >> Standard, Slew, Pullup, etc. on one line using | between constraints >> and the -aul will ignore the full line. In other versions the -aul >> just ignores some of the constraints and errors out on others. >> Oh, well... > > So far, I use the GUI, but sometime should switch to the > command line version. Maybe the GUI allows it, too, but I > didn't see where. > > -- glen In the GUI you go to translate properties --> "Other NGDBuild command line options" and there you can add any options you want. However more recent versions of the GUI have -aul and -aut as check boxes as well. -- GaborArticle: 158005
Gabor wrote: >> The one that keeps bothering me, is that you can't have lines in >> the UCF file for ports you aren't using. >> > You can certainly leave constraints for unused ports in Xilinx tools. > There's a couple of command line options, -aul and -aut IIRC to allow > unmatched LOC constraints and unmatched timing constraints. In some > versions of ISE, you can place all constraints for a port, LOC, IO > Standard, Slew, Pullup, etc. on one line using | between constraints > and the -aul will ignore the full line. In other versions the -aul > just ignores some of the constraints and errors out on others. > Oh, well... <rant> I never got why the DEFAULT behaviour is to quit with an error when there's LOC constraints for non-existant ports, but only issue a warning (which easily gets lost amongst thousands others in the logs) if an existing port is NOT location constrained. The tool then places the IO randomly, and this is most certainly not the desired behaviour, since you could potentially damage hardware when you're driving an IO that connects to something that should not be driven. Unlikely, but possible. The only exception I can think of is in the hardware concept phase, when you want to let the tools chose a valid pin out for you that you can then copy to your schematic. But that is a rare case that IMHO would justify an extra mouse click or an added command line switch. This DEFAULT behaviour is stupid IMHO. Of course you can change it with obscure command-line switches or a setting hidden away in some "Advanced" tab, but someone at Xilinx must have deliberately chosen to make this the default behaviour for whatever reason, and I don't get it. I think this is one of these things that got introduced in a very early software release, and even though it doesn't make any sense at all, it was never fixed because people would get confused if the default behaviour changed. I think Vivado now issues a "Critical Warning" by default for unconstrained ports. Sounds better, but when you think about it, it doesn't help a lot, since critical warnings also do not stop the flow (unless you promote that warning to an error). Unless you use the GUI, those critical warnings can also easily get lost in the log files if you don't specifically look for them, especially when you use a purely command-line driven flow like me. Not to mention that I don't understand what the hell a "Critical Warning" is supposed to be. Either it's a warning, or it's critical, and then it'd better be an error. What sense does it make to introduce another severity level in between "warning" and "error"? I personally have not seen a "critical warning" that did not cause me to re-run the entire flow, and then it would have been better to stop the flow right the moment the critical warning occured as not to waste my time. That's why I've promoted all critical warning to errors, which fortunately is easy enough in Vivdao via Tcl. </rant>, SeanArticle: 158006
GaborSzakacs <gabor@alacron.com> wrote: (snip on ignoring UCF entries for pins that don't exist.) >> So far, I use the GUI, but sometime should switch to the >> command line version. Maybe the GUI allows it, too, but I >> didn't see where. > In the GUI you go to translate properties --> "Other NGDBuild > command line options" and there you can add any options you > want. However more recent versions of the GUI have -aul > and -aut as check boxes as well. OK, I did that. Thanks! This is especially useful for starter boards which have a lot of pins that you aren't using, but also for general purpose boards, again with extra pins that you might not be using. -- glenArticle: 158007
Hi, I have seen contradictory data about speed of GTX transceivers in Kintex 7 = in FBG packages: 1. The datasheet ( http://www.xilinx.com/support/documentation/data_sheets/= ds182_Kintex_7_Data_Sheet.pdf , page 54 ) states that the maximum speed is = 6.6 Gb/s 2. The answer record http://www.xilinx.com/support/answers/50299.html state= s explicitly: " Limit the maximum line rate to 6.6 Gb/s if you need the cor= e files for an FBG package, even if the GUI allows for a higher line rate (For Kintex-7 devices the maximum line rate is not dependent on package type and can be up to 12.5 Gb/s for all packages while in Zynq it is limited to 6.6 Gb/s for FBG packages and is 12.5 Gb/s for FFG packages)." I haven't seen any warnings about rate limit in FB... packages in product s= election guides like http://www.xilinx.com/publications/prod_mktg/7-series-= product-selection-guide.pdf or http://www.xilinx.com/products/silicon-devic= es/fpga/kintex-7.html#producttable I have tested a board, which was supposed to be assembled with xc7k325t_ff= g900 chip, but due to a mistake an xc7k325t_fbg900 was used (chip was hidd= en under the heat sink, and in JTAG there is no difference between those ch= ips) The board worked perfectly at full speed with 10 Gbps links. Does anybody has an information if this speed limit for FB package really e= xists, and what is its reason? I can see two possible reasons: 1. Signal integrity. I know that there are differences between wire-bond and flip-chip packages (but AFAIK both FB and FF are flip-chip) 2. Heat dissipation. At 10 Gbps the link may dissipate more power=20 than at 6.6 Gbps. But does FB have higher thermal resistance than=20 the FF one? The difference between the two above is significant. In case 1 - if the board happened to work and Eye Diagram is good, it can b= e reliably used. In case 2 - the board may work with link test only, but when we add additio= nal processing blocks it may get overheated... Thank you in advance, Best regards, Wojtek=20 PS. This qustion was also asked on Xilinx forum: http://forums.xilinx.com/t5/7-Series-FPGAs/Speed-of-GTX-transceivers-in-Kin= tex-7-in-FBG-package/m-p/638015#M12356 With best regards, WojtekArticle: 158008
On Saturday, April 11, 2015 at 9:16:41 AM UTC+3, pini_kr wrote: > Hi >=20 > I just wanted to know if people use systemc in FPGA flow. systemc can be > used for cycle accurate simulation, where it can replace RTL. In this > mode test-benches will usually take advantage of c++ and SCV (for > writing constraints). > For big designs where RTL completion takes a lot of time systemc can be > used for LT or AT simulations ( Loosely Timed, Approximately Timed=20 > TLM). >=20 > Pini > --------------------------------------- > Posted through http://www.FPGARelated.com I am currently using SystemC to model a memory hierarchy that will later be= used on FPGAs. At this point it is a TLM model so it's pretty abstract. St= ill have not decided if I will try to refine to RTL with SystemC or jump di= rectly to VHDL once the behavior is validated. However, I am also curious about how often people use it for FPGA design, i= f it is worth it. Cheers,Article: 158009
Good morning, I was trying to run some test vectors on an ATF1504ASVL_A44 CPLD. Even found some BSDL files on the net(no Idea if they're correct, tho'). I have vectors like this: V0001 NLLNLLNLNLL1NNNNNNNHNNNNNNNNNNNNNN0NNNNNNLLL* V0002 NLLNLLNLNLL0NNNNNNNHNNNNNNNNNNNNNN0NNNNNNLLL* V0003 NLLNLLNLNLL0NNNNNNNLNNNNNNNNNNNNNN1NNNNNNHLL* [...] They are generated from a verilog sim. >From those I tried generating SVF files like this: [...] SIR 10 TDI (055); SDR 192 TDI (0000000000000000840101510401415145c1401045400411); SIR 10 TDI (000); RUNTEST 1.000000E-05 SEC; SIR 10 TDI (055); SDR 192 TDI (000000000000000044010151040141514541401045400411) TDO (000000080000000044010151040141514541401045400411) MASK (000000080185709400000000000000000000000000000000); SIR 10 TDI (055); SDR 192 TDI (000000000000000084010151040141514581401045400411); SIR 10 TDI (000); RUNTEST 1.000000E-05 SEC; SIR 10 TDI (055); SDR 192 TDI (000000000000000044010151040141514541401045400411) TDO (000000080000000044010151040141514541401045400411) MASK (000000080185709400000000000000000000000000000000); [...] using sample/preload runtest and extest states. When playing, it failed at the first vector. There was an IDCODE check before that, and that worked, so the communication seems ok. Then I tried this: [...] SIR 10 TDI (000); SDR 192 TDI (0000000000000000840101510401415145c1401045400411); SIR 10 TDI (000); SDR 192 TDI (000000000000000084010151040141d1458280208a800822) TDO (000000000000000044010151040141d1454280208a800822) MASK (000000000000000000000000000000c00003c030cfc00c33); SIR 10 TDI (000); SDR 192 TDI (0000000000000000c4010151040141d1458280208a800822) TDO (000000000000000044010151040141d1454280208a800822) MASK (000000000000000000000000000000c00003c030cfc00c33); SIR 10 TDI (000); SDR 192 TDI (00000000000000008401015104014191458280208a800823) TDO (00000000000000004401015104014191454280208a800823) MASK (000000000000000000000000000000c00003c030cfc00c33); [...] ..extest only... It also failed at the first vector (with the same bitpattern read back)... The program for generating the svf files is there: <https://github.com/klammerj/vec2svf> What am I doing wrong? (/Is/ there a way of doing it right?)Article: 158010
Can you share the error message if any and the tool environment?Article: 158011
On 06/28/2015 06:25 AM, Sharad wrote: > Can you share the error message if any and the tool environment? > using urjtag, I got: [...] svf.c:473 urj_svf_compare_tdo(): Error svf: mismatch at position 49 for TDO svf.c:479 urj_svf_compare_tdo(): in input file between line 22 col 1 and line 24 col 58 debug: svf.c:482 urj_svf_compare_tdo(): Expected : 00000000000000000000000000001 00000000000000000000000000000000000010001000000000100000001010100010000010000000 00101000001010100010100010101000001010000000001000001000101010000000000010000010001 debug: svf.c:483 urj_svf_compare_tdo(): Mask : 000000000000000000000000000010000 00000011000010101110000100101000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000 debug: svf.c:484 urj_svf_compare_tdo(): TDO data : 010001000001000000000001010 110011000011000000001010000100000000000000011000000000000000000000010000000000 000001000000000000000101101011011110001010111100111111111011110111000111011110 110001000 error: svf_bison.y:451 urj_svf_error(): Error occurred for SVF command, line 21, column 0-57: SDR. [...] on the first try (sample, extest, sample from scan inputs) and [...] debug: state.c:66 urj_tap_state_dump_2(): tap_state: UPDATE_DR =(tms:0)=> RUN_TEST_IDLE svf.c:473 urj_svf_compare_tdo(): Error svf: mismatch at position 190 for TDO svf.c:479 urj_svf_compare_tdo(): in input file between line 20 col 1 and line 22 col 58 debug: svf.c:482 urj_svf_compare_tdo(): Expected : 00000000000000000000000000000 00000000000000000000000000000000000010001000000000100000001010100010000010000000 00101000001110100010100010101000010100000000010000010001010100000000000100000100 010 debug: svf.c:483 urj_svf_compare_tdo(): Mask : 00000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000001100000000000000000000111100000000110000110011111100000000001100001100 11 debug: svf.c:484 urj_svf_compare_tdo(): TDO data : 010001000001000000000001010 110011000011000000001010000100000000000000011000000000000000000000010000000000 000001000000000000000101101011011110001010111100111111111011110111000111011110 110001000 error: svf_bison.y:451 urj_svf_error(): Error occurred for SVF command, line 19, column 0-57: SDR. [...] (extest only, testing internal bits and enables...)Article: 158012
Nevermind.. looks like I got the endianness wrong(again)...Article: 158013
Hi,
When I try to install Xilinx Vivado on 64-bit x86_64 machine,
I get the following error:
$ ./xsetup
ERROR: This installation is not supported on 32 bit platforms.
The reason is, that xsetup erroneously uses "uname -i" instead of "uname -m" to check the architecture:
# ERROR out if this installation is running on 32 bit OS
# and does not support 32 bit installation
if [ "$(uname -i)" != "x86_64" ]; then
# check that the 32 bit library directory exist or not
lnx32LibDir="${workingDir}/lib/lnx32.o"
if [ ! -d $lnx32LibDir ]; then
# terminate with an ERROR
echo "ERROR: This installation is not supported on 32 bit platforms."
exit 1;
fi
fi
To fix it, you should replace "uname -i" with "uname -m":
# ERROR out if this installation is running on 32 bit OS
# and does not support 32 bit installation
if [ "$(uname -m)" != "x86_64" ]; then
# check that the 32 bit library directory exist or not
lnx32LibDir="${workingDir}/lib/lnx32.o"
if [ ! -d $lnx32LibDir ]; then
# terminate with an ERROR
echo "ERROR: This installation is not supported on 32 bit platforms."
exit 1;
fi
fi
--
HTH & Regards,
Wojtek
Article: 158014Hi, I need to design a sub-module with 128-bit input and output stream interfaces (4 DWORDs/cycle) which can split the stream at arbitrary DWORD boundaries. Example input: DW3 DW2 DW1 DW0 DW7 DW6 DW5 DW4 DWB DWA DW9 DW8 Example output (stream was split after DW4 and re-starts with a full 128-bit word): DW3 DW2 DW1 DW0 - - - DW4 DW8 DW7 DW6 DW5 - DWB DWA DW9 Before I implement something naively in VHDL, I was wondering how this kind of circuit is called and whether there are any standard architectures for it. The application is, by the way, PCIe TLP splitting and header insertion. Thanks, Guy.Article: 158015
Guy Eschemann <Guy.Eschemann@gmail.com> wrote: > Hi, I need to design a sub-module with 128-bit input and > output stream interfaces (4 DWORDs/cycle) which can split the > stream at arbitrary DWORD boundaries. > Example input: > DW3 DW2 DW1 DW0 > DW7 DW6 DW5 DW4 > DWB DWA DW9 DW8 It is what you put in the data path of a processor that doesn't require data to be aligned. To me, it is related to a barrel shifter, though others might call itsomething else. > Example output (stream was split after DW4 and re-starts with a > full 128-bit word): > DW3 DW2 DW1 DW0 > - - - DW4 > DW8 DW7 DW6 DW5 > - DWB DWA DW9 > Before I implement something naively in VHDL, I was wondering > how this kind of circuit is called and whether there are any > standard architectures for it. The application is, by the way, > PCIe TLP splitting and header insertion. -- glenArticle: 158016
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > Guy Eschemann <Guy.Eschemann@gmail.com> wrote: > > Hi, I need to design a sub-module with 128-bit input and > > output stream interfaces (4 DWORDs/cycle) which can split the > > stream at arbitrary DWORD boundaries. > > > Example input: > > > DW3 DW2 DW1 DW0 > > DW7 DW6 DW5 DW4 > > DWB DWA DW9 DW8 > > It is what you put in the data path of a processor that doesn't > require data to be aligned. To me, it is related to a barrel > shifter, though others might call itsomething else. Seems to me to be a FIFO welded to a barrel shifter - buffer the incoming data, pick somewhere between 0 and 4 words, shift them into place. It's slightly different from a normal barrel shifter - words can only go 'downstream', and one of the inputs is 'padding', but that's basically what it is - a big pile of muxes. I doubt you'll find an off-the-shelf component: it'll probably be less work to implement it yourself. TheoArticle: 158017
Theo Markettos wrote: > glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >> Guy Eschemann <Guy.Eschemann@gmail.com> wrote: >>> Hi, I need to design a sub-module with 128-bit input and >>> output stream interfaces (4 DWORDs/cycle) which can split the >>> stream at arbitrary DWORD boundaries. >> >>> Example input: >> >>> DW3 DW2 DW1 DW0 >>> DW7 DW6 DW5 DW4 >>> DWB DWA DW9 DW8 >> It is what you put in the data path of a processor that doesn't >> require data to be aligned. To me, it is related to a barrel >> shifter, though others might call itsomething else. > > Seems to me to be a FIFO welded to a barrel shifter - buffer the incoming > data, pick somewhere between 0 and 4 words, shift them into place. It's > slightly different from a normal barrel shifter - words can only go > 'downstream', and one of the inputs is 'padding', but that's basically what > it is - a big pile of muxes. > > I doubt you'll find an off-the-shelf component: it'll probably be less work > to implement it yourself. > > Theo Not really a FIFO, just a pipeline stage so you can concatenate two successive 128-bit input words and then use a variable part-select on that (you could code the part-select operation as a barrel-shift followed by a fixed part-select). -- GaborArticle: 158018
For those who download the .bin file (the net installer) add --keep argument to the command line to get to the xsetup file for editing. Wise to be in an empty directory when running the installer this way.Article: 158019
I have several fifos that are small and implemented as distributed ram.There are some timing violations reported on paths between source register of fifo control signals(e.g. read signal) and fifo data output. This raised some question in my head as how timing is assessed for such fifos (or SRL for that matter). A fifo or SRL chain uses luts plus output register. Wouldn't that mean there is inherently a long path to the output register or should we say it is long but not combinatorial? Is there anyway to improve timing in such designs like fifos or SRL chains. Regards Kaz --------------------------------------- Posted through http://www.FPGARelated.comArticle: 158020
kaz wrote: > I have several fifos that are small and implemented as distributed > ram.There are some timing violations reported on paths between source > register of fifo control signals(e.g. read signal) and fifo data output. > > This raised some question in my head as how timing is assessed for such > fifos (or SRL for that matter). A fifo or SRL chain uses luts plus output > register. Wouldn't that mean there is inherently a long path to the output > register or should we say it is long but not combinatorial? Is there > anyway to improve timing in such designs like fifos or SRL chains. > > Regards > > Kaz > > --------------------------------------- > Posted through http://www.FPGARelated.com What you're asking is device-related. What FPGA family are you using? Generally speaking, Xilinx devices can implement distributed memory FIFO pretty well, but you need to limit the depth of the FIFO to get it to run at high clock rates. Also there's a big difference between common-clock FIFO and independent-clock FIFO. The first kind can be implemented in SRL, the second cannot. Also it would be good to see a full failing path from your timing report (.twr file) to see if this is a logic level issue or a routing length issue. -- GaborArticle: 158021
want to use dynamic range of array , so using "N" for converting an
incoming vector signal to integer. Using the specifc incoming port "Size"
gives me an error, while fixed vector produces perfect output.
architecture EXAMPLE of Computation is
signal size :std_logic_vector (7 downto 0);
process (ACLK, SLAVE_ARESETN) is
variable N: integer:=conv_integer ("00000111") ; ---WORKING
--variable N: integer:=conv_integer (size) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0
);
variable RAM :memory;
Only reason to do this type of coding is send as much data as possible to
FPGA .As I need to send Data from DDR to Custom IP via DMA in vivado may
be more than 100 MB. so kindly guide me if I am trying to implement in
wrong way as stated above.
I am thinking to make a counter to address ram, and have it reset when
it's greater than size but confused how to do it . Can anyone provide me
some example.
Thanks
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 158022Dear All, Why dynamic power after compilation complete equal to zero, any idea how can I calculate dynamic power at max freq in Quartus? Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 158023
On Friday, July 10, 2015 at 1:36:17 PM UTC-4, abd_elhamid_ wrote: > Dear All, > > Why dynamic power after compilation complete equal to zero, Read the Quartus warning messages that you got which tell you that you didn't provide either simulation vectors or default toggle rates. > any idea how > can I calculate dynamic power at max freq in Quartus? > Read about the PowerPlay Power Analyzer tool in the Quartus Manual. Kevin JenningsArticle: 158024
live4perfection <106037@fpgarelated> wrote:
> want to use dynamic range of array , so using "N" for converting an
> incoming vector signal to integer. Using the specifc incoming port "Size"
> gives me an error, while fixed vector produces perfect output.
Remember, VHDL describes hardware. Though it can also be used for
test benches and simulation. In hardware, you have to know
how big things are.
> architecture EXAMPLE of Computation is
>
> signal size :std_logic_vector (7 downto 0);
>
> process (ACLK, SLAVE_ARESETN) is
>
> variable N: integer:=conv_integer ("00000111") ; ---WORKING
>
> --variable N: integer:=conv_integer (size) ; -- Not working
> type memory is array (N downto 0 ) of std_logic_vector (31 downto 0
> );
> variable RAM :memory;
When you buy RAM chips from the store, you have to say how many
bits you want. That can't be a variable.
> Only reason to do this type of coding is send as much data as possible to
> FPGA .As I need to send Data from DDR to Custom IP via DMA in vivado may
> be more than 100 MB. so kindly guide me if I am trying to implement in
> wrong way as stated above.
That might mean an interface to an external DRAM. You write the
inteface, not the DRAM.
> I am thinking to make a counter to address ram, and have it reset when
> it's greater than size but confused how to do it . Can anyone provide me
> some example.
-- glen
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z