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On 8/18/2015 2:21 PM, KJ wrote: > On Tuesday, August 18, 2015 at 11:35:55 AM UTC-4, rickman wrote: >> >> I'm not sure what details of the routing the chip editors leave out. >> You only need to know what is connected to what, through what and what >> the delays for all those cases are. > > If you're trying to implement an open source toolchain you would likely need to know *how* to specify those connections via the programming bitstream. Well... yeah. That's the sticky wicket, knowing how to generate the bitstream. I think you missed the point of this subthread. -- RickArticle: 158151
On 8/18/2015 9:40 PM, Richard Damon wrote: > On 8/18/15 11:35 AM, rickman wrote: >> On 8/15/2015 8:32 AM, Richard Damon wrote: >>> >>> The chip editors tend to just show the LOGIC resources, not the details >>> of the routing resources. The manufactures tend to do a good job of >>> giving the detail of the logic blocks you are working with, as this is >>> the part of the design you tend to specify. Routing on the other hand >>> tends to not be something you care about, just that the routing 'works'. >>> When they have done a good job at designing the routing you don't notice >>> it, but there have been cases where the routing turned out not quite >>> flexible enough and you notice that you can't fill the device as well >>> before hitting routing issues. >> >> I'm not sure what details of the routing the chip editors leave out. You >> only need to know what is connected to what, through what and what the >> delays for all those cases are. Other than that, the routing does just >> "work". >> > > Look closely. The chip editor will normally show you the exact logic > element you are using with a precise location. The output will then go > out into a routing channel and on the the next logic logic cell(s) that > it goes to. It may even show you the the various rows and columns of > routing it is going through. Those rows and columns are made of a > (large) number of distinct wires with routing resources connecting > outputs to select lines and select lines being brought into the next > piece of routing/logic. Which wire is being used will not be indicated, > nor are all the wires interchangeable, so which wire can matter for > fitting. THIS is the missing information. I can't speak with total authority since I have not used a chip editor in a decade. But when I have used them they showed sufficient detail that I could control every aspect of the routing. In fact, it showed every routing resource in sufficient detail that the logic components were rather small and were a bit hard to see. When you say which wire is used is not shown, how would you be able to do manual routing if the details are not there? Manual routing and logic is the purpose of the chip editors, no? >>>>> I have had to work with the factory on things like this. I had a very >>>>> full FPGA and needed to make a small change. With the change I had >>>>> some >>>>> over clogged routing, but if I removed all internal constraints the >>>>> fitter couldn't find a fit. Working with someone who did know the >>>>> details, we were able to relax just a few internal constraints and get >>>>> the system to fit the design. He did comment that my design was >>>>> probably >>>>> the fullest design he had seen in the wild, we had grown to about 95% >>>>> logic utilization. >>>> >>>> Yeah, that's pretty full. I start to worry around 80%, but I've never >>>> actually had one fail to route other than the ones I tried to help by >>>> doing placement, lol. >>>> >>> >>> They suggest that you consider 75-80% to be "Full". This design started >>> in the 70% level but we were adding capability to the system and the >>> density grew. (And were already using the largest chip for the >>> footprint). Our next step was to redo the board and get the usage back >>> down. When we hit the issue we had a mostly working design but were >>> fixing the one last bug, and that was when the fitter threw its fit. >> >> The "full" utilization number is approximate because it depends on the >> details of the design. Some designs can get to higher utilization >> numbers, others less. As a way of pointing out that the routing is the >> part of the chip that uses the most space while the logic is smaller, >> Xilinx sales people used to say, "We sell you the routing and give you >> the logic for free." The point is the routing usually limits your >> design rather than the logic. If you want to be upset about utilization >> numbers, ask them how much of your routing gets used! It's *way* below >> 80%. >> > And this is why the keep the real details of the routing proprietary. > (Not to keep you from getting upset) The serious design work goes into > figuring out how much they really need per cell. If they could figure > out a better allocation that let them cut the routing per cell by 10%, > they could give you 10% more logic for free. If they goof and provide > too little routing, you see the resources that you were sold (since they > advertize the logic capability) as being wasted by some 'dumb design > limitation'. There have been families that got black eyes of having > routing problems, and thus should be avoided for 'serious' work. I don't follow the logic. There are always designs that deviate from the typical utilization in both directions. Whether you can see what details in the chip editor has nothing to do with user satisfaction since you can read the utilization numbers in the reports and don't need to see any routing, etc. -- RickArticle: 158152
On Tuesday, March 17, 2015 at 4:58:39 AM UTC+3, princesse91 wrote: > Hi Ahmed, > Can you tell me how did you generate VHDL from Handel-C?? I'm working on the conversion from c++ to vhdl with handel-c but i didn't know how to do it.. > Thanks It's very easy use interfaces for inputs and outputs in your Handel-C code. Then change the debug option into VHDL or Verilog or EDIF or SystemC. Be sure to use Mentor Graghics DK Design Suite 5.Article: 158153
On Friday, 21 August 2015 18:36:59 UTC+1, ahmed...@gmail.com wrote: > On Tuesday, March 17, 2015 at 4:58:39 AM UTC+3, princesse91 wrote: > > Hi Ahmed, > > Can you tell me how did you generate VHDL from Handel-C?? I'm working on the conversion from c++ to vhdl with handel-c but i didn't know how to do it.. > > Thanks > > It's very easy use interfaces for inputs and outputs in your Handel-C code. Then change the debug option into VHDL or Verilog or EDIF or SystemC. Be sure to use Mentor Graghics DK Design Suite 5. do you still have access to Mentor Graphics DK Design Suite 5? I thought this was now obsoleteArticle: 158154
On 22/08/2015 23:14, martinjpearson wrote: > On Friday, 21 August 2015 18:36:59 UTC+1, ahmed...@gmail.com wrote: >> On Tuesday, March 17, 2015 at 4:58:39 AM UTC+3, princesse91 wrote: >>> Hi Ahmed, >>> Can you tell me how did you generate VHDL from Handel-C?? I'm working on the conversion from c++ to vhdl with handel-c but i didn't know how to do it.. >>> Thanks >> >> It's very easy use interfaces for inputs and outputs in your Handel-C code. Then change the debug option into VHDL or Verilog or EDIF or SystemC. Be sure to use Mentor Graghics DK Design Suite 5. > > do you still have access to Mentor Graphics DK Design Suite 5? I thought this was now obsolete > I think DK is not (yet) obsolete but barely alive, the latest version is 5.4_1 released back in 2011. Nowadays anybody interested in C/C++/SystemC synthesis will have a wide choice from free to CatapultC. Hans www.ht-lab.comArticle: 158155
On Sunday, 23 August 2015 08:50:13 UTC+1, HT-Lab wrote: > On 22/08/2015 23:14, martinjpearson wrote: > > On Friday, 21 August 2015 18:36:59 UTC+1, ahmed...@gmail.com wrote: > >> On Tuesday, March 17, 2015 at 4:58:39 AM UTC+3, princesse91 wrote: > >>> Hi Ahmed, > >>> Can you tell me how did you generate VHDL from Handel-C?? I'm working on the conversion from c++ to vhdl with handel-c but i didn't know how to do it.. > >>> Thanks > >> > >> It's very easy use interfaces for inputs and outputs in your Handel-C code. Then change the debug option into VHDL or Verilog or EDIF or SystemC. Be sure to use Mentor Graghics DK Design Suite 5. > > > > do you still have access to Mentor Graphics DK Design Suite 5? I thought this was now obsolete > > > I think DK is not (yet) obsolete but barely alive, the latest version is > 5.4_1 released back in 2011. Nowadays anybody interested in > C/C++/SystemC synthesis will have a wide choice from free to CatapultC. > > Hans > www.ht-lab.com Our site licence has now expired and Mentor will not renew it. Anyone have any experience of Impulse C? I'm drawn to the CSP based architectureArticle: 158156
On 08/26/2015 02:03 PM, David Brown wrote: > On 26/08/15 01:20, Johann Klammer wrote: >> Hello, >> How are typical CPLD input muxen build up? > > (For other posters, a CPLD is a "complex programmable logic device". It > is a bit like a simple FPGA - there is no fixed dividing line between > them, but CPLD's tend to be built from a fairly small number of fairly > complex "macrocells" containing a flip-flop and a set of AND/OR trees > for logic operations, while FPGA's tend to have a large number of much > simpler cells and use lookup tables for logic.) > >> >> I was looking at the ATMEL .jed files and >> their input muxen seem to be a series of sparse, one- >> hot encoded bitfields with fewer bits >> than inputs in total. So now I am wondering: >> How are they distributed? >> Just the name of the permutation problem might help, or >> some other relevant search terms. >> > > You are unlikely to be able to make sense of the programming file for > even the simplest of PLD. It is not information that is published by > the manufacturers, making it almost impossible to figure out which bits > are used for the routing, the AND/OR tables, and other features. But it Their .jed files have comments... In this case I know which is which. guessing the and-matrix assignment is trivial(done from the input equations). The meaning of the MC fuses can be found by trial&error, I believe. the mux feeding those input lines is different... there's 40 lines coming into the and array from the outside(80 counting both inv and noninv ones). +16 local loopbacks(not muxed)... but the widths of the 40 muxes are not sufficiently large to do arbitrary selections from the inputs. as far as I can tell from their docs and .jed their devices have dev: 1502 1504 1508 input lines: 68 132 260 mux width: 5 8 27 (40 muxes in their input switch) [...]Article: 158157
I was just wondering... why is this group so quiet? With lots of interesting news like: Microsoft Extends FPGA Reach From Bing To Deep Learning - http://www.theplatform.net/2015/08/27/microsoft-extends-fpga-reach-from-bing-to-deep-learning/ China's FPGA Company - http://www.electronicsweekly.com/mannerisms/fpga/chinas-fpga-company-2015-09/ AMD patent filing hints at FPGA plans in the pipeline - http://www.theregister.co.uk/2015/08/11/amd_patent_filing_hints_at_fpga_plans_in_the_pipeline/ I would have expected at least a tiny bit of chatter... Mike.Article: 158158
On 06/09/2015 22:24, Mike Field wrote: > I was just wondering... why is this group so quiet? Unfortunately there are too many other sources like LinkedIn, Stackoverflow, Vendors mailing lists.... I guess young(?) engineers find usenet not "cool" enough, no up/down votes, no tags for code, no need for a news server, etc Hans www.ht-lab.com > > With lots of interesting news like: > > Microsoft Extends FPGA Reach From Bing To Deep Learning - http://www.theplatform.net/2015/08/27/microsoft-extends-fpga-reach-from-bing-to-deep-learning/ > > China's FPGA Company - http://www.electronicsweekly.com/mannerisms/fpga/chinas-fpga-company-2015-09/ > > AMD patent filing hints at FPGA plans in the pipeline - http://www.theregister.co.uk/2015/08/11/amd_patent_filing_hints_at_fpga_plans_in_the_pipeline/ > > I would have expected at least a tiny bit of chatter... > > Mike. >Article: 158159
>I was just wondering... why is this group so quiet? > because our next door neighbor is very noisy. Look at DSPrelated.com guys, 4 or five of them keep answering everyone, may be they robot members. Kaz --------------------------------------- Posted through http://www.FPGARelated.comArticle: 158160
On 9/6/2015 5:24 PM, Mike Field wrote: > I was just wondering... why is this group so quiet? > > With lots of interesting news like: > > Microsoft Extends FPGA Reach From Bing To Deep Learning - http://www.theplatform.net/2015/08/27/microsoft-extends-fpga-reach-from-bing-to-deep-learning/ > > China's FPGA Company - http://www.electronicsweekly.com/mannerisms/fpga/chinas-fpga-company-2015-09/ > > AMD patent filing hints at FPGA plans in the pipeline - http://www.theregister.co.uk/2015/08/11/amd_patent_filing_hints_at_fpga_plans_in_the_pipeline/ AMD getting into the FPGA market would indeed be news. I seriously doubt that will be happening. There are a lot of financial and patent barriers. I can't currently read any of your links, but it could be interesting if China did get into the FPGA market. But do you think they will market much in the US? I expect they will be pushed as alternatives to the big name FPGAs for use in many Chinese products which are more and more designed in China. There aren't many Chinese chips with much complexity that are used in other parts of the world. It can be very hard to get much info that is clear. Microsoft has their hands in lots of things. That doesn't mean they will bring it to fruition. -- RickArticle: 158161
On Mon, 07 Sep 2015 10:25:48 -0500, kaz wrote: >>I was just wondering... why is this group so quiet? >> >> > because our next door neighbor is very noisy. Look at DSPrelated.com > guys, > 4 or five of them keep answering everyone, may be they robot members. If so I'm a pretty damned well programmed robot! (Actually, I think a USENET question-answering robot would be a cool thing for someone to try. After lurking for about a year you can answer most questions by just regurgitating answers to previous questions.) -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 158162
> >(Actually, I think a USENET question-answering robot would be a cool >thing for someone to try. After lurking for about a year you can answer >most questions by just regurgitating answers to previous questions.) > >-- > >Tim Wescott >Wescott Design Services >http://www.wescottdesign.com The problem of DSPRelated G5 (Gang of 5) is not just answering posts but soon they 5 member gang start fighting each other on their comments and thoughts. It is in most cases waste of time and words to find any useful post. Kaz --------------------------------------- Posted through http://www.FPGARelated.comArticle: 158163
On Tue, 08 Sep 2015 14:25:39 -0500, kaz wrote: >>(Actually, I think a USENET question-answering robot would be a cool >>thing for someone to try. After lurking for about a year you can answer > >>most questions by just regurgitating answers to previous questions.) >> >>-- >> >>Tim Wescott Wescott Design Services http://www.wescottdesign.com > > The problem of DSPRelated G5 (Gang of 5) is not just answering posts but > soon they 5 member gang start fighting each other on their comments and > thoughts. > > It is in most cases waste of time and words to find any useful post. You may have a point there. So, if I'm going to pass a Turing test does this mean that I need to get offended easily? -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 158164
Den mandag den 7. september 2015 kl. 20.11.10 UTC+2 skrev rickman: > On 9/6/2015 5:24 PM, Mike Field wrote: > > I was just wondering... why is this group so quiet? > > > > With lots of interesting news like: > > > > Microsoft Extends FPGA Reach From Bing To Deep Learning - http://www.theplatform.net/2015/08/27/microsoft-extends-fpga-reach-from-bing-to-deep-learning/ > > > > China's FPGA Company - http://www.electronicsweekly.com/mannerisms/fpga/chinas-fpga-company-2015-09/ > > > > AMD patent filing hints at FPGA plans in the pipeline - http://www.theregister.co.uk/2015/08/11/amd_patent_filing_hints_at_fpga_plans_in_the_pipeline/ > > AMD getting into the FPGA market would indeed be news. I seriously > doubt that will be happening. There are a lot of financial and patent > barriers. > > I can't currently read any of your links, but it could be interesting if > China did get into the FPGA market. But do you think they will market > much in the US? I expect they will be pushed as alternatives to the big > name FPGAs for use in many Chinese products which are more and more > designed in China. There aren't many Chinese chips with much complexity > that are used in other parts of the world. It can be very hard to get > much info that is clear. > the company is Gowin semiconductor, http://hackaday.com/2015/08/24/two-new-fpga-families-designed-in-china/ maybe they will have learned something from Espressif and their ~1$ wifi chip As soon as English documentation and tools started to appear everyone and his cousin started doing stuff cool with them -LasseArticle: 158165
Tim Wescott wrote: > On Tue, 08 Sep 2015 14:25:39 -0500, kaz wrote: > > >>> (Actually, I think a USENET question-answering robot would be a cool >>> thing for someone to try. After lurking for about a year you can answer >> >>> most questions by just regurgitating answers to previous questions.) >>> >>> -- >>> >>> Tim Wescott Wescott Design Services http://www.wescottdesign.com >> >> The problem of DSPRelated G5 (Gang of 5) is not just answering posts but >> soon they 5 member gang start fighting each other on their comments and >> thoughts. >> >> It is in most cases waste of time and words to find any useful post. > > You may have a point there. So, if I'm going to pass a Turing test does > this mean that I need to get offended easily? > I think people do this when they think they might not pass a Turing test. -- Les CargillArticle: 158166
On Tue, 08 Sep 2015 18:09:22 -0500, Les Cargill wrote: > Tim Wescott wrote: >> On Tue, 08 Sep 2015 14:25:39 -0500, kaz wrote: >> >> >>>> (Actually, I think a USENET question-answering robot would be a cool >>>> thing for someone to try. After lurking for about a year you can >>>> answer >>> >>>> most questions by just regurgitating answers to previous questions.) >>>> >>>> -- >>>> >>>> Tim Wescott Wescott Design Services http://www.wescottdesign.com >>> >>> The problem of DSPRelated G5 (Gang of 5) is not just answering posts >>> but soon they 5 member gang start fighting each other on their >>> comments and thoughts. >>> >>> It is in most cases waste of time and words to find any useful post. >> >> You may have a point there. So, if I'm going to pass a Turing test >> does this mean that I need to get offended easily? >> >> > > I think people do this when they think they might not pass a Turing > test. Are you implying I can't pass a Turing test? I'm offended. Or maybe I'm simulating. Hmm. How to tell? -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 158167
Tim Wescott wrote: > On Tue, 08 Sep 2015 18:09:22 -0500, Les Cargill wrote: > >> Tim Wescott wrote: >>> On Tue, 08 Sep 2015 14:25:39 -0500, kaz wrote: >>> >>> >>>>> (Actually, I think a USENET question-answering robot would be a cool >>>>> thing for someone to try. After lurking for about a year you can >>>>> answer >>>> >>>>> most questions by just regurgitating answers to previous questions.) >>>>> >>>>> -- >>>>> >>>>> Tim Wescott Wescott Design Services http://www.wescottdesign.com >>>> >>>> The problem of DSPRelated G5 (Gang of 5) is not just answering posts >>>> but soon they 5 member gang start fighting each other on their >>>> comments and thoughts. >>>> >>>> It is in most cases waste of time and words to find any useful post. >>> >>> You may have a point there. So, if I'm going to pass a Turing test >>> does this mean that I need to get offended easily? >>> >>> >> >> I think people do this when they think they might not pass a Turing >> test. > > Are you implying I can't pass a Turing test? > I am not sure I can because lake bloop forble. > I'm offended. Or maybe I'm simulating. Hmm. How to tell? > -- Les CargillArticle: 158168
>Tim Wescott wrote: >> On Tue, 08 Sep 2015 18:09:22 -0500, Les Cargill wrote: >> >>> Tim Wescott wrote: >>>> On Tue, 08 Sep 2015 14:25:39 -0500, kaz wrote: >>>> >>>> >>>>>> (Actually, I think a USENET question-answering robot would be a cool >>>>>> thing for someone to try. After lurking for about a year you can >>>>>> answer >>>>> >>>>>> most questions by just regurgitating answers to previous questions.) >>>>>> >>>>>> -- >>>>>> >>>>>> Tim Wescott Wescott Design Services http://www.wescottdesign.com >>>>> >>>>> The problem of DSPRelated G5 (Gang of 5) is not just answering posts >>>>> but soon they 5 member gang start fighting each other on their >>>>> comments and thoughts. >>>>> >>>>> It is in most cases waste of time and words to find any useful post. >>>> >>>> You may have a point there. So, if I'm going to pass a Turing test >>>> does this mean that I need to get offended easily? >>>> >>>> >>> >>> I think people do this when they think they might not pass a Turing >>> test. >> >> Are you implying I can't pass a Turing test? >> > >I am not sure I can because lake bloop forble. > > >> I'm offended. Or maybe I'm simulating. Hmm. How to tell? >> > >-- >Les Cargill This forum is now under attack by the Robots from next door, really. kaz --------------------------------------- Posted through http://www.FPGARelated.comArticle: 158169
On 9/8/2015 5:20 PM, lasselangwadtchristensen@gmail.com wrote: > Den mandag den 7. september 2015 kl. 20.11.10 UTC+2 skrev rickman: >> On 9/6/2015 5:24 PM, Mike Field wrote: >>> I was just wondering... why is this group so quiet? >>> >>> With lots of interesting news like: >>> >>> Microsoft Extends FPGA Reach From Bing To Deep Learning - http://www.theplatform.net/2015/08/27/microsoft-extends-fpga-reach-from-bing-to-deep-learning/ >>> >>> China's FPGA Company - http://www.electronicsweekly.com/mannerisms/fpga/chinas-fpga-company-2015-09/ >>> >>> AMD patent filing hints at FPGA plans in the pipeline - http://www.theregister.co.uk/2015/08/11/amd_patent_filing_hints_at_fpga_plans_in_the_pipeline/ >> >> AMD getting into the FPGA market would indeed be news. I seriously >> doubt that will be happening. There are a lot of financial and patent >> barriers. >> >> I can't currently read any of your links, but it could be interesting if >> China did get into the FPGA market. But do you think they will market >> much in the US? I expect they will be pushed as alternatives to the big >> name FPGAs for use in many Chinese products which are more and more >> designed in China. There aren't many Chinese chips with much complexity >> that are used in other parts of the world. It can be very hard to get >> much info that is clear. >> > > the company is Gowin semiconductor, > > http://hackaday.com/2015/08/24/two-new-fpga-families-designed-in-china/ > > maybe they will have learned something from Espressif and their ~1$ wifi chip > As soon as English documentation and tools started to appear everyone and his cousin started doing stuff cool with them Unfortunately I am still fighting computer problems. I am unable to view a link unless I write it down and copy it to another machine. :( -- RickArticle: 158170
Hi, Good day to all. If suppose i received a HDL code for FPGA related design and it is obfuscated, how to understand it??? Is there any systematic procedure to perform it?? Thank you in advance. Regards, SUMATHI G. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 158171
>Hi, > >Good day to all. > >If suppose i received a HDL code for FPGA related design and it is >obfuscated, how to understand it??? Is there any systematic procedure to >perform it?? > >Thank you in advance. > >Regards, >SUMATHI G. > > >--------------------------------------- >Posted through http://www.FPGARelated.com It could be a nightmare. If you just want to view it as blackbox then run a testbench of your own with your inputs and reference outputs. Many designers have no mercy about readability or comments or documentation. Alternatively post this on DSPRelated and I guarantee you will get 89 replies at least from the 5 robots there. Seriously Kaz --------------------------------------- Posted through http://www.FPGARelated.comArticle: 158172
Den onsdag den 9. september 2015 kl. 08.58.47 UTC+2 skrev rickman: > On 9/8/2015 5:20 PM, lasselangwadtchristensen@gmail.com wrote: > > Den mandag den 7. september 2015 kl. 20.11.10 UTC+2 skrev rickman: > >> On 9/6/2015 5:24 PM, Mike Field wrote: > >>> I was just wondering... why is this group so quiet? > >>> > >>> With lots of interesting news like: > >>> > >>> Microsoft Extends FPGA Reach From Bing To Deep Learning - http://www.theplatform.net/2015/08/27/microsoft-extends-fpga-reach-from-bing-to-deep-learning/ > >>> > >>> China's FPGA Company - http://www.electronicsweekly.com/mannerisms/fpga/chinas-fpga-company-2015-09/ > >>> > >>> AMD patent filing hints at FPGA plans in the pipeline - http://www.theregister.co.uk/2015/08/11/amd_patent_filing_hints_at_fpga_plans_in_the_pipeline/ > >> > >> AMD getting into the FPGA market would indeed be news. I seriously > >> doubt that will be happening. There are a lot of financial and patent > >> barriers. > >> > >> I can't currently read any of your links, but it could be interesting if > >> China did get into the FPGA market. But do you think they will market > >> much in the US? I expect they will be pushed as alternatives to the big > >> name FPGAs for use in many Chinese products which are more and more > >> designed in China. There aren't many Chinese chips with much complexity > >> that are used in other parts of the world. It can be very hard to get > >> much info that is clear. > >> > > > > the company is Gowin semiconductor, > > > > http://hackaday.com/2015/08/24/two-new-fpga-families-designed-in-china/ > > > > maybe they will have learned something from Espressif and their ~1$ wifi chip > > As soon as English documentation and tools started to appear everyone and his cousin started doing stuff cool with them > > Unfortunately I am still fighting computer problems. I am unable to > view a link unless I write it down and copy it to another machine. :( > ok, afaict: 55nm, 1152 and 8640 LUTs, on-chip random access flash, Synopsys' Synplify Pro for synthesis, qfp100 to BGAs -LasseArticle: 158173
On 09/09/2015 15:07, kaz wrote: >> Hi, >> >> Good day to all. >> >> If suppose i received a HDL code for FPGA related design and it is >> obfuscated, how to understand it??? Is there any systematic procedure to >> perform it?? >> >> Thank you in advance. >> >> Regards, >> SUMATHI G. >> >> >> --------------------------------------- >> Posted through http://www.FPGARelated.com > > It could be a nightmare. If you just want to view it as blackbox then run > a testbench of your own with your inputs and reference outputs. Many > designers have no mercy about readability or comments or documentation. > > Alternatively post this on DSPRelated and I guarantee you will get 89 > replies at least from the 5 robots there. Seriously > > Kaz > --------------------------------------- > Posted through http://www.FPGARelated.com > Depends on how complex. Look at the generated RTL perhaps.....Article: 158174
On Thursday, 10 September 2015 00:11:48 UTC+12, Sumathigokul wrote: > Hi, >=20 > Good day to all. >=20 > If suppose i received a HDL code for FPGA related design and it is > obfuscated, how to understand it??? Is there any systematic procedure to > perform it?? >=20 > Thank you in advance. >=20 > Regards, > SUMATHI G. >=20 >=20 > --------------------------------------- > Posted through http://www.FPGARelated.com Wouldn't hold out much hope. On anything sufficiently complex you can have = a full description of the low-level implementation, but not enough context = to give full understanding of what is actually being implemented. e.g. Take this description - what does it do?=20 There is a single bit register, and it gets XORed with the value that is fr= om a 1-bit x 256 table, indexed by the 8-bit input, After that the 8-bit nu= mber plus the bit is used to index another 10-bit x 512 table, containing s= eemingly random values, to generate the final output value.
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