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Messages from 44025

Article: 44025
Subject: Virtex 2 Pro Board
From: "Jerry Francis" <jerryf@vt.edu>
Date: Mon, 10 Jun 2002 09:21:09 -0400
Links: << >>  << T >>  << A >>
Hi All,

Is there a Virtex II Pro evaluation board that I can buy with a PowerPC in
it?  I haven't seen any yet.

Thanks,
Jerry



Article: 44026
Subject: Re: where did my MHz go!
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Mon, 10 Jun 2002 14:54:43 +0100
Links: << >>  << T >>  << A >>
Rick,

Thanks for your quick response.

> Any or all of those things might help but before you get started trying
you'll
> need to do get a full timing report from TimingAnalyser or (command line)
TRCE.
> This should give you a breakdown of failing paths but before you run this
its
> probably worth re-doing your design and add some temporary pin assignments
on
> CLK,X,Y so its ``connected to something''.

TRCE output is below.  I do have pin assignments for CLK, X and Y already.

The Xilinx Timing Analzer says the following as hints about the first
offender:

This path has net "v_617_p3(0)" with high fanout of 22.

High fanout suggestions.

-Duplicate driver and direct synthesis tools to not remove duplicate logic.

-Use specific net fanout control on problem net if allowed by synthesis
tool.

and

This path has net "AdderChain_tap30_sub_v17_1(1)" with long delay of 4.07ns.

Long net delay suggestions.

-Try a higher placement effort (4 or 5).

-Use map -timing option. In Project Navigator this is an Advanced Option in
the Map Properties.

-Duplicate the net source.

-Floorplan the design to bring logic closer together.

I can try all of these things in turn to see what makes the most (if any)
difference - if however you or anyone else could direct me as to which route
would be most fruitful (in your experience) I would be very grateful.

This is my first forage into the world of timing reports etc. seems like a
bit of a black art so far!

Cheers,

Ken




============================================================================
====
Timing constraint: TS_CLK_IN_CLK0 = PERIOD TIMEGRP "CLK_IN_CLK0" TS_CLK *
1.000000  HIGH 50.000 % ;

 42864 items analyzed, 4 timing errors detected.
 Minimum period is  10.969ns.
----------------------------------------------------------------------------
----
Slack:                  -0.969ns (requirement - (data path - negative clock
skew))
  Source:               v_617_p3[0]
  Destination:          Y[1]
  Requirement:          10.000ns
  Data Path Delay:      10.879ns (Levels of Logic = 3)
  Negative Clock Skew:  -0.090ns
  Source Clock:         clki rising at 0.000ns
  Destination Clock:    clki rising at 10.000ns

  Data Path: v_617_p3[0] to Y[1]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    CLB_R24C21.S0.XQ     Tcko                  1.292   v_617_p3(0)
                                                       v_617_p3[0]
    CLB_R24C3.S0.F4      net (fanout=22)       2.376   v_617_p3(0)
    CLB_R24C3.S0.Y       Topy                  1.936
AdderChain_tap30_sub_v17_1(0)

AdderChain_tap30_sub_v17_1_axb_0

AdderChain_tap30_sub_v17_1_cry_0

AdderChain_tap30_sub_v17_1_s_1
    D14.O                net (fanout=1)        4.067
AdderChain_tap30_sub_v17_1(1)
    D14.CLK              Tioock                1.208   Y(1)
                                                       Y[1]
    -------------------------------------------------  ---------------------
------
    Total                                     10.879ns (4.436ns logic,
6.443ns route)
                                                       (40.8% logic, 59.2%
route)

----------------------------------------------------------------------------
----
Slack:                  -0.964ns (requirement - (data path - negative clock
skew))
  Source:               v_617_p3[0]
  Destination:          Y[3]
  Requirement:          10.000ns
  Data Path Delay:      10.874ns (Levels of Logic = 4)
  Negative Clock Skew:  -0.090ns
  Source Clock:         clki rising at 0.000ns
  Destination Clock:    clki rising at 10.000ns

  Data Path: v_617_p3[0] to Y[3]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    CLB_R24C21.S0.XQ     Tcko                  1.292   v_617_p3(0)
                                                       v_617_p3[0]
    CLB_R24C3.S0.F4      net (fanout=22)       2.376   v_617_p3(0)
    CLB_R24C3.S0.COUT    Topcyf                1.486
AdderChain_tap30_sub_v17_1(0)

AdderChain_tap30_sub_v17_1_axb_0

AdderChain_tap30_sub_v17_1_cry_0

AdderChain_tap30_sub_v17_1_cry_1
    CLB_R23C3.S0.CIN     net (fanout=1)        0.000
AdderChain_tap30_sub_v17_1_cry_1/O
    CLB_R23C3.S0.Y       Tciny                 0.545
AdderChain_tap30_sub_v17_1(2)

AdderChain_tap30_sub_v17_1_cry_2

AdderChain_tap30_sub_v17_1_s_3
    D15.O                net (fanout=1)        3.967
AdderChain_tap30_sub_v17_1(3)
    D15.CLK              Tioock                1.208   Y(3)
                                                       Y[3]
    -------------------------------------------------  ---------------------
------
    Total                                     10.874ns (4.531ns logic,
6.343ns route)
                                                       (41.7% logic, 58.3%
route)

----------------------------------------------------------------------------
----
Slack:                  -0.278ns (requirement - (data path - negative clock
skew))
  Source:               v_261_p3[1]
  Destination:          Y[3]
  Requirement:          10.000ns
  Data Path Delay:      10.187ns (Levels of Logic = 4)
  Negative Clock Skew:  -0.091ns
  Source Clock:         clki rising at 0.000ns
  Destination Clock:    clki rising at 10.000ns

  Data Path: v_261_p3[1] to Y[3]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    CLB_R24C10.S1.YQ     Tcko                  1.292   v_261_p3(2)
                                                       v_261_p3[1]
    CLB_R24C3.S0.G3      net (fanout=13)       1.779   v_261_p3(1)
    CLB_R24C3.S0.COUT    Topcyg                1.396
AdderChain_tap30_sub_v17_1(0)

AdderChain_tap30_sub_v17_1_axb_1

AdderChain_tap30_sub_v17_1_cry_1
    CLB_R23C3.S0.CIN     net (fanout=1)        0.000
AdderChain_tap30_sub_v17_1_cry_1/O
    CLB_R23C3.S0.Y       Tciny                 0.545
AdderChain_tap30_sub_v17_1(2)

AdderChain_tap30_sub_v17_1_cry_2

AdderChain_tap30_sub_v17_1_s_3
    D15.O                net (fanout=1)        3.967
AdderChain_tap30_sub_v17_1(3)
    D15.CLK              Tioock                1.208   Y(3)
                                                       Y[3]
    -------------------------------------------------  ---------------------
------
    Total                                     10.187ns (4.441ns logic,
5.746ns route)
                                                       (43.6% logic, 56.4%
route)

----------------------------------------------------------------------------
----


1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |   10.969|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 4  Score: 2226

Constraints cover 42864 paths, 0 nets, and 3168 connections (100.0%
coverage)

Design statistics:
   Minimum period:  10.969ns (Maximum frequency:  91.166MHz)


Analysis completed Mon Jun 10 14:33:44 2002
----------------------------------------------------------------------------
----



Article: 44027
Subject: Re: where did my MHz go!
From: Ray Andraka <ray@andraka.com>
Date: Mon, 10 Jun 2002 13:55:36 GMT
Links: << >>  << T >>  << A >>
Choice of LOCs in the UCF can Absolutely affect the timing, and to an amazingly
large degree.  Run the timing analyzer or TRCE and set it to report on paths
failing timing constraints.  That will tell you what paths you have a problem
with.  Could be poor placement, too many levels of logic, or a high fanout
killing you.  Until you read the timing report, you have no idea of the
magnitude of the problem or where to start tweaking to fix it.


Ken Mac wrote:

>
> Anyway, after mapping, the maximum clock frequency is reported to be
> 138.947MHz.
>
> But, after place and route, the max clock freq. is reported to be 91.166MHz.
>
> Where could I be losing so much MHz?  Can my choice of LOCs in the UCF
> affect the max clock freq.?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44028
Subject: Re: where did my MHz go!
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Mon, 10 Jun 2002 15:04:45 +0100
Links: << >>  << T >>  << A >>

Ray,

You are correct - it is high logic levels and fanout that is killing me (I
was generating the TRCE report and posting in response to Rick and in the
meantime you responded so the TRCE data is in my reply to Rick).

What is the definition of a "logic level"?  Is it the route of a signal
through e.g. a LUT or a MUX or is it just the route through any amount of
slice logic (in one slice) that is not a flip-flop?  If so, a <fully>
pipelined design would have a max logic level of 1 across the whole design
right?

I think I can do some tweaking to up the MHz - hopefully you guys can point
me in the right direction via the TRCE report!

Thanks for your time,

Ken

"Ray Andraka" <ray@andraka.com> wrote in message
news:3D04B098.CEE1727D@andraka.com...
> Choice of LOCs in the UCF can Absolutely affect the timing, and to an
amazingly
> large degree.  Run the timing analyzer or TRCE and set it to report on
paths
> failing timing constraints.  That will tell you what paths you have a
problem
> with.  Could be poor placement, too many levels of logic, or a high fanout
> killing you.  Until you read the timing report, you have no idea of the
> magnitude of the problem or where to start tweaking to fix it.



Article: 44029
Subject: Re: Virtex 2 Pro Board
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 10 Jun 2002 07:43:24 -0700
Links: << >>  << T >>  << A >>
Jerry,

We are in the early ES phase:  they are not going to be there for a little
while longer.  The parts are available (if you are already waiting in line).
Initially it is more important to supply the parts to customers who already
have boards waiting, than it is to supply parts to build evaluation boards.

SInce you have "edu" in your address, there is a specific program just getting
started for universities, as we think that a Virtex II Pro would be idea for
just about any class one takes in EECS.  Check out the University program on
the Xilinx website, and watch for details.

Austin


Jerry Francis wrote:

> Hi All,
>
> Is there a Virtex II Pro evaluation board that I can buy with a PowerPC in
> it?  I haven't seen any yet.
>
> Thanks,
> Jerry


Article: 44030
Subject: Information about FPGA
From: "Goteb" <goteb@katamail.com>
Date: Mon, 10 Jun 2002 15:28:09 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi! I'm searching documentation about FPGA in general (what they are,
what kind of them exist, ecc.). I have already found some informations
but they are too short.
Can you help me ?Tnx


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 44031
Subject: Re: Power supply caps on PCB
From: John_H <johnhandwork@mail.com>
Date: Mon, 10 Jun 2002 15:37:04 GMT
Links: << >>  << T >>  << A >>
Are you running 400 outputs at 24mA fast TTL?  16 outputs at 2mA LVCMOS?  The
output slew - translated into current draw during the risetime - is what
determines how much local decoupling demand you have on the Vcco.  If you have
fewer and slower outputs, the output slew could be less of a contribution than
the FPGA internals connected to that voltage, but the instantaneous current
needs are a good place to start.  So...  what's your slew, what's the load
capacitance you're driving, how many signals do you have?  You can figure out
the voltage fluctuations based on both capacitance and series resonance
frequency of the capacitors.

If you have limited board space and need the decoupling, there are more
expensive capacitor alternatives than the standard surface mount parts.
Suppliers such as AVX (Kyocera) have special caps that can get a bit pricey but
with good connections to the planes and good localization you can change the
"rule of thumb" and get the decoupling you need.

Without some form of simple analysis, stick to the rule of thumb.



Noddy wrote:

> Hi,
>
> I know that one should place 0.1uF and 0.01uF caps on all power supply pins
> on the FPGA... does this include both Vcco and Vccint, or can one get away
> with just Vccint and then put only 0.1uF on Vcco. I am seriously running out
> of room on my PCB, and increasing the PCB size is not an option!
>
> adrian


Article: 44032
Subject: Re: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
From: "Steve Casselman" <sc_no_spam@vcc.com>
Date: Mon, 10 Jun 2002 16:08:51 GMT
Links: << >>  << T >>  << A >>
The TRST is supposed to be asynchronous.  You might be able to use our
software but you'll need to write a little code.  Most of the Jtag software
tries to do everything for you and if it can't your out of luck. We try and
let you get between the bitstream and the board so if there is a problem at
least you have some kind of chance.

Steve

(Try HOTMan at www.vcc.com)


> This sounds similar to our problem with Texas DSPs. They need a few
> clock cycles on TCK while TRST is asserted, which is not compliant to
> the JTAG standard. In some rare cases after Power up it worked, but




Article: 44033
Subject: synthesis query: Xilinx + Synplify
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 10 Jun 2002 17:32:48 +0100
Links: << >>  << T >>  << A >>

Is there any way of re-wrting the following simple counter code so that
Synplify will merge the or'ed incrementer into the 1st LUT of the adder
chain ? Or am I going to have to instantiate everything ?

always @(posedge clk)
    if (reset)
        ra <= 0;
    else
        ra <= fra;

    wire [5:0] fra = ra + ((count_en[0] | count_en[1]) ? 1 : 0);




Article: 44034
Subject: ALTERA EPC16 Configuration in MAX+PLUS II V10.1
From: "SierraTech" <sierratk(NOSPAM)@sprynet.com>
Date: Mon, 10 Jun 2002 10:07:18 -0700
Links: << >>  << T >>  << A >>
I downloaded AN218 which shows how to configure EPC16 using Quartus II
"Convert Programming Files".

I am using MAX+PLUS II on a notebook (doesn't have the horsepower for
Quartus) version 10.12.  It states it supports EPC16 (which does show up in
device selection under programmer), but I cannot find how to configure the
EPC16 for various configuration modes of operation (i.e. Page mode where the
FLASH Pages can be programmed for 8 different ACEX 1K configurations).

How do you configure EPC16 from MAX+PLUS II V10.1?

Thanks!

--Bob



Article: 44035
Subject: Re: Information about FPGA
From: "Kate" <katie.mccall@btinternet.com>
Date: Mon, 10 Jun 2002 17:56:52 +0000 (UTC)
Links: << >>  << T >>  << A >>
FPGA = Field Programmable Gate Array = A chip that can be programmed and
then reprogrammed in the field.

Take a look at www.xilinx.com, www.cypress.com
and www.altera.com, these are the biggest suppliers of FPGA's.

Also try http://www.mrc.uidaho.edu/fpga/fpga.html

Hope this is of use.

:-)
"Goteb" <goteb@katamail.com> wrote in message
news:cf3a18f133b4974d82834e840f97a4a4.9826@mygate.mailgate.org...
> Hi! I'm searching documentation about FPGA in general (what they are,
> what kind of them exist, ecc.). I have already found some informations
> but they are too short.
> Can you help me ?Tnx
>
>
> --
> Posted via Mailgate.ORG Server - http://www.Mailgate.ORG



Article: 44036
Subject: programming xc3030 using atmel's ATDH2225 programmer cable
From: t.t.withaar@student.etc.etc (Thijs)
Date: Mon, 10 Jun 2002 18:11:05 GMT
Links: << >>  << T >>  << A >>
hi all,

I've could buy a cheap (used) xilinx XC3030A fpga,
now i'd like to make my own pcb for it,

Atmel has a pin-layout for a simple parallel programming cable,
and claims it works for xilinx devices 
http://www.atmel.com/atmel/acrobat/doc1417.pdf

does anyone have any experience with this?

if not, does anyone know another programming software which
works with an XC3030A and a home made programming cable ?

Greetz,

Thijs


Article: 44037
Subject: Re: synthesis query: Xilinx + Synplify
From: John_H <johnhandwork@mail.com>
Date: Mon, 10 Jun 2002 18:39:42 GMT
Links: << >>  << T >>  << A >>
I'm thinking the following will work:

always @(posedge clk)
  ra <= ( reset ? 0 : ra )
      + ( reset ? 0 : |count_en[1:0] );

I've done a bunch of sync reset and counter stuff.  I thrive on "clean"
synthesis.  I hope it works for you!



Rick Filipkiewicz wrote:

> Is there any way of re-wrting the following simple counter code so that
> Synplify will merge the or'ed incrementer into the 1st LUT of the adder
> chain ? Or am I going to have to instantiate everything ?
>
> always @(posedge clk)
>     if (reset)
>         ra <= 0;
>     else
>         ra <= fra;
>
>     wire [5:0] fra = ra + ((count_en[0] | count_en[1]) ? 1 : 0);


Article: 44038
Subject: Re: Problem with spartan2 vhdl code
From: "Benjamin Todd" <Benjamin.Todd@cern.ch>
Date: Mon, 10 Jun 2002 20:43:55 +0200
Links: << >>  << T >>  << A >>
that code looks a bit nasty, but if you consider the steps you have to take
to get a one clock pulse when you push a button then you'll see that it's
easier than you'd expect

first a couple of golden rules,
if you want a registered process try and stcik to the form:
process (clock, reset)
begin
if Reset = '1' then
--initialise your signals
elsif rising_edge (clock) then -- or indeed falling edge or even the 87
syntax
--do something
end if;
end process

To go back to the detect_edge matter; if you consider that the button gives
a logic one when it is pressed, then:

You can sample the button, you'll sample 0 all the time, until it is
pressed, then you will sample a 1.  To exploit this in VHDL, i'd recommend
starting with a registered process:

process (clock, reset)
begin
if Reset = '1' then
Current_Sample <= '0';
Old_Sample <= '0';
elsif rising_edge (clock) then
Current_Sample <= Button;
Old_Sample <= Current_Sample ;
end process

This is a small shift register, you put the first sample in current_sample.
And the next clock tick you make a new current_sample, and shift your old
value across into old_sample; so to get from here to a signal with a width
of one pulse when the button is pressed its a simple combinational result:
The btton is pressed when the old sample is zero and the current sample is
one.
i.e.

Pressed <= Current_Sample and not Old_Sample;

heres the tricky part... how do you remove the noise from a button that is
pressed? i.e. normally with a button you'd expect a lot of ones and zeros to
quickly appear as the switch contacts get closer!

Leave that one for you.

HTH.



--
Benjamin Todd
European Organisation for Partcile Physics
SL SPS/LHC -- Control -- Timing Division
CERN, Geneva, Switzerland,  CH-1211
Building 864 Room 1 - A24

The button will be pressed when the
"F. Modderkolk" <frankmotje@hotmail.com> wrote in message
news:82eb64d2.0206032335.39c179aa@posting.google.com...
> If I test the vhdl code with modelsim, it works just fine, but when I
> implement it, it doesn't do anything. The function of the code is to
> create a puls with a lenght of one clockpuls when I push a button
>
> the code:
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity startertwee is
>     Port ( puls : in std_logic;
>            pulsuit : out std_logic;
>            clk : in std_logic;
>            stopenreset : in std_logic);
> end startertwee;
>
> architecture Behavioral of startertwee is
> signal intern : std_logic;
> signal bpulsuit : std_logic;
>
> begin
> process (clk)
> begin
> if clk'event then
> if stopenreset = '1' then
>   pulsuit <= '0';
> intern <= '0';
> bpulsuit <= '0';
> else
> if clk  = '1' then
> if puls = '1' and intern = '0' then
> bpulsuit <= '1';
> intern <= '1';
> elsif puls = '0' and intern = '1' then
> intern <= '0';
> bpulsuit <= '0';
> else
> bpulsuit <= '0';
> intern <= intern;
> end if;
> end if;
>
> if clk = '0' then
> pulsuit <= bpulsuit;
> end if;
> end if;
> end if;
> end process;
> end Behavioral;
>
>
> Is there something I forget to program or something I do wrong?
> I hope you can help me
> thx



Article: 44039
Subject: Spartan II E -- BUFGDLL
From: "Jim Raynor" <chris_cheung66@hotmail.com>
Date: Mon, 10 Jun 2002 19:20:18 GMT
Links: << >>  << T >>  << A >>
hi,

    Is there any VHDL example on using the marco BUFGDLL?  I have download
the file xapp174.zip but it doesn't contain any example that explain on the
usage of BUFGDLL.  Also, does the macro BUFGDLL contains the properties like
STARTUP_WAIT, etc?

    Thanks

    Jim Raynor



Article: 44040
Subject: Re: programming xc3030 using atmel's ATDH2225 programmer cable
From: Ray Andraka <ray@andraka.com>
Date: Mon, 10 Jun 2002 19:25:15 GMT
Links: << >>  << T >>  << A >>
The 3030A is an antique, and is not supported with the current
tools.  The cost of the board and support for programming the part
is going to cost you much more than the part itself.  Very
seriously consider instead working with one of the current parts
such as the SpartanII.  There are a number of eval boards with
current parts available on the market for under $200 that are
compatible with the free development software available on the FPGA
vendor sites.

Thijs wrote:

> hi all,
>
> I've could buy a cheap (used) xilinx XC3030A fpga,
> now i'd like to make my own pcb for it,
>
> Atmel has a pin-layout for a simple parallel programming cable,
> and claims it works for xilinx devices
> http://www.atmel.com/atmel/acrobat/doc1417.pdf
>
> does anyone have any experience with this?
>
> if not, does anyone know another programming software which
> works with an XC3030A and a home made programming cable ?
>
> Greetz,
>
> Thijs

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44041
Subject: Re: where did my MHz go!
From: Davis Moore <davism@NOSPAMxilinx.com>
Date: Mon, 10 Jun 2002 14:08:10 -0600
Links: << >>  << T >>  << A >>
Ken,

The post-MAP timing report will always report a clock frequency greater
than the post-PAR timing report. This is because the post-MAP NCD
does not contain any routing delay information as the design has not yet
been placed or routed.

Ken Mac wrote:

[...SNIP...]

  Anyway, after mapping, the maximum clock frequency is reported to be
  138.947MHz.

  But, after place and route, the max clock freq. is reported to be 91.166MHz.

  Where could I be losing so much MHz?  Can my choice of LOCs in the UCF
  affect the max clock freq.?

[...SNIP...]

--
Davis Moore
Software Engineer - Logical Implementation Tools
davis.moore@NOSPAMxilinx.com




Article: 44042
Subject: Re: synthesis query: Xilinx + Synplify
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 10 Jun 2002 21:14:58 +0100
Links: << >>  << T >>  << A >>


John_H wrote:

> I'm thinking the following will work:
>
> always @(posedge clk)
>   ra <= ( reset ? 0 : ra )
>       + ( reset ? 0 : |count_en[1:0] );
>
> I've done a bunch of sync reset and counter stuff.  I thrive on "clean"
> synthesis.  I hope it works for you!

I could certainly try that for a "standard" counter but, unfortunately, in
this case I need the output of the combinatorial add+1 - its the read pointer
to a FIFO made from 16x1 ``DP'' RAMs - and I want the next read value to come
out at the point I hit the FIFO with the read signal, removing a clock
cycle's worth of latency.

What I'm actually trying to do is remove the routing delay between the
|count[1:0] LUT and the CIN of the counter bit 0. I can do some soft macro
stuff with xc_map, xc_uset, xc_rloc synth directives to put the LUT near the
adder but even this doesn't get the delay small enough.


Article: 44043
Subject: Re: synthesis query: Xilinx + Synplify
From: John_H <johnhandwork@mail.com>
Date: Mon, 10 Jun 2002 20:32:50 GMT
Links: << >>  << T >>  << A >>
Okay, so Synplify is getting edgy about forcing the .CI input...
I actually synthesized my suggestion and saw your troubles.
So.  Assuming the LUT1_2 elements are all where they're really needed
(sometimes they aren't), the following code synthesizes great:

module counters ( clk, reset, count_en, ra );

input        clk, reset;
input  [1:0] count_en;
output [5:0] ra;

wire [5:0] fra;
reg  [5:0] ra;

always @(posedge clk)
  if( reset )  ra <= 0;
  else         ra <= fra;

assign fra = {ra[5:1],|count_en} + ra[0];

endmodule

You can probably skip the wire and do the addition inline.  I just
convinced the synthesizer to do the carry-in differently by swapping the
LSbits.  Not pretty but it works.  The synthesis SHOULD push everything
into the bottom LUT without a carry-in.  At least this way is "better."



Rick Filipkiewicz wrote:

> Is there any way of re-wrting the following simple counter code so that
> Synplify will merge the or'ed incrementer into the 1st LUT of the adder
> chain ? Or am I going to have to instantiate everything ?
>
> always @(posedge clk)
>     if (reset)
>         ra <= 0;
>     else
>         ra <= fra;
>
>     wire [5:0] fra = ra + ((count_en[0] | count_en[1]) ? 1 : 0);


Article: 44044
Subject: BUFGDLL again
From: "Jim Raynor" <chris_cheung66@hotmail.com>
Date: Mon, 10 Jun 2002 23:03:33 GMT
Links: << >>  << T >>  << A >>
hi,

Could anyone explain what is the usage of BUFGDLL? If I have an input clock,
let's say CLKIN, connects to the input of IBUFG, would the output of that
IBUFG takes advantage of the dedicated global clock routing resources of the
device? If it does, what is the point of using BUFGDLL?



Jim




Article: 44045
Subject: Re: BUFGDLL again
From: Ray Andraka <ray@andraka.com>
Date: Mon, 10 Jun 2002 23:36:40 GMT
Links: << >>  << T >>  << A >>
It eliminates the skew between the internal clock net and the external clock,
and by doing so improves the timing of the I/O relative to the clock.

Jim Raynor wrote:

> hi,
>
> Could anyone explain what is the usage of BUFGDLL? If I have an input clock,
> let's say CLKIN, connects to the input of IBUFG, would the output of that
> IBUFG takes advantage of the dedicated global clock routing resources of the
> device? If it does, what is the point of using BUFGDLL?
>
> Jim

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44046
Subject: Re: Information about FPGA
From: alw@al-williams.com (Al Williams)
Date: 10 Jun 2002 18:24:26 -0700
Links: << >>  << T >>  << A >>
> > Hi! I'm searching documentation about FPGA in general (what they are,
> > what kind of them exist, ecc.). I have already found some informations
> > but they are too short.

You might enjoy our tutorials on Xilinx and Altera programmable logic.
Technically, they are on CPLDs, but you'll find a lot of the same info
applies since the tools you (usually) use are identical.

Have a look at http://www.al-williams.com/pictutor

Good luck!

Al Williams
AWC

Article: 44047
Subject: Re: where did my MHz go!
From: "XU QIJUN" <qijun677@oki.com>
Date: Tue, 11 Jun 2002 13:18:04 +0800
Links: << >>  << T >>  << A >>
Actually I have a problem here.
You mentioned that a high fanout net will affect timing, but how can I
constrain this
net so that it's end up with buffered properly? In my VHDL code I can decide
a high
fanout wire, but I feel don't know how to deal with it.


"Ray Andraka" <ray@andraka.com> wrote in message
news:3D04B098.CEE1727D@andraka.com...
> Choice of LOCs in the UCF can Absolutely affect the timing, and to an
amazingly
> large degree.  Run the timing analyzer or TRCE and set it to report on
paths
> failing timing constraints.  That will tell you what paths you have a
problem
> with.  Could be poor placement, too many levels of logic, or a high fanout
> killing you.  Until you read the timing report, you have no idea of the
> magnitude of the problem or where to start tweaking to fix it.
>
>
> Ken Mac wrote:
>
> >
> > Anyway, after mapping, the maximum clock frequency is reported to be
> > 138.947MHz.
> >
> > But, after place and route, the max clock freq. is reported to be
91.166MHz.
> >
> > Where could I be losing so much MHz?  Can my choice of LOCs in the UCF
> > affect the max clock freq.?
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 44048
Subject: Re: Information about FPGA
From: "Felix Bertram" <f.bertram@trenz-electronic.de>
Date: Tue, 11 Jun 2002 07:56:04 +0200
Links: << >>  << T >>  << A >>
> Hi! I'm searching documentation about FPGA in general (what they are,
> what kind of them exist, ecc.). I have already found some informations
> but they are too short.

we have a tutorial on FPGAs in general here:
http://www.trenz-electronic.de/down/tc-XC2S-SoC-1.pdf

and another one on tools here:
http://www.trenz-electronic.de/down/tc-XC2S-SoC-2.pdf

hope this helps,
best regards

Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic GmbH
Brendel 20
D - 32257 Buende
Tel.: +49 (0) 5223 4939755
Fax.: +49 (0) 5223 48945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de




Article: 44049
Subject: Re: programming xc3030 using atmel's ATDH2225 programmer cable
From: t.t.withaar@student.etc.etc (Thijs)
Date: Tue, 11 Jun 2002 07:22:41 GMT
Links: << >>  << T >>  << A >>
>The 3030A is an antique, and is not supported with the current
>tools.  The cost of the board and support for programming the part
>is going to cost you much more than the part itself.  Very
>seriously consider instead working with one of the current parts
>such as the SpartanII.  There are a number of eval boards with
>current parts available on the market for under $200 that are
>compatible with the free development software available on the FPGA
>vendor sites.

thanks, but i could get this 3030 for about $4, it's just for
a hobby project, so buying a board for $100 or more is way
out of my budget.





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