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"James Wang" <minfordtec@aol.com> schrieb im Newsbeitrag news:9ed66736.0210262210.79cabbfb@posting.google.com... > Hi Friends, > > We are making a FPGA demo board which is suitable for prototype > development and FPGA study. It has an Altera Flex10K devices > EPF10K10LC84, feature ICs(24LC64, LM75, 50MHz oscillator), RS232 port, ^^^^^^^^^^^^^^^^^^^^ Correct me If Iam wrong, but isnt this device a little bit out of date? IMHO there are many much better offers regarding FPGA demoboards out there. Just my 2 cent. -- MfG FalkArticle: 48926
"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag news:apg89j$11ll8$1@ID-84877.news.dfncis.de... > > We are making a FPGA demo board which is suitable for prototype > > development and FPGA study. It has an Altera Flex10K devices > > EPF10K10LC84, feature ICs(24LC64, LM75, 50MHz oscillator), RS232 port, > ^^^^^^^^^^^^^^^^^^^^ > > Correct me If Iam wrong, but isnt this device a little bit out of date? IMHO > there are many much better offers regarding FPGA demoboards out there. > Just my 2 cent. ??????? Hello?????? 199 US dollar for a ******* 10K gates FPGA plus some gimick? You better learn how to do business, or search for other fools. -- MfG FalkArticle: 48927
> ... > > Do you think this leaves enough room? In theory, the shannon theorem says > > that sampling at twice the maximum frequency is sufficcient to reconstruct > a > > signal... > > <nitpick on> > I thought that was the Nyquist critereon. > <nitpick off> > Try to post it to comp.dsp newsgroup... :-))) Jan PS: Nyquist criterion is about stability of a systemArticle: 48928
Steve Knapp wrote > The Power On Surge current associated with some Xilinx devices all boils > down to something relatively easy to accomplish in most applications. > However, I agree that the terse data sheet specification, without any > background information, creates a number of unanswered questions. <snip> Just wondering - what is the general approach for avoiding this effect in the design of recent FPGAs such as VirtexII? And do commodity SRAMs have the same problem?Article: 48929
Hallo,
after weeding out some long pathes on a XC2S200-5 design with about 700
loads on the "fpgaclk" BUFG net, in the synthesis report the following report
appeared. The delay reported for the clock distribution seems quite
high. How do I have to interpret this data?
Timing constraint: Default OFFSET IN BEFORE for Clock 'fpgaclk'
Offset: 8.982ns (Levels of Logic = 1)
Source: fpgaclk
Destination: m1_b7
Destination Clock: fpgaclk rising
Data Path: fpgaclk to m1_b7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
BUFGP:I->O 718 0.782 8.200 fpgaclk_BUFGP (fpgaclk_BUFGP)
RAMB4_S16_S16:CLKA 0.000 m1_b7
----------------------------------------
Total 8.982ns (0.782ns logic, 8.200ns route)
(8.7% logic, 91.3% route)
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 48930"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:apgl56$him$1@news.tu-darmstadt.de... > Hallo, > > after weeding out some long pathes on a XC2S200-5 design with about 700 > loads on the "fpgaclk" BUFG net, in the synthesis report the following report > appeared. The delay reported for the clock distribution seems quite > high. How do I have to interpret this data? Hello Uwe, nice to meet you here too ;-) > Timing constraint: Default OFFSET IN BEFORE for Clock 'fpgaclk' > Offset: 8.982ns (Levels of Logic = 1) > Source: fpgaclk > Destination: m1_b7 > Destination Clock: fpgaclk rising > > Data Path: fpgaclk to m1_b7 > Gate Net > Cell:in->out fanout Delay Delay Logical Name (Net Name) > ---------------------------------------- ------------ > BUFGP:I->O 718 0.782 8.200 fpgaclk_BUFGP (fpgaclk_BUFGP) > RAMB4_S16_S16:CLKA 0.000 m1_b7 > ---------------------------------------- > Total 8.982ns (0.782ns logic, 8.200ns route) > (8.7% logic, 91.3% route) This is just the synthesis report, means the actual speed in the device will be somewhat slower, since it doesnt take into account for the real placement & routing (since after synthesis, Place & Route havnt been happen yet). But whats a little bit curious about this report, is looks like that a clock signal (fpgaclk) is handled like a data signal?? Odd. Have you made some "special" clock connections/usage in your design? Usually, a clock only feeds clock inputs of the design. -- MfG FalkArticle: 48931
"Jan Pech" <j.pech@noSPAMieee.org> wrote in message news:apg8vc$vjd$1@ns.felk.cvut.cz... > > ... > > > Do you think this leaves enough room? In theory, the shannon theorem > says > > > that sampling at twice the maximum frequency is sufficcient to > reconstruct > > a > > > signal... > > > > <nitpick on> > > I thought that was the Nyquist critereon. > > <nitpick off> > > > > Try to post it to comp.dsp newsgroup... :-))) > Jan > > PS: Nyquist criterion is about stability of a system Er, huh? What do you think the Nyquist theory is?Article: 48932
Hello group:
I'll try to keep this short. I have a simple asynchronous Verilog
module that takes 3 inputs to produce a few simple outputs.
Behavorially, the module works fine. I pumped the design through
WebPACK and targeted an FPGA as well as a CPLD. Behavorially, the
post-PAR and post-fit models simulate and match the behavorial model
(now with various delays, of course). To switch back and forth between
FPGA <> CPLD I simply changed the "properties" of the project, and
re-synthesized, etc. The verilog code for the module being implemented
as well as the testbench were the same for both the FPGA and CPLD
cases. I let the Xilinx IDE handle all the background stuff for the
ModelSim simulations of the post-PAR, post-Fit models.
So, I then made the design synchronous - added a clock as well as a
reset and made small modifications to the testbench - and repeated the
exercise above. The FPGA implementation works fine, with the behavorial
functionality matching the post-PAR (and post-map, post-translate, etc.)
functionality, now with delays of course. However, the post-fit CPLD
implementation does not work functionally at all! Again, I am using the
same testbench and verilog code for the two synchronous
implementations. It seems the post-Fit CPLD design is "stuck." The
outputs are correct for the first set of inputs passed to it from the
testbench, but after this they never change, as if time is not passing.
But the same exact code works for the FPGA! I'm new to this area, but
it doesn't seem to make sense. Do I need to do something special for
the clock or reset in the post-Fit code for the CPLD that is transparent
for the FPGA? I expected the CPLD implementation to be easier and less
complicated.
Thanks for any insight to this very interesting issue.
- BT
Article: 48933Bill, Did you install the ModelSim library updates? The ones that come in a zip file so there's no way to back them out? If so, that's your problem. I had to re-install ModelSim to get rid of them to fix the same problem. Dig into the waveform of the post-fit cpld, and you will see way too many X's on the signals. SH7 On Sun, 27 Oct 2002 15:07:59 GMT, Bill Turnip <BTurnip@wellspring.org> wrote: >Hello group: > I'll try to keep this short. I have a simple asynchronous Verilog >module that takes 3 inputs to produce a few simple outputs. >Behavorially, the module works fine. I pumped the design through >WebPACK and targeted an FPGA as well as a CPLD. Behavorially, the >post-PAR and post-fit models simulate and match the behavorial model >(now with various delays, of course). To switch back and forth between >FPGA <> CPLD I simply changed the "properties" of the project, and >re-synthesized, etc. The verilog code for the module being implemented >as well as the testbench were the same for both the FPGA and CPLD >cases. I let the Xilinx IDE handle all the background stuff for the >ModelSim simulations of the post-PAR, post-Fit models. > So, I then made the design synchronous - added a clock as well as a >reset and made small modifications to the testbench - and repeated the >exercise above. The FPGA implementation works fine, with the behavorial >functionality matching the post-PAR (and post-map, post-translate, etc.) >functionality, now with delays of course. However, the post-fit CPLD >implementation does not work functionally at all! Again, I am using the >same testbench and verilog code for the two synchronous >implementations. It seems the post-Fit CPLD design is "stuck." The >outputs are correct for the first set of inputs passed to it from the >testbench, but after this they never change, as if time is not passing. >But the same exact code works for the FPGA! I'm new to this area, but >it doesn't seem to make sense. Do I need to do something special for >the clock or reset in the post-Fit code for the CPLD that is transparent >for the FPGA? I expected the CPLD implementation to be easier and less >complicated. > Thanks for any insight to this very interesting issue. >- BTArticle: 48934
Falk Brunner <Falk.Brunner@gmx.de> wrote: : This is just the synthesis report, means the actual speed in the device will : be somewhat slower, since it doesnt take into account for the real placement : & routing (since after synthesis, Place & Route havnt been happen yet). But : whats a little bit curious about this report, is looks like that a clock : signal (fpgaclk) is handled like a data signal?? Odd. Have you made some : "special" clock connections/usage in your design? Usually, a clock only : feeds clock inputs of the design. I've checked that I didn't use the clock on any other logic input beside the clock inputs. With another clock I made that error, and XST reported about it. And 8 ns delay for a global clock network seems insane. The post layout seems to indicate other. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 48935
I created a macro following the directions given in Xilinx Answer Record number: 10901. It has a single Virtex-2 slice. I was trying to instantiate this macro into the top level design. When ngdbuild tries to load the macro from the file I get an error (FATAL_ERROR:Ncd:basncmacrodef.c:1466:1.19.2.1 - Mangled nmc file start property read <0xffffcacc>). Can anyone let me know why this error occurs. Thanks -KiranArticle: 48936
Take a look at some one else's synthesizable code before you go to far down the "#1" path. In general, you'll use a single # in your design, just for clock generation, and everything else will key off your clock. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:<r9ku9.1270$8o1.241669@news.xtra.co.nz>... > I have been learning a little verilog. With the idea to play with my own > CPU. > > It seems that one can build multi step processes that run by using a process > time > > eg > always > begin > #1; > do register transfer > #1; > do some other transfer > #1 > do something else > end > > This loops around and around doing that. How do you specify which clock it > should be using to do this? Is this a normal way to do things, or is a state > machine more normal > > eg > > always @(posedge clk) > begin > switch ( state_reg) > //Do something depending on the state > end > endArticle: 48937
> > > > PS: Nyquist criterion is about stability of a system > > Er, huh? What do you think the Nyquist theory is? > Well... I used to learn about Nyquist theory you mean like about Shannon theorem. Nyquist criterion was the criteria how to determine whether will be linear continuous system stable or not. I took a look into some English-written literature and I found, that the stability criterion is called "Nyquist Stability Criterion" while the theory about sampling of continuous signal is called simply "Nyquist Criterion" (I knew it under the name Shannon theorem only). I'm sorry for misunderstanding. JanArticle: 48938
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:aph8os$ors$1@news.tu-darmstadt.de... > I've checked that I didn't use the clock on any other logic input beside the > clock inputs. With another clock I made that error, and XST reported about > it. > And 8 ns delay for a global clock network seems insane. The post layout > seems to indicate other. Yes. Seems like a bug in XST. :-( -- MfG FalkArticle: 48939
Article: 48940
Article: 48941
Article: 48942
I have a PCI model for verilog simulators which includes:
arbiter
master(s)
slave(s)
monitor with GUI
It is designed to interface with PCI designs to exercise them and display
activity and protocol errors.
You can download this for free at http://www.nelsim.com
Also included is a tool called ScriptSim which permits rapid development
of simulation models using perl or python.
As open source software, I hope the community will participate by
submitting bug reports, comments, and source code enhancements.
Requirements: Unix/Linux/Solaris system with gcc compiler
Verilog simulator with PLI interface
Dave Nelson
Article: 48943
Symon wrote:
> Dear All,
> At last an answer to these interminable threads about which is
> better! Just go to www.googlefight.com !
>
> VHDL v. Verilog, winner is VHDL.
> Xilinx v. Altera, winner is Altera.
> Synchronous v. Asynchronous, winner is Asynchronous.
> Hardware v. Software, winner is software.
>
> It's foolproof!?
>
> cheers, Syms.
Well Syms,
According to the stats, Lattice are at least 2x as good as Xilinx or
Altera...
I know it's true...especially the SERDES...
Check out www.latticesemi.com
Lots of Love
Your old Colleague
Mark Smith
PS Sorry to hear about the Plymouth Site..
Article: 48944
Uwe Bonnes wrote:
>
>
> I've checked that I didn't use the clock on any other logic input beside the
> clock inputs. With another clock I made that error, and XST reported about
> it.
> And 8 ns delay for a global clock network seems insane. The post layout
> seems to indicate other.
>
> Bye
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Yes, 8 ns for the global clock distribution delay sounds way too
much.
If everything is done correctly, you shouldn't get anything more than 3
ns.
Uwe, is the clock signal coming in using IBUFG and GCLKBUF?
If not, that might explain the delay.
To make sure, check the EDIF netlist generated by XST.
In case you don't know how to do it, do a search of this newsgroup at
Google about how to get XST to generate an EDIF netlist.
Also, I have never used it, but I believe there is an XST synthesis
option called "isclock" or something like it that tells the synthesis
tool that an input pin should be connected to a dedicated clock input
pin.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 48945A few mouth ago ,I've estimated the Fmax of a nomal design on Xilinx or Altera chip . The result said Xilinx is a little fast Than Altear . Tsu ( ns ) Tco ( ns ) Tlut ( ns ) Fmax Spartent II -5 0.7 1.3 0.7 96 M Virtex E -6 0.63 1.0 0.47 137M Virtex II -4 0.37 0.57 0.44 160M Virtex II Pro -50.29 0.40 0.37 193M APEX E -3 # 0.23 0.32 1.01 79M APEX II -9## 0.33 0.23 0.7 112M Stratix -7 0.011 0.202 0.527 153M "Brian Guralnick" <innerdimension@videotron.ca> wrote in message news:<L3yt9.23302$Td.417972@wagner.videotron.net>... > However, for the 400Kbit internal ram, the Altera Stratix is probably the best & fastest solution. To get anything else cost worthy > with over 400Kbit, you will need to connect to ZBTRam. > > ____________ > Brian Guralnick > innerdimension@hotmail.com > (514) 624-4003 > > > "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0210230245.3e5080db@posting.google.com... > > Thanks, > > > > The Altera Stratix does look quite good. I was possibly being a bit > > ambitious with my original spec as Xilinx only claim 800Mbps outputs > > when using their own fixed netlist cores. As long as it can run at > > 311MHz, 622Mbps Output Data Rate then that should be fine. > > > > Cost is not really an issue (as far as i know), i am under the > > impression that these FPGAs cost upto a few thousand dollars??, we are > > looking for the highest spec FPGA that best suits our requirements > > (High Speed Data comms with strict jitter tolerances). It is going to > > be used for simulating an ASIC without the time and money involved in > > immediately producing a test chip (around $1million!). > > > > MattArticle: 48946
In article <2ccc49b.0210272152.4a6e4206@posting.google.com>, Zhou Chang <zhouchang2001cn@yahoo.com.cn> wrote: >A few mouth ago ,I've estimated the Fmax of a nomal design on Xilinx or Altera >chip . The result said Xilinx is a little fast Than Altear . > > Tsu ( ns ) Tco ( ns ) Tlut ( ns ) Fmax >Spartent II -5 0.7 1.3 0.7 96 M What do you define as "normal". EG, AES is perfectly runable, 5 separate excution streams, at 115 MHz on a Spartan II. >Virtex E -6 0.63 1.0 0.47 137M >Virtex II -4 0.37 0.57 0.44 160M >Virtex II Pro -50.29 0.40 0.37 193M >APEX E -3 # 0.23 0.32 1.01 79M >APEX II -9## 0.33 0.23 0.7 112M >Stratix -7 0.011 0.202 0.527 153M > > > > > >"Brian Guralnick" <innerdimension@videotron.ca> wrote in message >news:<L3yt9.23302$Td.417972@wagner.videotron.net>... >> However, for the 400Kbit internal ram, the Altera Stratix is probably >the best & fastest solution. To get anything else cost worthy >> with over 400Kbit, you will need to connect to ZBTRam. >> >> ____________ >> Brian Guralnick >> innerdimension@hotmail.com >> (514) 624-4003 >> >> >> "M Pedley" <Pedley@talk21.com> wrote in message >news:b34821cd.0210230245.3e5080db@posting.google.com... >> > Thanks, >> > >> > The Altera Stratix does look quite good. I was possibly being a bit >> > ambitious with my original spec as Xilinx only claim 800Mbps outputs >> > when using their own fixed netlist cores. As long as it can run at >> > 311MHz, 622Mbps Output Data Rate then that should be fine. >> > >> > Cost is not really an issue (as far as i know), i am under the >> > impression that these FPGAs cost upto a few thousand dollars??, we are >> > looking for the highest spec FPGA that best suits our requirements >> > (High Speed Data comms with strict jitter tolerances). It is going to >> > be used for simulating an ASIC without the time and money involved in >> > immediately producing a test chip (around $1million!). >> > >> > Matt -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48947
yusuke wrote: > [9572xl cpld ...] when i write the signal i want, my cpld holds it > for a while at the bus and then the chip at the bus overwrite mine. > And xilinx enters on a "strange behavior" like missing clock rising edges. I observed the same "strange" behaviour when both the cpld-output and another source were driving the same bus-line simultaneously for few nanoseconds. The same happened, when two cpld-outputs were shortened together (by accident, bad soldering). The "strange behaviour" did also affect other macrocells, which were not involved in the output-driver overload. I never really found out why. > Does anyone has an advice/tip to help me? I worked around as follows: 1. Consider the timing very carefully and make sure that there is not a single nanosecond overlap between the cpld driving the bus and another component driving the bus. 2. When (1) is not feasible, use external bus drivers. Then the cpld does not "see" the bus-collision and will not mess up. HTH and best regards; Ralf.Article: 48948
Hi, I am an intermediate with Xilinx softwares like ISE 4.2 and ISE Webpack. I did a few designs also. I want to know whether it will take a lot of learning to get used to Altera softwares? Will it be like a computer amateur to switch from Macintosh to Windows?Article: 48949
Besides that, does Altera offer any free software like Xilinx's WebPack? I heard that Altera FPGA chips and demo boards are cheaper than it's competitors, is it so? Friends may come and go, but enemies accumulate. "Soul in Seoul" <Far@East.Design> wrote in message news:3dbced5e@news.starhub.net.sg... > Hi, > > I am an intermediate with Xilinx softwares like ISE 4.2 and ISE Webpack. I > did a few designs also. > I want to know whether it will take a lot of learning to get used to Altera > softwares? > > Will it be like a computer amateur to switch from Macintosh to Windows? > > > >
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Compare FPGA features and resources
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