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On Dec 3, 3:01=A0pm, Vikram <vkr...@gmail.com> wrote: > Announcing a Seminar on A New Approach - An FPGA and PCB System > Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10 > > #2 FPGA Design & Instant Prototyping > Learn how to design complex FPGA's with an embedded processor utlizing > block based IP and quickly debug your design in a NanoBoard with > virtual instrumentation. FPGA design using a PCB layout tool is a recipe for disaster. -aArticle: 144401
Hi, Is anyone aware of a design controlling the 'I2C_controller_core' from www.opencores.org? I read very good review of this core, but it needs to be controlled by either a state machine or a small processor. The current core only works at the 'byte' level. I'd like to be able to tell it: write those 37 bytes to that slave address...or read 48 bytes from that slave address... I thought I'd ask before starting to write the state machine! Thanks, Diego --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144402
On Dec 4, 2:09=A0am, Andy Peters <goo...@latke.net> wrote: > On Dec 3, 3:01=A0pm, Vikram <vkr...@gmail.com> wrote: > > > Announcing a Seminar on A New Approach - An FPGA and PCB System > > Development Platform, Santa Clara, CA, USA (By Altium) - Dec'10 > > > #2 FPGA Design & Instant Prototyping > > Learn how to design complex FPGA's with an embedded processor utlizing > > block based IP and quickly debug your design in a NanoBoard with > > virtual instrumentation. > > FPGA design using a PCB layout tool is a recipe for disaster. > > -a Altium Designer is NOT a PCB layotool. AnttiArticle: 144403
Oscar Almer wrote: > The FIFO macros basically, it seems to me, wraps a BRAM macro, which is > dual-port for free and gratis. The cost you refer to has already been > paid by the poor engineers at Xilinx who designed the BRAM. > > So, go ahead and save yourself the design effort, it won't really make > a difference anyway. In my opinion the FIFO macros that use the BRAM is the worst thing Xilinx could have done. Their core designers love to sprinkle them all around coregen cores, and the cores waste huge amounts of ram. Even small hundred bit fifos are built from one block ram etc. Without the macro the designers might have to think about what they are trying to do, and maybe optimize something in terms of size. Of course business wise it is a good decision because the customers need bigger chips to achieve things that could be much smaller. --KimArticle: 144404
As a beginner in FPGA design I run to the following problem:
I want to generate a 200MHz clock by the DCM from 2 different
clock sources, one is a 10MHz clock, the other is 60MHz.
My idea was to divide the 60MHz by 6 and alternatively
switch between the both clock-signals.
I use the Xilinx ISE9.1 and a Spartan3.
The synthesis (XST) was ok, but the Translate process shows
this error:
ERROR:NgdBuild:455 - logical net 'clk10mhz' has multiple driver(s):
pin O on block clk10mhz1 with type LUT3,
pin PAD on block clk10mhz with type PAD
ERROR:NgdBuild:924 - input pad net 'clk10mhz' is driving non-buffer
primitives:
pin O on block clk10mhz1 with type LUT3
When I put the selected clock to an output and read it from
another input and put it direct to the DCM then my design
works very well.
What is my fault?
Mathias
Article: 144405> FPGA design using a PCB layout tool is a recipe for disaster. Indeed, I think they're wasting their time down this path. What is good is the ability to pin/netlist swap when routing and pass that back to the FPGA constraints. They should concentrate on this and making it as flexible as possible but forget the FPGA development side of things. Nial.Article: 144406
On Dec 4, 5:30=A0am, Mathias Weierganz <mwe...@expires-31-12-2009.news- group.org> wrote: > As a beginner in FPGA design I run to the following problem: > I want to generate a 200MHz clock by the DCM from 2 different > clock sources, one is a 10MHz clock, the other is 60MHz. > My idea was to divide the 60MHz by 6 and alternatively > switch between the both clock-signals. > > I use the Xilinx ISE9.1 and a Spartan3. > The synthesis (XST) was ok, but the Translate process shows > this error: > > ERROR:NgdBuild:455 - logical net 'clk10mhz' has multiple driver(s): > =A0 =A0 pin O on block clk10mhz1 with type LUT3, > =A0 =A0 pin PAD on block clk10mhz with type PAD > ERROR:NgdBuild:924 - input pad net 'clk10mhz' is driving non-buffer > primitives: > =A0 =A0 pin O on block clk10mhz1 with type LUT3 > > When I put the selected clock to an output and read it from > another input and put it direct to the DCM then my design > works very well. > > What is my fault? > > Mathias Did you use the architecture wizard (or CoreGen) to "create" your DCM? This method has a habit of adding the input pin buffer, which you obviously don't want if the input to the DCM comes from an internal signal. Regards, GaborArticle: 144407
Hi everyone, I've been playing with fpga since a couple of time and I can't find the answer to my quesiton. I have a picoblaze in a design of mine and I want to update the bitstream without having to re-"build" my design entirly ( to save time ). I'm using linux and thus the tool given with the picoblaze can't work. I found out picoasm ( http://www.xs4all.nl/~marksix/picoasm.html ) + this page ( http://www.labbookpages.co.uk/fpgas/picoBlaze.html ) witch give all the info I should need but I have a problem. How can I locate the blockram witch the placer has placed my program. The script that the site give use this command : xdl -ncd2xdl vga.ncd This output a vga.xdl file witch should contain my Block ram and it's position but it is nowhere to be found. I'm using Xilinx 10.1... Do anyone has an idea ? Thanks a lot for your input, paxl13Article: 144408
The CS484 package is nice but I believe it is some time off before it is available for Spartan-6. For layout plan for an entire rerouting of the design. John Adair Enterpoint Ltd.- Home of Merrick1 the High Performance Computing Board. On 3 Dec, 21:23, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > Hi, > Just got a question what to do if future needs fill up a Spartan-3A > DSP 3400 CS484. A very quick and unqualified look at Spartan-6 family > show a package called CSG484 with same physical dimensions as the > CS484. Hope to do as few changes on the PCB as possible. Since the > supply voltage is not the same, a drop-in replacement will not be > possible anyway, but I would like to keep the rewiring need low. > Anybody done this or thought of this who would share some impressions? > > -- > SvennArticle: 144409
hello there for a measuring utility (running @ 100MHZ) I need a counter of 42-bit width whose value is used by several sub blocks of my design. As a first, somehow dirty solution I have implemented this like follows. Since this approach needs quite a huge amount of FFs and leads to long delaytimes (bit 0 to 42) I am looking for an alternative. I was thinking about using Block RAM (Spartan3) to reduce routing effort and delaytimes. (see also http://courses.ece.illinois.edu/ece412/References/datasheets/xapp463.pdf) Has anyone ever done such a thing or do you have any suggestions on solving my task? current code: ------------------------------------- # i have to use std_logic_unsigned since numeric_std has as integer width the normal 4 bytes width (32bit - which for 42 bits is not enough ... overflow,..) # ... GENERIC ( t : NATURAL := 42; --! counter width wd: NATURAL := 5 --! divider (clk/(2*wd)) ); # ... ARCHITECTURE rtl OF worldtimeCtr IS SIGNAL cnt: std_logic_vector(t-1 downto 0); BEGIN PROCESS(clk,rst) VARIABLE temp : NATURAL RANGE 0 to wd; BEGIN IF(rst='0')THEN cnt <= (others =>'0'); temp := 0; ELSIF(clk'event and clk='1')THEN IF(en='1' and temp = wd)THEN temp := 0; cnt <= STD_LOGIC_VECTOR(cnt + 1); END IF; temp := temp+1; END if; END process; o_worldtime <= cnt; END rtl; # ... ------------------------------------- thank you in advance kendorArticle: 144410
hello, can anyone tell me whats the minimum clock resolution in fpga, i mean whether fpga works in nano second or in micro seconds if an external clock of 100 Mhz is provided? thanksArticle: 144411
I feel ugly !, When you try to update a block ram, always assure yourself THAT Xilinx didn't have removed it from the design !!! Sorry for this, paxl On Dec 4, 11:31=A0am, paxl13 <pax...@gmail.com> wrote: > Hi everyone, > > I've been playing with fpga since a couple of time and I can't find > the answer to my quesiton. I have > a picoblaze in a design of mine and I want to update the bitstream > without having to re-"build" my design > entirly ( to save time ). I'm using linux and thus the tool given with > the picoblaze can't work. I found out > picoasm (http://www.xs4all.nl/~marksix/picoasm.html) + this page > (http://www.labbookpages.co.uk/fpgas/picoBlaze.html) witch give all > the info I should need but I have a problem. How can I locate the > blockram > witch the placer has placed my program. The script that the site give > use this command : > xdl -ncd2xdl vga.ncd > This output a vga.xdl file witch should contain my Block ram and it's > position but it is nowhere to be found. > I'm using Xilinx 10.1... > > Do anyone has an idea ? > Thanks a lot for your input, > paxl13Article: 144412
On Fri, 04 Dec 2009 12:15:24 -0600 "kendor" <jonas.reber@bfh.ch> wrote: > hello there > > for a measuring utility (running @ 100MHZ) I need a counter of 42-bit > width whose value is used by several sub blocks of my design. As a > first, somehow dirty solution I have implemented this like follows. > Since this approach needs quite a huge amount of FFs and leads to > long delaytimes (bit 0 to 42) I am looking for an alternative. I was > thinking about using Block RAM (Spartan3) to reduce routing effort > and delaytimes. (see also > http://courses.ece.illinois.edu/ece412/References/datasheets/xapp463.pdf) > > Has anyone ever done such a thing or do you have any suggestions on > solving my task? > > current code: > ------------------------------------- > # i have to use std_logic_unsigned since numeric_std has as integer > width the normal 4 bytes width (32bit - which for 42 bits is not > enough ... overflow,..) > > # ... > GENERIC ( > t : NATURAL := 42; --! counter width > wd: NATURAL := 5 --! divider (clk/(2*wd)) > ); > > # ... > ARCHITECTURE rtl OF worldtimeCtr IS > SIGNAL cnt: std_logic_vector(t-1 downto 0); > BEGIN > PROCESS(clk,rst) > VARIABLE temp : NATURAL RANGE 0 to wd; > BEGIN > IF(rst='0')THEN > cnt <= (others =>'0'); > temp := 0; > ELSIF(clk'event and clk='1')THEN > IF(en='1' and temp = wd)THEN > temp := 0; > cnt <= STD_LOGIC_VECTOR(cnt + 1); > END IF; > temp := temp+1; > END if; > > END process; > o_worldtime <= cnt; > END rtl; > > # ... > ------------------------------------- > > thank you in advance > > kendor > > Another option would be to pipeline the block into, say, 3 segments of 14 bits a piece, so that you don't have that one LONG carry chain trying to propagate up the whole thing. Depending on how willing your toolchain is to rebalance registers (ISE 11 _may_ be smart enough), you might just be able to add a few stages of pipeline delay on the output of the entire 43 bits, and let it push things around across the logic. Otherwise you'd have to code it manually, which isn't the end of the world. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 144413
n, The Xilinx FPGA device is entirely static, and synchronous. That means that when a clock transitions, that the flip flops all store information on the rising (or falling) edge of the clock. The delay from the clock edge, to the data output of the flip flop changing is in the timing report, and is usually known as "clock to out." This delay is also in the 100's of picoseconds range. The clock could run at .000001 Hz, or up to the maximum allowed by your design (550 MHz? 200 MHz? whatever you designed it for). The time it takes for the clock to enter the FPGA device (get from the pin on the board, to the silicon) is known as "flight time" and is listed in the package files (IBIS models). This is roughly the speed of light in the medium (~200 picoseconds per inch -- or ~ 8 picoseconds per mm) The time it takes for the clock signal to propagate through the clock tree, from any point, to any point, is in the timing report reported as clock skew. This can be from a few picoseconds, to more than a nanosecond (>1000 ps), depending on the size of the device, the locations, and the loading of the clock tree. AustinArticle: 144414
On Dec 4, 1:15=A0pm, "kendor" <jonas.re...@bfh.ch> wrote: > hello there > > for a measuring utility (running @ 100MHZ) I need a counter of 42-bit wid= th > whose value is used by several sub blocks of my design. As a first, someh= ow > dirty solution I have implemented this like follows. Since this approach > needs quite a huge amount of FFs and leads to long delaytimes (bit 0 to 4= 2) > I am looking for an alternative. I was thinking about using Block RAM > (Spartan3) to reduce routing effort and delaytimes. (see alsohttp://cours= es.ece.illinois.edu/ece412/References/datasheets/xapp463.pdf) > > Has anyone ever done such a thing or do you have any suggestions on solvi= ng > my task? > > current code: > ------------------------------------- > # i have to use std_logic_unsigned since numeric_std has as integer width > the normal 4 bytes width (32bit - which for 42 bits is not enough ... > overflow,..) > > # ... > GENERIC ( > =A0 t : NATURAL :=3D 42; =A0--! counter width > =A0 wd: NATURAL :=3D 5 =A0 =A0--! divider (clk/(2*wd)) > ); > > # ... > ARCHITECTURE rtl OF worldtimeCtr IS > =A0 =A0 =A0 =A0 SIGNAL cnt: std_logic_vector(t-1 downto 0); > BEGIN > =A0 =A0 =A0 =A0 PROCESS(clk,rst) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 VARIABLE temp : NATURAL RANGE 0 to wd; > =A0 =A0 =A0 =A0 BEGIN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF(rst=3D'0')THEN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt <=3D (others =3D>'0')= ; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp :=3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF(clk'event and clk=3D'1')THEN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF(en=3D'1' and temp =3D = wd)THEN > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0temp :=3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cnt <=3D STD_LOGIC= _VECTOR(cnt + 1); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp :=3D temp+1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 END if; > > =A0 =A0 =A0 =A0 END process; > =A0 =A0 =A0 =A0 o_worldtime <=3D cnt; > END rtl; > > # ... > ------------------------------------- > > thank you in advance > > kendor If you mean the input clock is running 100 MHz, then after your prescaler (temp) your 42-bit count runs at 1/6 of 100 MHz if I read this code correctly? That means the entire counter has a multicycle propagation delay to itself of about 60 ns. Did you try adding a from : to style timing constraint to let the tools realize this? Regards, GaborArticle: 144415
> 1. Verify that the timing report for Fmax is greater than the actual
> clock frequency.
> 2. Verify that the setup time requirement listed in the timing report
> for each input is actually being met in the real system.
All timings are verified, however there is one problem.
This is what I had in my 1st version of UCF:
OFFSET = OUT 15 ns AFTER "CLK"; -- ALL pins are constrained.
After viewing the reports, I've seen that not only SCODE0 is
affected by that constraint, but also the complete DBUS.
(Slave CPU writes with SCODE0, Master CPU reads with DBUS)
My thinking was/is: the master CPU will not read the data regs
until the status reg shows READY='1', so there is no need
to optimize timing from CLK to DBUS.
So I replaced my UCF with this 2nd version:
INST "SCODE0" TNM = CLK_OUT; -- constrain SCODE0 only
TIMEGRP "CLK_OUT" OFFSET = OUT 15 ns AFTER "CLK";
At first, that worked. However, after changing my READY code
things started to go wrong (and that is when I posted to this NG).
Now, I have reverted back to 1st UCF version, and the problem
is, I dare to say, gone.
Q: has that really solved my problem?
I really don't see anything wrong with my VHDL code and I had
that test prog running for hours w/o errors now.
> 3. Have the timing analyzer analyze all clock domain crossings or look
> at the final implementation for clock domain crossings
> - Does every clock domain crossing meet that requirement?
> - Did you verify that the requirement is met by viewing the final
> implementation?
I have used timing analyzer (TA) yesterday for the first time,
so I don't have much experience.
TA shows a list of constrained and unconstrained paths.
I did my best and removed almost all of the unconstrained items,
only the "Maximum Data Path: CLK to FF" have left, and they
all have the delay of only 2.2ns.
This is what I now have in my 3rd UCF:
for every global clock:
NET "CLK" TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD "CLK" 25 ns HIGH 50%;
OFFSET = IN 10 ns VALID 15 ns BEFORE "CLK";
OFFSET = OUT 15 ns AFTER "CLK";
next, all combinations of:
TIMESPEC TS_CLK1_2 = FROM "CLK1" TO "CLK2" 15 ns;
and:
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 15 ns;
> Have the timing analyzer analyze all clock domain crossings
How?
Like this: "TIMESPEC TS_CLK1_2 = FROM "CLK1" TO "CLK2" 15 ns;"?
Since I now know a little more than yesterday, I went back to 2nd UCF
file, hoping to see why that failed. TA did show some errors,
but nothing connected to the problem I was seeing, at least I think so.
Plenty of unconstrained items, but, again, no apparent connection..
In other words, I have it now working, but am not sure if the
problem is really solved, or I'm just currently lucky.
> Some of your comments are
> contradictory (only one clock, but there are multiple things being
> clocked, there are multiple clocks)
Well, there are three clocks, but only one (CLK) is important here:
- MASTERCLK just toggles WR0, and then CLK copies it to its domain.
- SCLK is connected to ordinary pin, and gets sampled with CLK.
- (MASTERCLK and CLK are connected to GCLK pins)
> - If multiple bits get moved from one domain to another (maybe the two
> bits of 'ACTIONCODE' as an example) what one *other* signal is there
> that tells you that it is OK to sample these signals and that they are
> guaranteed valid?
Only one bit is moved: SCODE0 to SHIFTIN when SCODE1='0' and rising SCLK.
The signal that tells me that it is OK to sample is rising SCLK with
SCODE1='1' and SCODE0='0'. Read my second post, maybe is not
commented well, but its all there.
Article: 144416
I am trying to minimize my bram usage for the design. My basic BRAM
code in vhdl is shown below. If I change the address width to 8 and
data width to 64 the synplify pro gives me 2 brams usage. Shouldnt it
be only one BRAM since I am using 256 * 64 = 16384 bits? Am I doing
something wrong in the vhdl code?
Appreciate any help.
Thanks.
ENTITY SDP_8_8192 Is
GENERIC(AWIDTH : INTEGER := 8; DWIDTH : INTEGER := 64);
PORT(
CLK : IN std_logic; WE : IN std_logic; ADDRA : IN std_logic_vector
(AWIDTH-1 downto 0);
ADDRB : IN std_logic_vector(AWIDTH-1 downto 0);
DIA : IN std_logic_vector(DWIDTH-1 downto 0);
DOB : OUT std_logic_vector(DWIDTH-1 downto 0)
);
end entity;
architecture synth of SDP_8_8192 is
constant MEM_DEPTH : integer := 2**AWIDTH;
type mem_array is array(0 to MEM_DEPTH-1) of std_logic_vector
(DWIDTH-1 downto 0);
signal ram : mem_array;
begin
proc: process(CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
ram(conv_integer(ADDRA)) <= DIA;
end if;
DOB <= ram(conv_integer(ADDRB));
end if;
end process;
END synth;
Article: 144417I would think it will depend on the fpga technology you are targeting as the BRAM can have different port widths and sizes. Check with the user guide for the fpga you are using. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144418
> This is what I had in my 1st version of UCF: > OFFSET = OUT 15 ns AFTER "CLK"; -- ALL pins are constrained. I forgot to mention that I also had PERIOD and OFFSET IN for CLK and PERIOD, OFFSET IN and OFFSET OUT for all other clocks.Article: 144419
Dear all I'm a new member of this board so a big hello to everybody I am using spartan 3 Starter Board, and I want to know if it supports multiprocessor architecture or not? anyone can help me Please! thank you in advance. INESArticle: 144420
On Dec 5, 4:38=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I would think it will depend on the fpga technology you are targeting as > the BRAM can have different port widths and sizes. Check with the user > guide for the fpga you are using. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com I am using virtex II pro x2vp70.I will check it out.Article: 144421
On Dec 5, 10:49=A0am, ni <nbg2...@gmail.com> wrote: > On Dec 5, 4:38=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > > > I would think it will depend on the fpga technology you are targeting a= s > > the BRAM can have different port widths and sizes. Check with the user > > guide for the fpga you are using. > > > Jon =A0 =A0 =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > This message was sent using the comp.arch.fpga web interface onhttp://w= ww.FPGARelated.com > > I am using virtex II pro x2vp70.I will check it out. Virtex II maximum data width for a single BRAM is 36 bits. However if you are careful, you can get a single-ported BRAM of 72-bits by using both ports of the same BRAM and tying off the upper address bit to 0, 1 for each respective port. For dual-port applications the limit is 36 bits. By the way using a BRAM at maximum width and dual port uses all the routing resources to the BRAM as well as the adjacent multiplier, so you will lose the use of the multiplier. Regards, GaborArticle: 144422
On Dec 4, 5:25=A0pm, "aleksa" <aleks...@gmail.com> wrote: > > Now, I have reverted back to 1st UCF version, and the problem > is, I dare to say, gone. > > Q: has that really solved my problem? > Form your original post you said... "In real world that didn't work. I wrote a test prog that has failed after several seconds. READY was set to '1' when it should have stayed '0'" Unless you can explain at least to yourself the chain of events that allowed 'READY' to be set to 1 when it should have stayed 0, I would say that no you haven''t really solved the problem because you really don't quite understand the problem. There are many things that one can change to make a problem seem to disappear, but usually they only disappear for some period of time only to reappear later...and this later time is usually at the most inopportune moment and you'll be under some real heat to fix the problem. > I really don't see anything wrong with my VHDL code and I had > that test prog running for hours w/o errors now. > Try heating and cooling the various parts with cold spray and a heat gun and see if it all still works. Look at it this way... - You had a failure (described in your original post) - You haven't explained the reason for the failure - You've put in changes that make the problem less frequent (code changes and constraint changes) - You currently have something that appears to be working (it hasn't failed after several hours) but can't explain why previous versions didn't Now ask youself, if you were the end user rather than the designer, would you feel confident that the issue has been put to rest and will never come back? > > TA shows a list of constrained and unconstrained paths. > > I did my best and removed almost all of the unconstrained items, > only the "Maximum Data Path: CLK to FF" have left, and they > all have the delay of only 2.2ns. > > This is what I now have in my 3rd UCF: > Again, more changes without understanding why the system failed in the first place. > > Since I now know a little more than yesterday, I went back to 2nd UCF > file, hoping to see why that failed. TA did show some errors, You went to the wrong place, put a scope or logic analyzer on the failing hardware. > but nothing connected to the problem I was seeing, at least I think so. > Plenty of unconstrained items, but, again, no apparent connection.. > > In other words, I have it now working, but am not sure if the > problem is really solved, or I'm just currently lucky. > Since you don't understand why it failed, you're getting lucky. There are also two forms of luck. It would be 'good luck' if you happened to stumble upon the fix without understanding the failure. It will be 'bad luck' if this change has only made the problem go away on this board (or some small set of boards) but it comes back when the design goes into production and it resurfaces. Design problems are like submarines, unless you target and sink them, they will re-surface. I'd strongly suggest reading and following the guidelines I outlined in my second posting on December 2 regarding how to debug. That process will lead you to understanding why your original two cracks at it failed. From that knowledge you'll be able to know (not guess) at whether or not your last attempt actually fixes the problem or you got lucky. Remember to start with your older failed attempts since they fail more frequently (you can't debug something that appears to be working). You need to know why something failed before you can evaluate whether you've fixed it or covered it up. Kevin JenningsArticle: 144423
On Dec 5, 11:07=A0am, Gabor <ga...@alacron.com> wrote: > On Dec 5, 10:49=A0am, ni <nbg2...@gmail.com> wrote: > > > On Dec 5, 4:38=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > > > > I would think it will depend on the fpga technology you are targeting= as > > > the BRAM can have different port widths and sizes. Check with the use= r > > > guide for the fpga you are using. > > > > Jon =A0 =A0 =A0 =A0 > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > This message was sent using the comp.arch.fpga web interface onhttp:/= /www.FPGARelated.com > > > I am using virtex II pro x2vp70.I will check it out. > > Virtex II maximum data width for a single BRAM is 36 bits. > However if you are careful, you can get a single-ported > BRAM of 72-bits by using both ports of the same BRAM > and tying off the upper address bit to 0, 1 for each > respective port. =A0For dual-port applications the limit > is 36 bits. =A0By the way using a BRAM at maximum width > and dual port uses all the routing resources to the > BRAM as well as the adjacent multiplier, so you will > lose the use of the multiplier. > > Regards, > Gabor Is there any application note which explains this stuff? I am more interested in optimizing bram usage for my architecture.Article: 144424
I just came across a couple of old Avnet eval boards for the Xilinx XC3VP7. Part number is ADS-XLX-V2PRO-EVLP7-5 and there's a product brief here: http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx_Virtex-II_Pro_Eval_Kit-Product_Brief_081103F1.pdf I'd like to find a schematic, or at least an I/O pin mapping for this board, but Avnet seems to have removed all the design materials from their site. Can anyone help? Thanks Eric
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