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A new large-diameter, permanent magnet motor line is currently under design for very low speed (2 rad/sec), high-precision (10 urad) applications. For a 3-phase motor, torque ripple is ~7%, with ripple inversely proportional to the number of phases. An attractive alternative to the standard 3-phase controller is an FPGA multi-phase controller where each stator coil is individually controlled. For the preliminary design, somewhere in the range of 30 stator coils will be utilized. Has anyone had any experience in using an FPGA for this type of application? Commercial drivers are primarily based on either trapezoidal or sinusoidal commutation schemes, and it would seem that since each coil could be individually controlled, either scheme could be readily implemented. Commercial and open cores all seem to be based on the standard 3-phase windings. If any individuals with experience in this area would be interested in working on a project such as this on a consultant basis, kindly send a brief description of relevant experience and a contact number or email address to jjacob @ acm-nevada . com (without spaces). Jon Jacob ACM NevadaArticle: 70976
Bob wrote: > > I ordered one of these yesterday, received it today. > All in all, it's a nice little testing platform. > Yes, it's a nice bundle for the asking $$: decent sized device, large x32 SRAM, download cable. I'd also like to see a version with a larger (3s400) device; even if Xilinx doesn't offer one, I'd expect that Digilent would once they start selling them directly. The board's one major shortcoming, shared with most low cost boards, is the poor signal layout of the expansion headers: 36 I/O's, one ground. It would add virtually nothing to the cost of these boards to show a little respect for the sub-ns edge rates found on modern CMOS devices, and place a ground pin every few I/O pins. The pinout probably was picked to match that of the the older Digilent boards; however, it looks like there's enough room on the layout to add a third row of ground pins so the end user could snip off the pre-stuffed two row headers and use a three row header instead. An I/O connector with diff. pair routing and provision for VRP/VRN resistors and VREF bank pins would also be handy. Maybe on the RevB layout after they sell out of these :) BrianArticle: 70977
Antti Lukats wrote:
> I do have a desing and FPGA evaluation system where I constantly see
> bitstreams that start but have erratic behavior.
Check your clock and reset.
Consider simulation before synthesis.
There are many possible sources of erratic
behavior after download.
> 2) Xilinx Virtex2 FPGA have a new feature called AutoCRC what is more
> reliable as the CRC used in older FPGAs. The normal CRC check (RCRC
> command and write to CRC register) are still being used unless its a debug
> bitstream! -- Good god, but why does impact generate bitstreams with CRC
> value fixed 0x5F57 for all Virtex2/p/s3 devices ??
I would expect a fixed crc sum for a good packet.
The packet generator should add the proper suffix word (FCS)
to make this happen.
Good luck.
-- Mike Treseler
Article: 70978On Sat, 3 Jul 2004 18:54:16 -0700, "Antti Lukats" <antti@case2000.com> wrote: <stuff snipped> >its not funny to simulate Full 1M Gate with MicroBlaze ! Does this mean it wasn't simulated? > and you can not simulate badly configured FPGA anyway, can you? No, but it remains to be seen whether that's the problem. If you haven't simulated, start there. Bob Perlman Cambrian Design WorksArticle: 70979
Hi!
Could anyone explain, what are route-throughs in look up tables and why
are they used? When I run the map command (xilinx) on my design, I get
in the report file (design.mrp) a section:
Design Summary:
Number of errors: 0
Number of warnings: 3
Number of CLBs: 124 out of 324 38%
CLB Flip Flops: 81
4 input LUTs: 203 (3 used as route-throughs)
3 input LUTs: 68 (13 used as route-throughs)
Number of bonded IOBs: 62 out of 144 43%
IOB Flops: 0
IOB Latches: 0
Number of clock IOB pads: 1 out of 8 12%
Number of primary CLKs: 1 out of 4 25%
Number of startup: 1 out of 1 100%
Thanks in advance
Frank
Article: 70980Hi until recently I did live in good faith that all decent FPGAs do have bitstream integrity checks and do not start in case of configuration loading errors. This seems not to be case at least for Xilinx Virtex2 FPGAs. I do have a desing and FPGA evaluation system where I constantly see bitstreams that start but have erratic behaviour. This can only be explained that there have been errors during download but impact (JTAG download) does not report and error and FPGA starts as it would be OK. After power off and reconfigure the error is gone. 1) from Xilinx answers: if prog_b pin is being pulsed during JTAG download then the FPGA configuration sync is lost what yields to bullshit loaded into FPGA and FPGA starting with that bullshit with no errors being reported during configuration. My system has a button and pullup resistor on prog pin - nobody is pushing it during download. 2) Xilinx Virtex2 FPGA have a new feature called AutoCRC what is more reliable as the CRC used in older FPGAs. The normal CRC check (RCRC command and write to CRC register) are still being used unless its a debug bitstream! -- Good god, but why does impact generate bitstreams with CRC value fixed 0x5F57 for all Virtex2/p/s3 devices ?? the meaning of CRC is that is not constant but calculated? Ok, the AutoCRC is written, but the AutoCRC should only operate on frame data? how are other config writes protected if the normal CRC check seems to be bypassed ??? Antti PS 0x0000DEFC !!! for those who do not know the meaning 0xDEFC its the DEFault Crc value written to CRC register when CRC check is disabled. When CRC check is enabled CRC is 0x5F57 but the meaning of that - sorry I can not decode! it must be a magical value that matches any good CRC value (a calculated value!) PPS Xilinx: where is the algorithm for AutoCRC ???Article: 70981
John Jacobs wrote: > A new large-diameter, permanent magnet motor line is currently under design > for very low speed (2 rad/sec), high-precision (10 urad) applications. For a > 3-phase motor, torque ripple is ~7%, with ripple inversely proportional to > the number of phases. That's true for a fixed voltage/sine drive : with electronics it does not have to be either. > > An attractive alternative to the standard 3-phase controller is an FPGA > multi-phase controller where each stator coil is individually controlled. > For the preliminary design, somewhere in the range of 30 stator coils will > be utilized. > > Has anyone had any experience in using an FPGA for this type of application? > Commercial drivers are primarily based on either trapezoidal or sinusoidal > commutation schemes, and it would seem that since each coil could be > individually controlled, either scheme could be readily implemented. > Commercial and open cores all seem to be based on the standard 3-phase > windings. FPGA would be well suited to this, as would higher end DSPs, and some DSP vendors have specific motor development kits. At the extremes of precision, the problems are not just electrical - the best motor-optimise designs I have seen, include a Motor-Cal-ROM, that is the calibrations of that particular motor. High precision absolute Rotary encoder feedback is another method to check/calibrate the motor behaviour. Also remember copper wire has a significant temperature coefficent. -jgArticle: 70982
hi Has anyone used the uClinux port on the Xilinx MicroBlaze? thanks, gesmith __ George Smith Linear Acoustic, IncArticle: 70983
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:-c2dnd1xN7olRnvd4p2dnA@comcast.com... > Antti Lukats wrote: > > > I do have a desing and FPGA evaluation system where I constantly see > > bitstreams that start but have erratic behavior. > > Check your clock and reset. > Consider simulation before synthesis. > There are many possible sources of erratic > behavior after download. this erratic behaviour only happens with known good working bitstream on some downloads. the whole system (1M gate system with MicroBlaze system) is working but soft core microcontroller sees some hard-wired registers return random data (not pre programmed constant). This bad register is consistent for one download attempt and persist after hardware reset also. you have hardwired register that should be read as 0xAA always - but on some download attempts it reads lets 0xE1 every time you do hardware reset. next download is ok again. its not funny to simulate Full 1M Gate with MicroBlaze ! and you can not simulate badly configured FPGA anyway, can you? hm but the check clock and reset, hm, that is a good thing todo maybe, the system has 2 clock domains running from 2 different external clock inputs and 3 DCMs. So the reset of the system is not simple. and yes the register that returns bad data is in other clock domain the system SoC. > > 2) Xilinx Virtex2 FPGA have a new feature called AutoCRC what is more > > reliable as the CRC used in older FPGAs. The normal CRC check (RCRC > > command and write to CRC register) are still being used unless its a debug > > bitstream! -- Good god, but why does impact generate bitstreams with CRC > > value fixed 0x5F57 for all Virtex2/p/s3 devices ?? > > I would expect a fixed crc sum for a good packet. > The packet generator should add the proper suffix word (FCS) > to make this happen. but the fixed checksum doesnt seem possible there are 2 checksum locations 1 AutoCRC after frame data this calculated and OK 2 normal CRC this is fixed to 5F57 no way the AutoCRC is correct CRC for previous data and also fixes the next CRC to have a constant value!! > Good luck. > > -- Mike Treseler thanks, Mike AnttiArticle: 70984
In both cases it sounds like you are missing carriage returns or line feeds. The staircase pattern is an classic example. You may need to set minicom to append carriage returns to incoming line feeds, to echo typed characters, or to send carriage returns with line feeds. Once you are sure both CR & LF is part of every line, it should be clear when you need them and when you don't. Nigel Gunton CEMS STAFF wrote: > Hi, > I'm having problems getting nios-run -t to function correctly. The > development platform is Quartus 3 sp2, SOPC 3.02 on Linux, Apex board. > > I'm using the standard_32 example provided with the Nios kit 3.2. This > builds (SDK and the hardware) without apparent problem, synthesises and > can be downloaded via the jtag interface. > > executing nios-run -t results in the peripherals test menu being displayed > but no response to keyboard input occurs, except ^C which occasionally > requires repeating to get the program to quit. Running strace shows > repeated calls to query the keyboard via select(), but only the ^c is > picked up on. > > Running minicom permits access to germs: and to the peripheral tests, > albeit with a 'staircase' problem on the output from the peripherals test, > but at least I have 2 way communication which implies that the problem > lies with nios-run. > > Running nios-run -p with a download file results in it waiting > indefinitely for the board to respond, both with the factory default and > the jtag downloaded file. > > Has anybody had similar problems? A search through the archives didn't > find anything, hence the post. > > AFAIUS, I need to use nios-run to reprogram the onboard flash or is there > an alternative. > > thanks in advance, > nigelg. > > -- > Nigel Gunton Office: +44/0 117 32 83167 /"\ > CEMS, UWE, Bristol, BS16 1QY. \ / > X > ASCII Ribbon Campaign against HTML email & microsoft attachments / \ >Article: 70985
Hy all, I'm currently implementing a receiver (vhdl) part of the ethernet mac which is responsible for the MII interafce. I'm need an crc32 calculator (RTL) to check the FCS field. I've tried using the easics crctoll in order to create the mechanism (for a 4 bit data input) but it does not seems to work. does anyone have a working (rtl) vhdl implementation for this block? or at least a detailed expalnation on how to create it..? Thanks in advance, Moti.Article: 70986
Moti Cohen wrote:
> Hy all,
> I'm currently implementing a receiver (vhdl) part of the ethernet mac
> which is responsible for the MII interafce. I'm need an crc32
> calculator (RTL) to check the FCS field. I've tried using the easics
> crctoll in order to create the mechanism (for a 4 bit data input) but
> it does not seems to work. does anyone have a working (rtl) vhdl
> implementation for this block? or at least a detailed expalnation on
> how to create it..?
Howdy Moti,
I'd be willing to bet that your problem is bit ordering (hint: take
an 8 bit chunk and reverse the order of the bits before throwing it into
the easics checker). Although I'm sure there is probably a way, I don't
quickly see how you'd do it four bits at a time.
Good luck,
Marc
Article: 70987> only needs one power supply (3.3V). On the power side it is also less > power hungry and you can probably do with a linear regulator and not > use switch mode power (witch is a pest when coming to size, those darn > inductors and caps are real board eaters). Isn't linear require a heat dissapiation area? So, if a regulator is a consern, a variant with external regulator may me considered. Right?Article: 70988
Thank you Brian! It seems to work with me. Best Regards, Kelvin "Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message news:cc4jjh$4pg1@xco-news.xilinx.com... > > > Tim wrote: > > > Kelvin wrote: > > > >>I am compiling a partial design with XST. I can only use 24 > >>multipliers in my portion of a V2-6000 chip... > >>However, the RTL has 35 multipliers... > >>Now I need to compile the other 11 multipliers with LUT, but I don't > >>want to modify the RTL codes... > >>How may I handle this situation? > >> > >>"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK > >>makes all multipliers with > >>block multiplers...sigh... > > > > > > Tell the synth that you are compiling for a smaller chip? > > > > > > > > Looks to me that MULT_STYLE is an attribute as well as a synthesis > option meaning you can either use it globally as it sounds you may have > done or attach it on certain modules or certain signals to specify how > to implement individual multipliers in your code. As a quick test, I > wrote the following code and got one multiplier built from LUTs and the > other using the MULT18X18S block: > > `timescale 1ns/1ps > > module mult_style_test (A, B, C, CLK, X, Y, Z); > > input [10:0] A; > input [10:0] B; > output [21:0] C; > input CLK; > input [10:0] X; > input [10:0] Y; > output [21:0] Z; > > reg [21:0] C; // synthesis attribute mult_style of C is lut; > reg [21:0] Z; // synthesis attribute mult_style of Z is block; > > always @(posedge CLK) > Z <= X * Y; > > always @(posedge CLK) > C <= A * B; > > endmodule > > > -- Brian >Article: 70989
However, the following code seemed fail...Maybe D & E are removed in the
synthesis.
`timescale 1ns/1ps
module mult_style_test (A, B, C, CLK, X, Y, Z);
input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;
reg [21:0] C; // synthesis attribute mult_style of C is block;
reg [21:0] Z;
wire [21:0] D;
wire [21:0] E;
assign D = X * Y; // synthesis attribute mult_style of D is lut;
assign E = A * B; // synthesis attribute mult_style of E is block;
always @(posedge CLK)
Z <= D + E;
always @(posedge CLK)
C <= A * B - X * Y;
endmodule
"Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message
news:cc4jjh$4pg1@xco-news.xilinx.com...
>
>
> Tim wrote:
>
> > Kelvin wrote:
> >
> >>I am compiling a partial design with XST. I can only use 24
> >>multipliers in my portion of a V2-6000 chip...
> >>However, the RTL has 35 multipliers...
> >>Now I need to compile the other 11 multipliers with LUT, but I don't
> >>want to modify the RTL codes...
> >>How may I handle this situation?
> >>
> >>"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
> >>makes all multipliers with
> >>block multiplers...sigh...
> >
> >
> > Tell the synth that you are compiling for a smaller chip?
> >
> >
>
>
>
> Looks to me that MULT_STYLE is an attribute as well as a synthesis
> option meaning you can either use it globally as it sounds you may have
> done or attach it on certain modules or certain signals to specify how
> to implement individual multipliers in your code. As a quick test, I
> wrote the following code and got one multiplier built from LUTs and the
> other using the MULT18X18S block:
>
> `timescale 1ns/1ps
>
> module mult_style_test (A, B, C, CLK, X, Y, Z);
>
> input [10:0] A;
> input [10:0] B;
> output [21:0] C;
> input CLK;
> input [10:0] X;
> input [10:0] Y;
> output [21:0] Z;
>
> reg [21:0] C; // synthesis attribute mult_style of C is lut;
> reg [21:0] Z; // synthesis attribute mult_style of Z is block;
>
> always @(posedge CLK)
> Z <= X * Y;
>
> always @(posedge CLK)
> C <= A * B;
>
> endmodule
>
>
> -- Brian
>
Article: 70990never mind, it does apply to a wire also...Can test with these code... assign D = A * Y; // synthesis attribute mult_style of D is lut; assign E = X * B; // synthesis attribute mult_style of E is block; "Kelvin" <student@nowhere.com> wrote in message news:40e8f2bb@news.starhub.net.sg... > However, the following code seemed fail...Maybe D & E are removed in the > synthesis. > > > > > > `timescale 1ns/1ps > > module mult_style_test (A, B, C, CLK, X, Y, Z); > > input [10:0] A; > input [10:0] B; > output [21:0] C; > input CLK; > input [10:0] X; > input [10:0] Y; > output [21:0] Z; > > reg [21:0] C; // synthesis attribute mult_style of C is block; > reg [21:0] Z; > wire [21:0] D; > wire [21:0] E; > > assign D = X * Y; // synthesis attribute mult_style of D is lut; > assign E = A * B; // synthesis attribute mult_style of E is block; > > always @(posedge CLK) > Z <= D + E; > > always @(posedge CLK) > C <= A * B - X * Y; > > endmodule > > > "Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message > news:cc4jjh$4pg1@xco-news.xilinx.com... > > > > > > Tim wrote: > > > > > Kelvin wrote: > > > > > >>I am compiling a partial design with XST. I can only use 24 > > >>multipliers in my portion of a V2-6000 chip... > > >>However, the RTL has 35 multipliers... > > >>Now I need to compile the other 11 multipliers with LUT, but I don't > > >>want to modify the RTL codes... > > >>How may I handle this situation? > > >> > > >>"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK > > >>makes all multipliers with > > >>block multiplers...sigh... > > > > > > > > > Tell the synth that you are compiling for a smaller chip? > > > > > > > > > > > > > > Looks to me that MULT_STYLE is an attribute as well as a synthesis > > option meaning you can either use it globally as it sounds you may have > > done or attach it on certain modules or certain signals to specify how > > to implement individual multipliers in your code. As a quick test, I > > wrote the following code and got one multiplier built from LUTs and the > > other using the MULT18X18S block: > > > > `timescale 1ns/1ps > > > > module mult_style_test (A, B, C, CLK, X, Y, Z); > > > > input [10:0] A; > > input [10:0] B; > > output [21:0] C; > > input CLK; > > input [10:0] X; > > input [10:0] Y; > > output [21:0] Z; > > > > reg [21:0] C; // synthesis attribute mult_style of C is lut; > > reg [21:0] Z; // synthesis attribute mult_style of Z is block; > > > > always @(posedge CLK) > > Z <= X * Y; > > > > always @(posedge CLK) > > C <= A * B; > > > > endmodule > > > > > > -- Brian > > > >Article: 70991
Hi Frank, There is an XOR gate (mainly for arith operations) in xilinx slice. whenever synthesis tool uses this XOR gate for some operation, LUT is used in bypass mode (i.e input is directly connected to output) and that is the only way to access XOR gate. All these LUTs are reported as route-throughs in mapping report frle@hrz.tu-chemnitz.de wrote in message news:<cc6ree$3sf$1@anderson.hrz.tu-chemnitz.de>... > Hi! > > Could anyone explain, what are route-throughs in look up tables and why > are they used? When I run the map command (xilinx) on my design, I get > in the report file (design.mrp) a section: > > Design Summary: > Number of errors: 0 > Number of warnings: 3 > Number of CLBs: 124 out of 324 38% > CLB Flip Flops: 81 > 4 input LUTs: 203 (3 used as route-throughs) > 3 input LUTs: 68 (13 used as route-throughs) > Number of bonded IOBs: 62 out of 144 43% > IOB Flops: 0 > IOB Latches: 0 > Number of clock IOB pads: 1 out of 8 12% > Number of primary CLKs: 1 out of 4 25% > Number of startup: 1 out of 1 100% > > Thanks in advance > > FrankArticle: 70992
What special did u find on it?? on the first glance it looks similar to what altera is proving for year as DSP block paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>... > I am just wandering if any of you have take a look at the Lattice > FPGAs. I do like the DSP functions. > is out there any serious comparation against SpartanIII and Cyclone? > > regards, > > paulArticle: 70993
go to have a look at John's work: Microblaze uClinux Project Home Page http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ tk "George Smith" <gesmith@linearacoustic.com> ???????:pan.2004.07.04.01.11.15.824679@linearacoustic.com... > hi > Has anyone used the uClinux port on the Xilinx MicroBlaze? > thanks, > gesmith > > __ > George Smith > Linear Acoustic, Inc >Article: 70994
"Simon Peacock" <nowhere@to.be.found> wrote in message news:<40e60e27@news.actrix.gen.nz>... > Actually.. I believe they charge you a license fee if you move sites.. for > their time and effort of course They even charge if you move from one license server to another when they are in the same location. Rehosting they call it, and it cost money even if you have maintenance contract. Milage may of cource vary. It is amazing that noone from the vendors have even tried to make their policies clear. There are enough of them listening on these channels. Working off-site is very easy with the flexlm license system since you only need to transfer the licensing info. Most programs check out license when they start, and then keep it, which is very convenient on a low bandwidth line like a DSL or modem line. Working off-site could save a lot of jobs since you don't need to move where the engineers are, have the engineers telecommute to you. Just my opinion on the topic. -- SvennArticle: 70995
moti@terasync.net (Moti Cohen) wrote in message news:<c04bfe33.0407040651.2199a09f@posting.google.com>...
> Hy all,
> I'm currently implementing a receiver (vhdl) part of the ethernet mac
> which is responsible for the MII interafce. I'm need an crc32
> calculator (RTL) to check the FCS field. I've tried using the easics
> crctoll in order to create the mechanism (for a 4 bit data input) but
> it does not seems to work. does anyone have a working (rtl) vhdl
> implementation for this block? or at least a detailed expalnation on
> how to create it..?
> Thanks in advance, Moti.
Hi,
I've developped, for my personnal needs, a crc software. I've took for
inputs : g(x)=x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7
+ x5 + x4 + x2 + x + 1
and 4 bits bus.
The results are :
-- x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7
+ x^5 + x^4 + x^2 + x^1 + 1
function fcrc(DIN : std_logic_vector(3 downto 0); CRC :
std_logic_vector(31 downto 0))
return std_logic_vector is
variable RESUL : std_logic_vector(31 downto 0);
begin
RESUL( 0):=CRC(28) xor DIN(0);
RESUL( 1):=CRC(28) xor CRC(29) xor DIN(0) xor DIN(1);
RESUL( 2):=CRC(28) xor CRC(29) xor CRC(30) xor DIN(0) xor DIN(1)
xor DIN(2);
RESUL( 3):=CRC(29) xor CRC(30) xor CRC(31) xor DIN(1) xor DIN(2)
xor DIN(3);
RESUL( 4):=CRC(0) xor CRC(28) xor CRC(30) xor CRC(31) xor DIN(0)
xor DIN(2) xor DIN(3);
RESUL( 5):=CRC(1) xor CRC(28) xor CRC(29) xor CRC(31) xor DIN(0)
xor DIN(1) xor DIN(3);
RESUL( 6):=CRC(2) xor CRC(29) xor CRC(30) xor DIN(1) xor DIN(2);
RESUL( 7):=CRC(3) xor CRC(28) xor CRC(30) xor CRC(31) xor DIN(0)
xor DIN(2) xor DIN(3);
RESUL( 8):=CRC(4) xor CRC(28) xor CRC(29) xor CRC(31) xor DIN(0)
xor DIN(1) xor DIN(3);
RESUL( 9):=CRC(5) xor CRC(29) xor CRC(30) xor DIN(1) xor DIN(2);
RESUL(10):=CRC(6) xor CRC(28) xor CRC(30) xor CRC(31) xor DIN(0)
xor DIN(2) xor DIN(3);
RESUL(11):=CRC(7) xor CRC(28) xor CRC(29) xor CRC(31) xor DIN(0)
xor DIN(1) xor DIN(3);
RESUL(12):=CRC(8) xor CRC(28) xor CRC(29) xor CRC(30) xor DIN(0)
xor DIN(1) xor DIN(2);
RESUL(13):=CRC(9) xor CRC(29) xor CRC(30) xor CRC(31) xor DIN(1)
xor DIN(2) xor DIN(3);
RESUL(14):=CRC(10) xor CRC(30) xor CRC(31) xor DIN(2) xor DIN(3);
RESUL(15):=CRC(11) xor CRC(31) xor DIN(3);
RESUL(16):=CRC(12) xor CRC(28) xor DIN(0);
RESUL(17):=CRC(13) xor CRC(29) xor DIN(1);
RESUL(18):=CRC(14) xor CRC(30) xor DIN(2);
RESUL(19):=CRC(15) xor CRC(31) xor DIN(3);
RESUL(20):=CRC(16);
RESUL(21):=CRC(17);
RESUL(22):=CRC(18) xor CRC(28) xor DIN(0);
RESUL(23):=CRC(19) xor CRC(28) xor CRC(29) xor DIN(0) xor DIN(1);
RESUL(24):=CRC(20) xor CRC(29) xor CRC(30) xor DIN(1) xor DIN(2);
RESUL(25):=CRC(21) xor CRC(30) xor CRC(31) xor DIN(2) xor DIN(3);
RESUL(26):=CRC(22) xor CRC(28) xor CRC(31) xor DIN(0) xor DIN(3);
RESUL(27):=CRC(23) xor CRC(29) xor DIN(1);
RESUL(28):=CRC(24) xor CRC(30) xor DIN(2);
RESUL(29):=CRC(25) xor CRC(31) xor DIN(3);
RESUL(30):=CRC(26);
RESUL(31):=CRC(27);
return RESUL;
end fcrc;
Tell me (in the news group) if it's ok.
Article: 70996IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice is proposing is much richer: reg, mult, pipeline reg, accu, reg. On top of it, the IO cell has more regs than any other comparable architecture. Anyone tried to implement DDR333 on Cyclone or S3? rgrds, On 4 Jul 2004 23:42:00 -0700, digari@dacafe.com (digari) wrote: >What special did u find on it?? on the first glance it looks similar >to what altera is proving for year as DSP block > >paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>... >> I am just wandering if any of you have take a look at the Lattice >> FPGAs. I do like the DSP functions. >> is out there any serious comparation against SpartanIII and Cyclone? >> >> regards, >> >> paulArticle: 70997
Marc Randolph <mrand@my-deja.com> wrote in message news:<u4ednTCBZ4B5q3XdRVn-vA@comcast.com>... > Moti Cohen wrote: > > Hy all, > > I'm currently implementing a receiver (vhdl) part of the ethernet mac > > which is responsible for the MII interafce. I'm need an crc32 > > calculator (RTL) to check the FCS field. I've tried using the easics > > crctoll in order to create the mechanism (for a 4 bit data input) but > > it does not seems to work. does anyone have a working (rtl) vhdl > > implementation for this block? or at least a detailed expalnation on > > how to create it..? > > Howdy Moti, > > I'd be willing to bet that your problem is bit ordering (hint: take > an 8 bit chunk and reverse the order of the bits before throwing it into > the easics checker). Although I'm sure there is probably a way, I don't > quickly see how you'd do it four bits at a time. > > Good luck, > > Marc Hi Marc, Thanks for your answer so first of all I have already tried revesring the bits order without any success - I read something about a "magic number" but I'm not sure what to do with it. regarding the 4 bit data path - the easics "crctoll" can generate a vhdl file for 1,2,4,8...64 bits so its not the problem..Article: 70998
"Moti Cohen" <moti@terasync.net> wrote in message news:c04bfe33.0407040651.2199a09f@posting.google.com... > Hy all, > I'm currently implementing a receiver (vhdl) part of the ethernet mac > which is responsible for the MII interafce. I'm need an crc32 > calculator (RTL) to check the FCS field. I've tried using the easics > crctoll in order to create the mechanism (for a 4 bit data input) but > it does not seems to work. does anyone have a working (rtl) vhdl > implementation for this block? or at least a detailed expalnation on > how to create it..? > Thanks in advance, Moti. Hi Moti, I have done a CRC32 with 16bit parallel input using easics and it took me loads of time to figure out that it was working perfectly from the beginning.! Speaking with more people, I found out that most of them had similar problems verifying the outcome. My advice is to sit down and find a methodical way to test it. http://rcswww.urz.tu-dresden.de/~sr21/crc.html using this calculator and putting the settings CRC order (1..64) : 32 CRC polynom (hex) :4C11DB7 Initial value (hex) :FFFFFFFF Final XOR value (hex) : 0 direct : checked and the rest of options: unchecked worked for me at least. Check this link too, it has one more crc_gen, (I haven't used it myself though). http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1998f/ethernet/ethernet.html#vhdlArticle: 70999
Thank you for your information.
Am I correct that a bootloop application would bee something as simple as
loop:
b loop
and be placed at address 0xFFFFFFFE (the start address for the PPC405)
How would I do that? Do I need to do it manually?
We are using EDK and ISE version 6.1
Cheers
// Jonas
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