Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi siriuswmx,
"siriuswmx" <wangmanxi@yahoo.com> schrieb im Newsbeitrag news:4528663b.0212021655.4951876@posting.google.com...
> hi. everybody,
> I wrote a program in VHDL to realize the following function : if
> en=1 ,x is latched into reg_x, y is latched into reg_y after "not" has
> been excuted in alu.
> if en=0 , x adds y in alu.
> I used xilinx2.1 to simulate it
Don't use a synthesis tool for simulation, use a simulator instead
(e.g. ModelsimXE, it's part of the free webpack).
> but failed , and i found that x was
> latched into reg_x just when en=0, but y into reg_y when en=1.
> Someone have told me that there must be something wrong with the
> difference with register and latch , but he knows little about it.
> Can you help me ?
> Thank you!
I looked at your source code and saw the following: in the second
process (step2) your sensitivity list is incomplete, the signals
"reg_x" and "reg_y" are missing. So you might also have another
result during simulation.
> step2:process(en,y) -- correct to: ...(en,y,reg_x,reg_y)
> begin
> if en='1' then
> a_in<=y;
> ci_in<="01";
> b_in<="00000000";
> else
> b_in<=reg_x;
> a_in<=reg_y;
> ci_in<="10";
> end if;
> end process;
>end alg;
Best regards,
Markus Sponsel
Article: 50126In Xilinx FPGA, use block RAM just like CPU use RAM, at least need wait one cycle to get the output, but it doesn't use LUT or slice, distributed RAM usually based on LUTs, you can get the output almost immediately, but it increase the number of slice that be used In some respects, block and distributed RAM just like RAM and cache in computer. "longjin" <lchin1@excite.com> 写入消息新闻 :21cf9f42.0212022209.45362d05@posting.google.com... > Does any know the difference between block and distributed RAM in terms > of application and functionality. The question seems trivial but please > enlighten just to verify my doubt. Thanks. > > There is no where to find the difference.Article: 50127
Austin Franklin wrote: > > > Hi Kevin, > > If you are interested in having your core PCI-SIG compliance tested, I do > that using an Agilent E2928A PCI analyzer for a fixed price for either > target only or target/master. Price depends on what you are able to send > me. As an example, if you send me a complete machine, software all loaded > with your driver etc. and a script that runs the code that will run your > board, for a target only, it's $500. > > Austin Austin, Because I am not spending much money on my project, I have been doing most of the verification work on a simulator, and plan to keep it that way. Kevin Brace (If you want to respond to what I wrote, I prefer if you will do so within the newsgroup.)Article: 50128
The latch is in step1 process. Since this is combinatorial logic you have to complete the "if" expression with "else". Otherwise the output gets latched. Matjaz "siriuswmx" <wangmanxi@yahoo.com> wrote in message news:4528663b.0212021657.6bfd6b3a@posting.google.com... > My program : > > Library IEEE; > use IEEE.std_logic_1164.all; > use work.alu_package.all; > entity x_y is > port(x,y:in std_logic_Vector(7 downto 0); > z:out std_logic_vector(7 downto 0); > en:in std_logic); > end x_y; > > > end x_y; > architecture alg of x_y is > signal a_in,b_in,c_out,reg_x,reg_y:std_logic_vector(7 downto 0); > signal ci_in:std_logic_vector(1 downto 0); > begin > z<=c_out; > u1:alu8 port map(a_in,b_in,c_out,ci_in); > step1:process(en,x,c_out) > begin > if en='1' then > reg_x<=x; > reg_y<=c_out; > end if; > end process; > > step2:process(en,y) > begin > if en='1' then > a_in<=y; > ci_in<="01"; > b_in<="00000000"; > else > b_in<=reg_x; > > > b_in<=reg_x; > a_in<=reg_y; > ci_in<="10"; > end if; > end process; > end alg; > > Thanks ! :)Article: 50130
I guess it would be nice to have the DCI single series termination without the power hungry parallel one on receive for SSTL2 class 1 or 2 point to point data bus solutions - eg. 1 V2 talking to 1 DDR SDRAM bank. The V2 and V2 PRO don't support this as far as I know but it would save a large amount of W in the device (especially with a very wide data bus). Otherwise you are stuck with adding resistor arrays although the poducts from Calmicro can help reduce board area if you like BGA's. Bill "A. Karen Alfke" <karen@2ndesign.com> wrote in message news:3DE65EC7.47A83E06@2ndesign.com... > Peter wrote > > > > > > .........For series termination, one can turn on parts of both transistors, > > > each with the desired resistance value. That's what causes the static > > > current and the power consumption, which can be quite high if busses > > > are terminated this way. > > I should of course have written: For parallel termination.... > Too much German beer of French wine??? > Peter Alfke, Xilinx Applications > > >Article: 50131
Hi is it possible to use an old isa vga card connected to an FPGA for video output? what must be sent over the bus to get it working? or is there another - easier - way to get a monitor connected to my FPGA. all hints welcome ThomasArticle: 50132
Hello, does anyone knows if is it possible configure leonardo in order to NOT instance clock pad and clock buffer? I have checked the box exclude gates yet. Thank you RosariaArticle: 50133
Hi there.. I'm experiencing quite a few problems with Windows XP and Impact. I did a total reinstall of my OS, and then it seemed to be working (using a JTAG cable for downloading firmware to a XC9500). But yesterday it suddenly refused to work, some failures regarding boundering scan or something like that. Since then I haven't been able to get it to work again. Any ideas on how to correct this particular problem? PS. Impact works in Windows 2000. So it seems to be a problem specific to Windows XP. -- I doubt, therefore I might be.Article: 50134
Why not? But you need to have the data sheet of your VGA controller. If a 8bit VGA board, then, use the PicoBlaze to inface with the VGA controller and write your algo using PicoBlaze asm. Very simple to do, but you have to know your VGA controller! Regards, Laurent Gauch, http://www.amontec.com Thomas Buerner wrote: > Hi > > is it possible to use an old isa vga card connected to an FPGA > for video output? what must be sent over the bus to get it working? > > or is there another - easier - way to get a monitor connected to > my FPGA. > all hints welcome > > ThomasArticle: 50135
Hi, I have generated a 64:1 Multiplexer using Coregen. and In some cases i have to use this 64:1 multiplexer as 8:1 multiplexer. So, for this i am connecting the unused inputs(selection and data) to Zeros. Since the coregen macro is generated with RPM, it is giving the below error during the Mapping Phase ---------------------------------- ERROR:Pack - A collection of symbols which have restrictive placement or routing requirements has some symbols contained within the RPM "test_ins1/mux_64_ins 1/hset", and some symbols not contained within the RPM. The collection is: A wide function starting with F8 mux "MUXF8" ----------------------------------- How can we eliminate this? Best regards, MuthuArticle: 50136
wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0212021655.4951876@posting.google.com>... > hi. everybody, > I wrote a program in VHDL to realize the following function : if > en=1 ,x is latched into reg_x, y is latched into reg_y after "not" has > been excuted in alu. > if en=0 , x adds y in alu. > I used xilinx2.1 to simulate it but failed , and i found that x was > latched into reg_x just when en=0, but y into reg_y when en=1. > Someone have told me that there must be something wrong with the > difference with register and latch , but he knows little about it. > Can you help me ? > Thank you! could you u provide the piece of code to check? Rgds, MuthuArticle: 50137
/shameless plug on Have a look at http://www.bittware.com/ We have a couple of PMC boards (can be mounted on PCI adaptors or on any PMC site) with Virtex IIs. One has a Sharc 21160 and the V2, one has a couple of 105 MHz ADCs with the V2, and another is basically a V2 with I/O headers. All have a dedicated 64/66 PCI interface chip separate from the Virtex, and large (up to 512 MByte) Sdram. / shameless plug off ---- Ron Huizen Bittware Seth wrote: > > I am looking for vendors of PCI FPGA boards for production, not just > prototyping. > > So far I know of Annapolis Microsystems which offers boards with > Virtex chips and RAM. > > Can anyone recommend any others?Article: 50138
I'm not sure where you're getting your pricing information from, but it doesn't seem accurate to me. Note that a 21160 is not a $30 part, so maybe you're looking at our quad 21160 board, not our quad 21161 board, which is substantially less expensive. Also note that if you only ask for low volume quotes, the pricing will be MUCH higher than reasonable volume orders - support almost seems inversely proportional to order size. The toolkit (our windows and linux API) and VDSP are one time costs. Also, note that you'll need Visual DSP whether you buy boards or develop your own - there are no shareware compilers for the 21161 or 21160, and you'll also probably want an emulator, though with our boards we do have a software plugin for the VDSP debugger that is cheaper. Also, the $13K for a quad Tiger is way off as well - are you including the cost of VDSP and the toolkit in it, which are time development costs? --- Ron Huizen BittWare John Jacob wrote: > > > Take a look at the Bittware SharcFin ASIC. It was designed exactly for > what > > you seem to be asking for: > > http://www.bittware.com/products/app-specific/ic.stm > > > > A quad DSP board for a PCI slot runs ~5K, with another 3K for the Visual DSP > and 2K for their API - ~10K total. That seems expensive considering the > chips are only ~30, PCB manufactures are at 1/2 capacity for lack of work, > and shareware compilers are readily available. > > Their TigerSHARC board is likewise expensive - ~13K for (4) 1500 MFLOP DSP > chips that list for ~200 each.Article: 50139
Hi, I'm currently developing a project with a xc2s300 Xilinx FPGA. Now I need to purchase the corresponding PROM. It's supposed to be the xc17S300a. This IC is hard to find in the market. Then I heart about an Atmel replacement. The AT17LV002. Is this true? Is this a valid replacement, are there any differences? Looking at the pines and the signals over time there are some differences but quite small, though. But even for this PROM, were can I purchase it? Finally, are there more/better replacement then these? Were can I find them. Perhaps it's possible to get a sample. Can anybody help me? Thanks in advanceArticle: 50140
Bill Blyth wrote: > > I guess it would be nice to have the DCI single series termination without > the power hungry parallel one on receive for SSTL2 class 1 or 2 point to > point data bus solutions - eg. 1 V2 talking to 1 DDR SDRAM bank. > > The V2 and V2 PRO don't support this as far as I know but it would save a > large amount of W in the device (especially with a very wide data bus). > Otherwise you are stuck with adding resistor arrays although the poducts > from Calmicro can help reduce board area if you like BGA's. Maybe I am missing something, but since when do you use both series and parallel termination at the same time? Series works fine for point to point and use little power. The parallel form works with a single driver and multiple destinations in a daisy chain and the termination as the last destination. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50141
Thomas Buerner wrote: > > Hi > > is it possible to use an old isa vga card connected to an FPGA > for video output? what must be sent over the bus to get it working? > > or is there another - easier - way to get a monitor connected to > my FPGA. > all hints welcome > > Thomas Yes, you can interface to a ISA video card if you have a means of programming the registers and drawing your images in memory. I assume you are connected to a MCU or similar. Another way is to build the controller into your FPGA. If you only need text display then you can use a very simple controller indeed and can likely use the on chip memory. There are several types here. http://www.opencores.com/projects/ -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50142
I've seen discussions here about clock distribution over circuit boards but my application is slightly different than those previously mentioned. I am building a multi-FPGA system based on the XC2S200E part from Xilinx, whereby each device and its corresponding SRAMs are socketed via a PCI-like cardedge connector. The FPGAs are to talk to each other via a bus protocol similar to that used in Intel-based SMPs. In order to do this, each FPGA needs to be using the same clock to handle proper timeslicing. Now, my application requires very speedy access to the on-circuit SRAM chips and so I was anticipating using 4X the FPGA clock to "quad-pump" memory I/O. The SRAM devices are 7ns, so I was figuring using a 33Mhz mainboard clock, distributing it to each device and having the FPGA's memory controller run on a 4X clock. The Spartan, if I recall correctly, can only do 2X multiplication. How can I overcome this problem? Do I simply distribute a 66Mhz clock and use the 2X multiplier? It is likely there will only be one or two runs of the board and everything will be hand-soldered, so I'm wondering if junction capacitance will be too high to allow a clean 66Mhz clock. The target bus will be 4-8 cards, each with one XC2S200E device and four high-speed SRAMs. Thanks. -- Brian Wickman Center for Advanced Computing http://www.brianwickman.com http://cac.engin.umich.eduArticle: 50143
According to the V2 SSTL2 DCI diagrams in DS031.PDF, you can't have just the series resistor in a bidirectional pad you must take the parallel termination and the subsequent power hit. I agree series works fine but for bidirectionals using SSTL2 it is not possible to use DCI and the resistors have to go on the outside. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3DECC853.EE5E933F@yahoo.com... > Bill Blyth wrote: > > > > I guess it would be nice to have the DCI single series termination without > > the power hungry parallel one on receive for SSTL2 class 1 or 2 point to > > point data bus solutions - eg. 1 V2 talking to 1 DDR SDRAM bank. > > > > The V2 and V2 PRO don't support this as far as I know but it would save a > > large amount of W in the device (especially with a very wide data bus). > > Otherwise you are stuck with adding resistor arrays although the poducts > > from Calmicro can help reduce board area if you like BGA's. > > Maybe I am missing something, but since when do you use both series and > parallel termination at the same time? Series works fine for point to > point and use little power. The parallel form works with a single > driver and multiple destinations in a daisy chain and the termination as > the last destination. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50144
Bill, Maybe I'm confused. SSTL2 Class II is a bidirectional IO standard. It has symmetric arrangements of resitors, so that it can be tristate and/or bidirectional (transmit or receive). The DCI version of it in Virtex II and II Pro works just fine, but as has been pointed out, does dissipate the power inside the chip, as opposed to outside the chip in external resistors (the power has to be dissipated somewhere). How about using LVDCI as the bidirectional interface? Series termination while driving means low power and no external resistors, and the receive side is fine while the driver is tristate. TANSTAAFL* Austin *No free lunch, somebody has to match the t-lines. Or to paraphrase another sci-fi author "Resistance is mandatory!". Bill Blyth wrote: > According to the V2 SSTL2 DCI diagrams in DS031.PDF, you can't have just the > series resistor in a bidirectional pad you must take the parallel > termination and the subsequent power hit. > > I agree series works fine but for bidirectionals using SSTL2 it is not > possible to use DCI and the resistors have to go on the outside. > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3DECC853.EE5E933F@yahoo.com... > > Bill Blyth wrote: > > > > > > I guess it would be nice to have the DCI single series termination > without > > > the power hungry parallel one on receive for SSTL2 class 1 or 2 point to > > > point data bus solutions - eg. 1 V2 talking to 1 DDR SDRAM bank. > > > > > > The V2 and V2 PRO don't support this as far as I know but it would save > a > > > large amount of W in the device (especially with a very wide data bus). > > > Otherwise you are stuck with adding resistor arrays although the poducts > > > from Calmicro can help reduce board area if you like BGA's. > > > > Maybe I am missing something, but since when do you use both series and > > parallel termination at the same time? Series works fine for point to > > point and use little power. The parallel form works with a single > > driver and multiple destinations in a daisy chain and the termination as > > the last destination. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50145
LVDCI would be nice but not for DDR SDRAM using SSTL2. A version of SSTL2_II_DCI where you have the driver series resistor in the IOB but not the parallel termination would allow single parallel termination to be used elsewhere on the board or in another device and reduce overall system power consumption whilst still meeting the JEDEC spec. It's not resistor-less but less-resistors. Bill "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3DECDE61.BA22ED8A@xilinx.com... > Bill, > > Maybe I'm confused. > > SSTL2 Class II is a bidirectional IO standard. > > It has symmetric arrangements of resitors, so that it can be tristate and/or > bidirectional (transmit or receive). > > The DCI version of it in Virtex II and II Pro works just fine, but as has been > pointed out, does dissipate the power inside the chip, as opposed to outside the > chip in external resistors (the power has to be dissipated somewhere). > > How about using LVDCI as the bidirectional interface? Series termination while > driving means low power and no external resistors, and the receive side is fine > while the driver is tristate. > > TANSTAAFL* > > Austin > > *No free lunch, somebody has to match the t-lines. Or to paraphrase another > sci-fi author "Resistance is mandatory!". > > > Bill Blyth wrote: > > > According to the V2 SSTL2 DCI diagrams in DS031.PDF, you can't have just the > > series resistor in a bidirectional pad you must take the parallel > > termination and the subsequent power hit. > > > > I agree series works fine but for bidirectionals using SSTL2 it is not > > possible to use DCI and the resistors have to go on the outside. > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3DECC853.EE5E933F@yahoo.com... > > > Bill Blyth wrote: > > > > > > > > I guess it would be nice to have the DCI single series termination > > without > > > > the power hungry parallel one on receive for SSTL2 class 1 or 2 point to > > > > point data bus solutions - eg. 1 V2 talking to 1 DDR SDRAM bank. > > > > > > > > The V2 and V2 PRO don't support this as far as I know but it would save > > a > > > > large amount of W in the device (especially with a very wide data bus). > > > > Otherwise you are stuck with adding resistor arrays although the poducts > > > > from Calmicro can help reduce board area if you like BGA's. > > > > > > Maybe I am missing something, but since when do you use both series and > > > parallel termination at the same time? Series works fine for point to > > > point and use little power. The parallel form works with a single > > > driver and multiple destinations in a daisy chain and the termination as > > > the last destination. > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX >Article: 50146
You are not clear on what stage you are at in your project and I don't know what the availability situation is, neither do I know anything about the Atmel parts, but you may want to consider using reprogrammable parts such as XC18Vxxx instead of the one time programmable XC17xxx's. Also, depending on where you are in your development you might want to consider using a different method of loading your FPGA., e.g. from a parallel PROM. There are multiple appnotes on the Xilinx website in regards to this issue. /Mikhail "Cristian" <cbustos@yx.cl> wrote in message news:69583e13.0212030616.af701d0@posting.google.com... > Hi, > > I'm currently developing a project with a xc2s300 Xilinx FPGA. Now I > need to purchase the corresponding PROM. It's supposed to be the > xc17S300a. This IC is hard to find in the market. Then I heart about > an Atmel replacement. The AT17LV002. Is this true? Is this a valid > replacement, are there any differences? Looking at the pines and the > signals over time there are some differences but quite small, though. > But even for this PROM, were can I purchase it? > > Finally, are there more/better replacement then these? Were can I find > them. Perhaps it's possible to get a sample. > > Can anybody help me? > > Thanks in advanceArticle: 50147
I need a software such as Xilinx foundation that supports xc4000xl fpga. This should be free, even in a limited version. In this way I can distribute the software to my students and let them exercise at home. The support for xc400xl is important since I own demo board including xc4005xl fpga and spartan fpga. Can you suggest a software? Also a collection of packages (one for synthesys, one for simulation, etc.) could work. Thank you for any suggestion. E. NapoliArticle: 50148
Thomas Buerner wrote: > > Hi > > is it possible to use an old isa vga card connected to an FPGA > for video output? what must be sent over the bus to get it working? A truck-load of register initialises, typically stored in the on-board ROM, within the x86 Boot code. > or is there another - easier - way to get a monitor connected to > my FPGA. > all hints welcome We have a VGA-232, which is a Text Mode ( 640 x 400 ) PCB module. Takes Serial data input, in a similar, but extended, scheme to the old ANSI terminal control codes. See http://www.designtools.co.nz/vga_232.htm If you were planning pictures, or XBOX Grapics, this is not for you :) -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 50149
The two main differentiators I see (beyond the obvious width/depth issues): Distributed RAM is slower than BlockRAM in write speeds (limited by the clock pulse width in the CLB SelectRAM) but the read is faster (limited by Tbcko and routing in the BlockRAM). The routing on BlobkRAMs for Enable and Write Enable signals can be a speed breaker, but the design-around for a trash address location (thanks to Ray Andraka for pointing out the method) can keep the speeds high. Distributed RAMs have combinatorial read while the BlockRAM reads are registered. "longjin" <lchin1@excite.com> wrote in message news:21cf9f42.0212022209.45362d05@posting.google.com... > Does any know the difference between block and distributed RAM in terms > of application and functionality. The question seems trivial but please > enlighten just to verify my doubt. Thanks. > > There is no where to find the difference.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z