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Allan Herriman wrote: > > On Sat, 14 Sep 2002 02:40:51 -0700, "Bruce (newbie)" > <bruce@bytes.co.za> wrote: > > >I am a new comer to VHDL design, and I need to some sort of clock divison scheme that can divide a clock by noninteger values such as 3.33. Not simple values like 1.5,2.5 etc. Can anyone give me some suggestions or ways of achieving this? > > Are the dividers fixed ratio or agile? > > A program that generates fixed ratio dividers in both VHDL and Verilog > can be found at this site: > http://fractional_divider.tripod.com/index.html > > A variable divider is best made with a phase accumulator as Falk > suggested. > > You should be aware that any divider described in synthesisable VHDL > will be a state machine that can only change its output on edges of > the input clock. So your output clock must have jitter if you are > dividing the frequency by a noninteger value. > > This jitter can be as high as one period of the input clock. (Well, I > guess it could be higher if the divider was badly designed.) > > E.g. dividing 1MHz by your example of 3.33 (to give 300.3kHz) will > result in about 990ns p-p of jitter. > > Depending on your jitter budget, this may be too much. There are some > fixes using *analog* electronics (a PLL would work or you could also > try a DDS driving a DAC, followed by a low- or bandpass filter and a > comparator). > > But it isn't possible to make intelligent suggestions until your > requirements are known. Simplest design is a counter than divides by 3, OR divides by 4, such that it AVERAGES 3.33 ( or easier, 3 1/3 ) With more effort, you can use BOTH clock edges, and draw a clock picket line, and toggle the output on the closest edge to 3 1/3 eg Start at 0, whole cycle choices : 1st toggle @ 2 time slot (1 2/3 ideal) 1/3 error 2nd toggle @ 3 time slot (3 1/3 ideal) 1/3 error 3rd toggle @ 5 time slot (5 ideal ) eg Start at 0, half cycle choices : 1st toggle @ 2.5 time slot (1 2/3 ideal) 0.166666 error 2nd toggle @ 3.5 time slot (3 1/3 ideal) 0.166666 3rd toggle @ 5 time slot (5 ideal ) phase error per cycle is halved. You can also look at Rate Multipliers for ideas. -jgArticle: 47026
douglas wrote: > Hello, > > I have a question regarding JTAG ... > > I have 2 Virtex II devices in a JTAG chain. The chain is configured with TDI > of the first device going to TDO of the second device. TMS and TCK go to > both devices in parallel. I am using the 4.2WP3.x version of IMPACT that I > received with the latest WebPack (downloaded yesterday). > > I can successfully configure the first device in the chain. When I do this, > its current consumption is about 700 mA. The problem is that if I configure > the second device then the first device stops working and its current > consumption drops to about 70 mA. It does not matter what the bitfile for > the second one contains. I even made a very basic bitfile which had one > input pin and one output pin, neither of which connect to anything, and > tried to load it. There was no difference. > > I can successfully check the Device ID as well as perform IDCODE looping on > the second FPGA without affecting the first. However, if I try programming > it, then the first one quits. Sounds like a bug in WebPack. It's supposed to put the first device into "BYPASS" mode when programming the second. Can you force it to do that with the jtag set up program? Since it knows that both devices are there, it's mostly working, but it sounds like the instruction for the first device is not being set to BYPASS when you program the second one. Are they similar devices? Can you program them both simultaneously? It may be the only way WebPack knows how to do things, I've not tried more than one device in the chain myself. Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 47027
"Jim Granville" <jim.granville@designtools.co.nz> schrieb im Newsbeitrag news:3D8395F3.6FFC@designtools.co.nz... > Simplest design is a counter than divides by 3, OR divides by 4, > such that it AVERAGES 3.33 ( or easier, 3 1/3 ) Thats it was a DDS does. -- MfG FalkArticle: 47028
Falk Brunner wrote: > > > Sorry if I seem so "insane" about this. I do a lot of planning up front > > where I don't even get to the point of assigning pins until I know a > > design will fit in the part. Often I don't have the option of moving to > > a larger part once I have commited to a given package size and/or > > price. So finding at the design stage that the data sheet was off by 6 > > ?????? > Looks like you have a someway much different way of design than me. At > first, I (try to) design with flexibility in mind. So I choose a FPGA which > is availabe in different sizes for a given package. Gives room for > up/downgrading after design is fully implemented. Makes you (and your design > buddys/leader) have sweet dreams and not to worry too much about FPGA > reaching 101% of its limits. Just recently a colleage had a design in a > XCS30. No more way to change the part. Logic resources usage somewhere to > 85%. This was a hell for P&R, only with heavy LOCing we could make it. Also > I dont design to 100% pin usage. IF you really need this, I do not rely on a > plain number, grabbing the excel pin list is vital there. That is nice if you can get away with it. I often have significant cost constraints. If you read any of the XCR3256XL thread, you would see an example where if I blow the IO count issue in my planning, my only choice at design time is to use a $50 part in the place of a $15 part. So messing up is not an option. > Sure, verification is important. But it should not develop into paranoia, > should'nt it?? ;-)) Where do YOU draw the line. I would rather be overly cautious up front. As they say, "It's only takes ONE 'Oh Damn!' to make up for a whole lot of 'Attaboys'... :) > > "discrepancies" than all the other parts on the board together. When > > was the last time a memory, logic, CPU vendor told you that a new part > > had pin count or assignment errors???? > > Never happend to me, yet. Maybe Iam not long enough in the business (just 2 > years up to now). No, that is the point. The FPGA vendors make a lot more mistakes in the area of IOs, package availability and speed grades than everyone else combined. I guess there is a lot more flux with programmable parts. So verification of chip data can save you a board spin and/or blowing a cost budget. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47029
On Sun, 15 Sep 2002 08:02:59 +1200, Jim Granville <jim.granville@designtools.co.nz> wrote: >Allan Herriman wrote: >> >> On Sat, 14 Sep 2002 02:40:51 -0700, "Bruce (newbie)" >> <bruce@bytes.co.za> wrote: >> >> >I am a new comer to VHDL design, and I need to some sort of clock divison scheme that can divide a clock by noninteger values such as 3.33. Not simple values like 1.5,2.5 etc. Can anyone give me some suggestions or ways of achieving this? >> >> Are the dividers fixed ratio or agile? >> >> A program that generates fixed ratio dividers in both VHDL and Verilog >> can be found at this site: >> http://fractional_divider.tripod.com/index.html >> >> A variable divider is best made with a phase accumulator as Falk >> suggested. >> >> You should be aware that any divider described in synthesisable VHDL >> will be a state machine that can only change its output on edges of >> the input clock. So your output clock must have jitter if you are >> dividing the frequency by a noninteger value. >> >> This jitter can be as high as one period of the input clock. (Well, I >> guess it could be higher if the divider was badly designed.) >> >> E.g. dividing 1MHz by your example of 3.33 (to give 300.3kHz) will >> result in about 990ns p-p of jitter. >> >> Depending on your jitter budget, this may be too much. There are some >> fixes using *analog* electronics (a PLL would work or you could also >> try a DDS driving a DAC, followed by a low- or bandpass filter and a >> comparator). >> >> But it isn't possible to make intelligent suggestions until your >> requirements are known. > >Simplest design is a counter than divides by 3, OR divides by 4, >such that it AVERAGES 3.33 ( or easier, 3 1/3 ) > >With more effort, you can use BOTH clock edges, and draw a clock picket >line, >and toggle the output on the closest edge to 3 1/3 The program I mentioned already does this for one type of divider. So perhaps you could say "With *less* effort, you can use BOTH clock edges". Regards, Allan. >eg Start at 0, whole cycle choices : >1st toggle @ 2 time slot (1 2/3 ideal) 1/3 error >2nd toggle @ 3 time slot (3 1/3 ideal) 1/3 error >3rd toggle @ 5 time slot (5 ideal ) > >eg Start at 0, half cycle choices : >1st toggle @ 2.5 time slot (1 2/3 ideal) 0.166666 error >2nd toggle @ 3.5 time slot (3 1/3 ideal) 0.166666 >3rd toggle @ 5 time slot (5 ideal ) > >phase error per cycle is halved. > >You can also look at Rate Multipliers for ideas. > >-jgArticle: 47030
Dear, Does anybody know the readback size for virtex2 devices? Xilinx App note 138 says only about virtex series, but I coudn't find any documents about readback of virtex2 devices. One more question. Readback methodology of virtex2 is the same with that of virtex/virtex-E? Thank you in advance. -- *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* Young-Su Kwon, Ph. D Student VLSI Systems Lab., KAIST Korea (Republic of Korea) E-mail : yskwon@vslab.kaist.ac.kr *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*Article: 47031
Frankly, board test is better done by taking advantage of the FPGA's
reconfigurability than by inserting boundary scan. Reconfiguration lets you
test the board under worst case conditions without the intended FPGA function
getting in the way (for example, you can run an at-speed memory test that
purposely uses patterns that maximize the bit switching). Please refer to my
paper "An FPGA Based Processor Yields a Real Time High Fidelity Radar
Environment Simulator " which is available on my website at
http://www.andraka.com/files/mapld.pdf which goes into considerable detail in
using FPGAs as part of your board test. Using the methods described in the
paper, we got through system integration in a week on a very complex system (our
part of the design was 2 boards, each with 4 full 4025E's and more than a dozen
FPGA images). Several people told me last week at MAPLD that they had adopted
the methodology I described in that paper with similar success stories.
Boundary scan methods generally can't check interfaces at operating speed, so
problems with signal integrity or timing are not visible. It is fine for
continuity tests, but is little more than a bandaid for modern boards if other
methods are available.
Thomas Stanka wrote:
> Scan insertion is also necessary for runtime bist. In critical systems
> you like to know, when your chip fails. Another point is, that a
> boardlevel test may require boundary scan regardless if you use an
> fpga or an asic.
>
> bye Thomas
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47032"Young-Su Kwon" <yskwon@vslab.kaist.ac.kr> writes: > Does anybody know the readback size for virtex2 devices? > Xilinx App note 138 says only about virtex series, but I coudn't > find any documents about readback of virtex2 devices. > > One more question. > Readback methodology of virtex2 is the same with that of virtex/virtex-E? Both are answered, but in less detail, in: http://www.xilinx.com/publications/products/v2pro/handbook/ug012_ch3.pdf -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domainArticle: 47033
yup, I manually instantiate muxes as you describe. (see risc5x on opencores.org) If I need to go wider than 8, I would cascade muxers with a register in the middle if possible. you could also write out RLOC attributes to guarante the mux components are located in the same slice. Cheers, Mike. "Stephen Williams" <1vntkd4i001@sneakemail.com> wrote in message news:3D82CC0C.1020908@sneakemail.com... > > I'm working on getting the Virtex/EDIF code generator for Icarus Verilog > in line with the improved synthesis of combinational logic, and I'm > worrying myself (probably needlessly) over the implementation of 4:1 > and 8:1 mux devices. > > What I've done so far is emit for 4:1 mux devices two LUT3 and a MUXF5. > This superficially seems pretty optimal, although I can also change it > to generate 2 LUT4 and an XORCY to generate the same function. > > For 8:1 MUX devices, I imagine generating 4 LUT3, 2 MUXF5 and a MUXF6. > This too seems pretty optimal on the surface. > > For 16:1 and wider, I see no alternative to recursively nesting the > right combination of 8:1, 4:1 and 2:1 subnets I've already described. > Gosh, muxes are pretty nasty, I can imagine having nightmares over > the routing problems these create :-/ > > So does all this sound plausible? > -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > steve at picturel.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." > > abuse@xo.com > uce@ftc.gov >Article: 47034
Hi, I am trying to create a custom plug-in for a downstream tool flow using HDL Designer. My new flow is based on the Synplify.pm and Synplify.cfg files that already exist in HDL Designer. The manual pages suggest that I can copy these files, edit the name field in the .cfg file to my new name, and change all instances of the original name in the synplify.pm file to create the new flow. However, after doing this my new flow does not run, giving an error in HDL Designer. Anyone out there done this who can offer some advice? Or alternatively maybe someone who knows Perl could help, since the modules are written in Perl? Thanks, Pete. (reply here, or remove theobvious to reply by email)Article: 47035
Thank you to everybody for helping me with this!! For the questions about me using an obsolet part: You are right, it is not reasonable to be using an XC4k part in these days. But for this only design, its convenient because I have all the tools (Foundation Software, two XC4010XL, etc) available through my university. For a second stage no doubt I will upgrade to another line. Thank you again. Its good to know there are people willing to help others! Mauricio LangeArticle: 47036
I think there is a tool that is part of the jhdl distribution that you mention. It converts edif back into jhdl. This means you can generate your state machine logic in a synthesis tool from vhdl and convert the netlist back to vhdl. Try www.jhdl.org -- Pete Dudley Arroyo Grande Systems "Joeri Vankelst" <swinger667@yahoo.com> wrote in message news:6b28dcff.0207090657.695f05c2@posting.google.com... > Hi, > > I'm not sure if anyone here uses JHDL... > Would it be possible to define a State Machine using JHDL without > having to write the java? What i mean is, is there a tool (like Xilinx > has) you know of I can use to generate JHDL from the states I would > enter. > > I'm also looking for information on the EDIF syntax. Does anyone here > know where I can find a tutorial or white papers? www.edif.org wasn't > very helpfull in providing information on the syntax. > > tnx! > > joeri Vankelst > swinger667@yahoo.comArticle: 47037
Hello All, Before you guys jump all over me I should state up front that I do not want to synthesize any floating point operations. If you want to give the obvious answer that reals don't synthesize you can find that already at this link. http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=3B15A80F.4239026F %40uoguelph.ca&rnum=1&prev=/groups%3Fq%3Dmath_real%2Bgroup:comp.arch.fpga%26 hl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3D3B15A80F.4239026F%2540uoguelph.ca%26rn um%3D1 My question relates to computing the integer values of a look up table by using real operations and rounding to the desired integer values. Something like you would do in matlab or C but I want to do it right in my code to have a single source that's parameterizable for word width and table depth. In other words I want to include a little initialization loop like this. for i in 0 to 255 loop table(i) <= signed(round(64.0*sin(2*pi*i/256))); end loop; What I'm finding is that XST errors out, saying "Undefined symbol 'real'" when I include the math_real library. Can anyone tell me if this is possible in vhdl? I'm starting to think about using a general purpose language for synthesis so little tasks like this are not so trying. See www.jhdl.org for one possibility. -- Pete Dudley Arroyo Grande SystemsArticle: 47038
To Whom It May Concern: I currently work for a Telecommunications company in the Bay Area doing High Speed FPGA design. I'm not sure how much longer my company will be around, so I wanted to see if any company here in the Bay Area could use another designer. =) I would also be willing to do work in more of a Customer Engineering roll, I miss interacting with customers. Please email: fpgadesign2002@yahoo.com if there is interest. No Visa issues (American Citizen), very good written and communication skills. Let's talk more if you're interested! Thanks, -- BradArticle: 47039
Hello, I would like a 1.8V reg in Industrial temp and a three pin surface mount package. I hit the web and found from National Semi : LP3961 it is 1.8V & Ind. Temp. but not 3 pins TI has the TPS77518 in Ind.Temp but it is 8 pin package. Burr Brown has the REG1117A-1.8 in a three pin SM package but it is commercial temp. I searched the Xilinx site and got too many matches on voltage regulators. So what 1.8 V Reg do you use ? Sincerely DanArticle: 47040
Dan wrote: > > Hello, > > I would like a 1.8V reg in Industrial temp and a three pin surface mount > package. > > I hit the web and found from National Semi : LP3961 it is 1.8V & Ind. Temp. > but not 3 pins > > TI has the TPS77518 in Ind.Temp but it is 8 pin package. > > Burr Brown has the REG1117A-1.8 in a three pin SM package but it is > commercial temp. > > I searched the Xilinx site and got too many matches on voltage regulators. > > So what 1.8 V Reg do you use ? I am not sure what your issue is with a 3 pin package. If it is size, then you need to consider the caps required to make the chip stable as well. There are significant differences in the parts and it will make a BIG difference in the total board space used. Some parts will work with 1 or 2 uF ceramic caps which you can get in an 0603 package. Others require tantalum caps due to the higher ESR. These parts come in sizes closer to 1206 and will nearly double the size of your LDO to use one on input and output. So an 8 pin MSOP with two 0603 ceramic caps may be as small as a SOT-23 with the tantalum parts, and may work better and be cheaper as well. BTW, check TI again, I am pretty sure they have a SOT-23 LDO that is industrial temp. It may be a 5 pin version though if that will work. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47041
You'll also want to watch your power dissipation with a linear regulator. It
doesn't take much to get several watts dissipation in the FPGA, and if your
regulator is sourced off a 5v supply it will dissipate twice what the FPGA does.
Much depends on the FPGA device too, if this is a 2000E, the linear regulator is
probably not sufficient. If it is a 50E, it is most likely OK.
rickman wrote:
> Dan wrote:
> >
> > Hello,
> >
> > I would like a 1.8V reg in Industrial temp and a three pin surface mount
> > package.
> >
> > I hit the web and found from National Semi : LP3961 it is 1.8V & Ind. Temp.
> > but not 3 pins
> >
> > TI has the TPS77518 in Ind.Temp but it is 8 pin package.
> >
> > Burr Brown has the REG1117A-1.8 in a three pin SM package but it is
> > commercial temp.
> >
> > I searched the Xilinx site and got too many matches on voltage regulators.
> >
> > So what 1.8 V Reg do you use ?
>
> I am not sure what your issue is with a 3 pin package. If it is size,
> then you need to consider the caps required to make the chip stable as
> well. There are significant differences in the parts and it will make a
> BIG difference in the total board space used. Some parts will work with
> 1 or 2 uF ceramic caps which you can get in an 0603 package. Others
> require tantalum caps due to the higher ESR. These parts come in sizes
> closer to 1206 and will nearly double the size of your LDO to use one on
> input and output.
>
> So an 8 pin MSOP with two 0603 ceramic caps may be as small as a SOT-23
> with the tantalum parts, and may work better and be cheaper as well.
>
> BTW, check TI again, I am pretty sure they have a SOT-23 LDO that is
> industrial temp. It may be a 5 pin version though if that will work.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47042
I presume you are referring to a 2D FFT. What resolution? Yes it can be done
real time if you throw enough hardware at it, even for a 1Kx1K image. We did a
block floating point point FFT design recently that does a 4K FFT in 68us
(which is slightly more than an NTSC line time) using the QPRO (radiation
tolerant) version of the XCV1000-4 clocked at 100 MHz. That design uses about
45% of the CLBs, but requires the V1000 for the memory. A similar design
should handle two simultaneous 1K block floating point FFTs in that device
using our cores. Where you are doing video, you may not need the precision nor
the block floating point either, which would reduce the size considerably.
lng wrote:
> I would like to know if anyone do FFT filter for NTSC or PAL in real time?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47043Pete Dudley wrote: > My question relates to computing the integer values of a look up table by > using real operations and rounding to the desired integer values. Something > like you would do in matlab or C but I want to do it right in my code to > have a single source that's parameterizable for word width and table depth. > In other words I want to > include a little initialization loop like this. > > for i in 0 to 255 loop > table(i) <= signed(round(64.0*sin(2*pi*i/256))); > end loop; > I had a similar problem, in an even simpler context. I was trying to do things like this: constant scale : integer := 2**field_width; -- field_width is a generic constant threshold : real := 0.83; constant int_thresh : integer := threshold * scale; or have my thresholds passed at synthesis time as generics. Simply couldn't get it to synthesise, even though the integer constant could be resolved as synthesis time. I ended up with a couple of work-arounds. For scaled integer constants like that above I used constant int_thresh : integer := (55307 * scale) / 65536; which worked reasonably well. For lookup tables I wrote Matlab programs to generate VHDL constant arrays which I included as modules in my design. Hope this is useful. Regards, JohnArticle: 47044
Use the delay lock loops. A primary reason that they are there is to reduce the
tco's. Also, our designs are generally clocked faster inside than at the I/O to
take advantage of extra clock cycles to reduce the size of the design.
Paul Baxter wrote:
> > Are you sure that all outputs are registered AND those registers are place
> > inside the IOBs??
>
> I guess that was why I said 'what irks me'
>
> It must not be putting the registers on the IOBs or the global clock is
> hugely delayed around the device.
>
> I assumed that with no pre-existing assignments Quartus 2 PAR would put the
> final registers on the IOBs.
>
> I'm now wondering because a lot of these outputs are from a ROM-based state
> machine (Thanks Peter Alfke for reminding me of the technique) but if it
> uses the ESB registered outputs and then routes to a latchless IOB that
> could be causing it.... Thanks for jogging my memory. I think I'll put an
> extra pipeline stage on my outputs to be sure.
>
> In essence my question still stands. An Fmax figure is meaningless if the
> Tco (or indeed Tsetup/hold) are excessive. Its OK for some types of
> inputs/outputs but not for those needing to be operating at full speed in a
> synchronous system.
>
> I just evaluated an SDRAM core which claimed 88MHz + but has Tco's up at 15
> ns for the SDRAM interface. I'm now running into similar issues in my own
> design and I think Tco's that high are a big show stopper, but I'm asking if
> I'm right or not.
>
> Paul Baxter
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47045
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That is not currently part of the LRM, although I wish it were. The work around
is to use something else to generate the constants. For small fixed tables, we
use a spreadsheet (Excel), then cut and paste the column into the VHDL code.
For tables that are dependent on the generics, it is easier to write a C program
that in turn generates a package containing all the constants and tables needed
(basically print text to a file).
Pete Dudley wrote:
> Hello All,
>
> Before you guys jump all over me I should state up front that I do not want
> to synthesize any floating point operations. If you want to give the obvious
> answer that reals don't synthesize you can find that already at this link.
> http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=3B15A80F.4239026F
> %40uoguelph.ca&rnum=1&prev=/groups%3Fq%3Dmath_real%2Bgroup:comp.arch.fpga%26
> hl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3D3B15A80F.4239026F%2540uoguelph.ca%26rn
> um%3D1
>
> My question relates to computing the integer values of a look up table by
> using real operations and rounding to the desired integer values. Something
> like you would do in matlab or C but I want to do it right in my code to
> have a single source that's parameterizable for word width and table depth.
> In other words I want to
> include a little initialization loop like this.
>
> for i in 0 to 255 loop
> table(i) <= signed(round(64.0*sin(2*pi*i/256)));
> end loop;
>
> What I'm finding is that XST errors out, saying "Undefined symbol 'real'"
> when I include the math_real library.
>
> Can anyone tell me if this is possible in vhdl?
>
> I'm starting to think about using a general purpose language for synthesis
> so little tasks like this are not so trying. See www.jhdl.org for one
> possibility.
>
> --
> Pete Dudley
>
> Arroyo Grande Systems
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47046- and don't forget the 'wake-up' current, - check the peak Io of the 3 pin SMD regulator ( SOT23?), with the peak startup value of the FPGA..... - jg Ray Andraka wrote: > > You'll also want to watch your power dissipation with a linear regulator. It > doesn't take much to get several watts dissipation in the FPGA, and if your > regulator is sourced off a 5v supply it will dissipate twice what the FPGA does. > Much depends on the FPGA device too, if this is a 2000E, the linear regulator is > probably not sufficient. If it is a 50E, it is most likely OK. > > rickman wrote: > > > Dan wrote: > > > > > > Hello, > > > > > > I would like a 1.8V reg in Industrial temp and a three pin surface mount > > > package. > > > > > > I hit the web and found from National Semi : LP3961 it is 1.8V & Ind. Temp. > > > but not 3 pins > > > > > > TI has the TPS77518 in Ind.Temp but it is 8 pin package. > > > > > > Burr Brown has the REG1117A-1.8 in a three pin SM package but it is > > > commercial temp. > > > > > > I searched the Xilinx site and got too many matches on voltage regulators. > > > > > > So what 1.8 V Reg do you use ? > > > > I am not sure what your issue is with a 3 pin package. If it is size, > > then you need to consider the caps required to make the chip stable as > > well. There are significant differences in the parts and it will make a > > BIG difference in the total board space used. Some parts will work with > > 1 or 2 uF ceramic caps which you can get in an 0603 package. Others > > require tantalum caps due to the higher ESR. These parts come in sizes > > closer to 1206 and will nearly double the size of your LDO to use one on > > input and output. > > > > So an 8 pin MSOP with two 0603 ceramic caps may be as small as a SOT-23 > > with the tantalum parts, and may work better and be cheaper as well. > > > > BTW, check TI again, I am pretty sure they have a SOT-23 LDO that is > > industrial temp. It may be a 5 pin version though if that will work.Article: 47047
On Fri, 13 Sep 2002, Peter Alfke wrote: > Let me discourage you from trying to use metastability to generate random > numbers. Metastability is an extremely fast phenomenon, and I do not see how > you can achieve true randomness ( equal probability of any 1-0 sequence, and > equal number of 0s and 1s. > What is you purpose? > Linear Feedback Shift Registers (LFSRs) can substitute for random number > generators in many, but not all, cases > > Peter Alfke, Xilinx > =================== I do not need an equal distribution of 1's and 0's. Even a ratio of 1:1000 is good. I can get anything with further processing in FPGA or CPU. What I would like to achieve is that it has to be non-deterministic. When I have 1000 identical devices and turn them on, they should generate different non-predictable sequences. It is good even if the sequences differ in 10000th bit. -- -- Wojciech Piechowski - wpiechowski@acm.org - Gadu-Gadu 494156 --Article: 47048
On Fri, 13 Sep 2002, rickman wrote: > Wojciech Piechowski wrote: > > > > hello! > > > > I've just read an interesting thread about metastability and this made me > > think about making a hardware random bit generator. Exploiting > > metastability seems to be interesting. Just put to D an alternating > > sequence which toggles with clock. Add some smart routing to make it hit > > the hold window. And have a long time thinking how to read metastable Q > > without passing metastability to the rest of the circuit.... > > > > Has anyone done something like this? Or heard about it? I'm thinking about > > implementing it. Any help and comments appreciated. > > Resolving the metastable state in another FF stage or two would not be a > problem. That is what is going on in a cross clock domain synchonizer. > The first FF can not be made stable and always has a chance of becoming > metastable. But the following stages have a much, much reduced chance > of being metastable. > This is useful when you synchronize unrelated signals. Then you have some little probability of a metastate in the 1st FF and a very very little probability that this FF would put the next FF into the metastate. But we intentionally want a meta. Even a million times in a second (very optimistic, but who cares :)). Probability of getting a meta in the next stage is much greater than "once per 1000 years". It cannot be ignored. A series of FF's may help, but still no guarantees. The solution may be to wait long enough to be sure that Q is stable and then read it. > But, to have a *useful* random number generator, the values must have > certain properties. One of them is that the distibution must be even. > If you are generating a stream of 1s and 0s, then you must have half 1s > and half 0s. [...] I don't require an equal distribution. Take a look into my answer to Peter. -- -- Wojciech Piechowski - wpiechowski@acm.org - Gadu-Gadu 494156 --Article: 47049
Hi Pete, I'm facing to write my own plug-in, therefore I'm interested in this topic. But you should provide some error messages. Furthermore I have some Perl experience. Pete H. schrieb: > Hi, > I am trying to create a custom plug-in for a downstream tool flow using= HDL > Designer. > My new flow is based on the Synplify.pm and Synplify.cfg files that alr= eady > exist in HDL Designer. > The manual pages suggest that I can copy these files, edit the name fie= ld in > the .cfg file to my new name, and change all instances of the original = name > in the synplify.pm file to create the new flow. However, after doing th= is my Perl expects an upper-case letter as the first letter for a package. > new flow does not run, giving an error in HDL Designer. Does the Synplify-plug-in run? Bye Tom! -- Thomas Reinemann www.uni-magdeburg.de/reineman IMAT Public key available Otto-von-Guericke-Universit=E4t Magdeburg Universit=E4tsplatz 2 39106 Magdeburg, Germany
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