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doug wrote: (snip) >> I think my choice would be to write in verilog, and then use >> a verilog to schematic conversion program. They aren't >> perfect, but maybe good enough. > Do you have any good examples. The ISE translations > are mostly useless. I only tried the ISE conversion once, and only figured out how to do the top level. That wasn't a good test, though. Some years ago I used one with Compass design software (though not from verilog source). That one wasn't so bad for the designs I was doing at the time, though it could have been improved. >> If the verilog is appropriately >> modular, then the schematic for each module isn't too complicated. > It is probably easier to have the program make verilog > from schematics and then we know the schematics are readable. Most of the time I find it easier to write verilog than enter the schematic, but yes that probably results in a more readable schematic. If you make many changes to the design, though, the result is often not so good. >>> One argument is that HDLs are more portable and that is >>> true but it is of more importance to people who move >>> between chips more often. I have been using Xilinx chips >>> since 1991 so I am pretty old and slow to change my ways. >> Yes, but Xilinx changes the families often enough that it >> might just as well be different. > They also have changed the software a lot. (snip) -- glenArticle: 138601
Hello, I am a final year student in electronics engineering and am doing my final year project in FPGA spartan 3E starter kit. I need to have a character generator ROM along with VGA controller core. Could anyone help me with this. I need to read characters from the character ROM and display them on the VGA monitor. Please helpArticle: 138602
Vesh wrote: > I am a final year student in electronics engineering and am doing my > final year project in FPGA spartan 3E starter kit. I need to have a > character generator ROM along with VGA controller core. Could anyone > help me with this. I need to read characters from the character ROM > and display them on the VGA monitor. Please help You mean you need the ROM image, or the whole character generator logic. ROM images are available, but then with some graph paper you can make your own. http://www.slac.stanford.edu/cgi-wrap/getdoc/slac-r-199.pdf has a design for a display terminal including a character generator. It generates NTSC timing, but it shouldn't be hard to modify for VGA timing. -- glenArticle: 138603
Hi all: I generated edf file and use it as source file for quartus, the analysis and fitter are successful, but when I run timequest, it report error as below: Error: Can't write to database file /**.tiscmp.slow_900mv_0c.ddb. Database error: Disk quota exceede what cause this problem and how to solve it? thank you very much for your comments.Article: 138604
Allan Herriman wrote:
> 1. Is my take on the future of PCIe right? Will it become the only high
> speed interface in future mid- or high-level embedded CPUs?
PCIe is the ticket for any card that needs
data from the internet or a hard drive.
For rack equipment, buy a server off the shelf
and make a PCIe card.
> 2. Will future generations FPGAs be able to be programmed via PCIe? If
> so, when?
It will be built-in on big fpgas.
> 3. Is there a better way of configuring a current generation (e.g. V5 or
> V6) FPGA than via a bridge chip?
If the interface is built-in and cheap enough, maybe.
-- Mike
Article: 138605
-jg wrote:
> On Mar 1, 9:38 pm, "dracosilv" <dracosil...@wi.rr.com> wrote:
>>
>> I wish I could find a simple, yet free graphical CPLD development
>> program, since right now, I don't know enough about any HDL language
>> (VHDL/Verilog HDL) yet.
>
> Xilinx tool flows still support ABEL (I think)
> - that's an intermediate HDL, that is more suited to smaller designs.
> Lattice also have ABEL, and Atmel have the similar CUPL.
>
> Such Boolean Entry languages have a simple, easy to learn syntax :
>
> They are also MUCH more stable and portable, than Schematic Entry,
> but close to the wire-level design model.
>
> Reg.ck = ClockPin;
> Reg.D = !Reg;
> Reg.CE = EnablePin;
>
> Reg2.T = Reg1 & Reg0;
>
> etc...
> The fitter reports usually report in Boolean Egn format, and some can
> switch to VHDL
> so you can learn from that too.
>
> -jg
I think I'm going to go with Verilog or VHDL (not 100% sure which yet, but
probably VHDL), since the logic seems pretty simple.
I mean this is (most of) the the code for 4 buffers with active high
enables:
<CODE>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BUFE4 is
port(
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
E : in std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end BUFE4;
architecture BUFE4_V of BUFE4 is
begin
process (I0, I1, I2, I3, E)
begin
if (E='1') then
O0 <= I0;
O1 <= I1;
O2 <= I2;
O3 <= I3;
else
O0 <= 'Z';
O1 <= 'Z';
O2 <= 'Z';
O3 <= 'Z';
end if;
end process;
end BUFE4_V;
</CODE>
Article: 138606srikanthv2 wrote: > 1. FPGA programming (all boards use standard Xilinx/Altera FPGAs. so > this is not a problem) > 2. Software interface on the PC - to not only program the FPGA but > also to talk to the FPGA after programming. (I presume the vendors > will provide this, I am concerned about the availability of the source > code in case I want to modify this to suit my custom board) > 3. USB controller firmware (Again, will I need to edit the firmware? You might take a look at the Demand Peripherals Baseboard. It has a Spartan 3E tied to an FTDI-245 USB-serial part. You can download the bitfile over the USB link and then the USB is available for application data transfers. HTH Bob SmithArticle: 138607
On Mar 2, 4:56=A0am, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Vesh wrote: > > I am a final year student in electronics engineering and am doing my > > final year project in FPGA spartan 3E starter kit. I need to have a > > character generator ROM along with VGA controller core. Could anyone > > help me with this. I need to read characters from the character ROM > > and display them on the VGA monitor. Please help > > You mean you need the ROM image, or the whole character > generator logic. =A0ROM images are available, but then with some > graph paper you can make your own. > > http://www.slac.stanford.edu/cgi-wrap/getdoc/slac-r-199.pdf > > has a design for a display terminal including a character > generator. =A0It generates NTSC timing, but it shouldn't be > hard to modify for VGA timing. > > -- glen Glen 5 ***** award to you for the best reply to "please do my homework begger" question. a scanned document from 1976 :) great reading... AnttiArticle: 138608
On Mar 2, 7:17=A0am, Bob Smith <use...@linuxtoys.org> wrote: > srikanthv2 wrote: > > 1. FPGA programming (all boards use standard Xilinx/Altera FPGAs. so > > this is not a problem) > > 2. Software interface on the PC - to not only program the FPGA but > > also to talk to the FPGA after programming. (I presume the vendors > > will provide this, I am concerned about the availability of the source > > code in case I want to =A0modify this to suit my custom board) > > 3. USB controller firmware (Again, will I need to edit the firmware? > > You might take a look at the Demand Peripherals Baseboard. > It has a Spartan 3E tied to an FTDI-245 USB-serial part. > You can download the bitfile over the USB link and then > the USB is available for application data transfers. > > HTH > Bob Smith your forgot the advertizement url ;) google finds this first http://sourceforge.net/projects/periphondemand/ but this isnt your product what is here http://www.demandperipherals.com/ AnttiArticle: 138609
Antti.Lukats@googlemail.com wrote: (snip) > 5 ***** award to you for the best reply to "please do my homework > begger" question. > a scanned document from 1976 :) I am not so sure what he was asking, but it is a pretty nice machine. Implementing one in an FPGA might be a good project for many courses. I believe it uses a commercial ROM for the character generator, but the data sheet is probably available. I am not sure if the software is, though. It makes a pretty nice terminal, even compared to ones produced much later. In text mode there is a scroll wheel on the side. Rotating it moves the text image up and down in scan line (or maybe line pair) increments. It has enough inertia that one can start it, then stop it at the desired position. In addition to the ROM character generator there is a loadable RAM character generator, and the ROM is addressable by the processor. I used to have a program that would read the ROM, mirror each row, then write to RAM. Activating the RAM mirrors all the characters on the screen. Also, it has a graphics mode that uses the whole display memory for bitmap graphics with Tektronix 4013 emulation, though that isn't so unusual now. -- glenArticle: 138610
rickman wrote: > interfaces rather than using a small number of GPIO pins. That is a > tradeoff with those chips. But you are asking everyone buying FPGAs > to pay for the Silicon to implement the hard PCIe interface and make > it part of the configuration logic. On top of that, I am still not The PCIe core is there in many of the new or upcoming FPGAs so that would not be extra logic. The logic needed to connect the core to configuration logic would be very small. If done via configuration space it would be few hundred gates extra. > convinced that this can be done without some data in Flash which > someone else pointed out is required for initilization of the PCI > interface. Is this not the same with PCIe? They way I read the standards it would not need any flash etc. The vendor would just have to use their own PCI code for the endpoint during configuration, and after configuration all the data would come from the image. Only thing needed would be the selection of configuration mode, that is already now done via external pins. > And how does the FPGA get the various parameters which the PCI > protocol requires the FPGA to report? To what parameters do you refer? I can't think of any, for configuration mode the core could have hardcoded values. >> immediatly answer to the bus even if the FPGA is not loaded. If the >> PCI configuration space would then have extended configuration register >> that could be used to bang the data in via configuration cycles. Or >> other option would be one hardcoded PCI BAR for the configuration image. >> Memory mapped configuration image also might create some pretty >> interesting opportunities for dynamic reconfiguration. > > So is this an extension to just to the FPGA or also to the PCI > protocol? Just extension to the FPGA hardcore, and how boot is done. In embedded applications the implementor has full access usually to the boot process. > So how much additional work is required? I can assure you that if > there were any significant number of users asking for something like > this, it would appear. At least I have asked for this from the vendors, I hope they would implement it also ;) >>> I seem to recall that there was support for a JTAG or some other >>> serial interface on PCI, but it has been so long that I don't recall. >> I think you are referring to SMBus. It is I2C style slow (10kHz-100kHz) >> interface. I think it would be too slow for FPGA configuration. > > Is that part of the PCI spec? I just remember that when I looked at > PC/104+ and PCI/104 that they explicitly left out some serial control > bus that I thought was JTAG. I don't remember it being SMBus which is It is part of PCI LB 3.0, check chapter 8. It's not part of the 2.2 version. --KimArticle: 138611
>They way I read the standards it would not need any flash etc. The >vendor would just have to use their own PCI code for the endpoint during >configuration, and after configuration all the data would come from >the image. Only thing needed would be the selection of configuration >mode, that is already now done via external pins. I think you need a tiny external ROM, or at least that is what the specs expect and what I think will be the easiest way to make a sensible system. Without that code, you can't tell what sort of device it is so you can't hand it off to the right driver to load the right FPGA code. (You don't even know there is an FPGA to be loaded.) It might have some default device/manufacturer codes. If so, that will work as long as you only have one of them in the system. I'd do that for a one-off lab hack, but you can't sell (m)any of them. Things will break as soon as two of you do that, or only one of you if you have new and old boards. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 138612
>I am not so sure what he was asking, but it is a pretty >nice machine. Implementing one in an FPGA might be a good >project for many courses. I believe it uses a commercial >ROM for the character generator, but the data sheet is probably >available. I am not sure if the software is, though. I remember in the early 70s when my roommate came home smiling and showed me a data sheet for a new part that was a character generator ROM. In 1965 or '66, working on a PDP-7 that implemented that ROM with cores. They were big enough so that you could get a lot (64?) of wires through them even when the wires were big enough to thread by hand. I think they filled up a drawer. We rewired a few of them to get some special characters. If I wanted the contents for a ROM like that, I'd make it from the fonts on my PC. Pick one I like. I don't know if it would be easier to decode whatever font format file the system uses or take a picture of my screen and decode the camera format. Graph paper would be fun too, at least for the first few characters. I was actually thinking that it would be fun to make an old fashoned character display with a twist. Use variable width fonts. :) -- These are my opinions, not necessarily my employer's. I hate spam.Article: 138613
On Mar 2, 2:03 am, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > rickman wrote: > > interfaces rather than using a small number of GPIO pins. That is a > > tradeoff with those chips. But you are asking everyone buying FPGAs > > to pay for the Silicon to implement the hard PCIe interface and make > > it part of the configuration logic. On top of that, I am still not > > The PCIe core is there in many of the new or upcoming FPGAs so > that would not be extra logic. The logic needed to connect the core > to configuration logic would be very small. If done via configuration > space it would be few hundred gates extra. You are just talking about the gates, there is a whole can of worms associated with documentation, support and training. I am confident that configuring over PCIe is a lot more complex than you are making it out to be. > > convinced that this can be done without some data in Flash which > > someone else pointed out is required for initilization of the PCI > > interface. Is this not the same with PCIe? > > They way I read the standards it would not need any flash etc. The > vendor would just have to use their own PCI code for the endpoint during > configuration, and after configuration all the data would come from > the image. Only thing needed would be the selection of configuration > mode, that is already now done via external pins. What if you have more than one in the system? How are they distinguished? I remember several different parameters that have to be returned by the hardware before the slave can be controlled. > > And how does the FPGA get the various parameters which the PCI > > protocol requires the FPGA to report? > > To what parameters do you refer? I can't think of any, for configuration > mode the core could have hardcoded values. Yes, but you are simplifying the issue. If you are creating a PCI device, it has to be identifiable at boot time. For an FPGA this is especially true because you have to know which bit file to send it. In the simple case of one FPGA this may not be an issue, but the FPGA vendor has to consider the general case. > >> immediatly answer to the bus even if the FPGA is not loaded. If the > >> PCI configuration space would then have extended configuration register > >> that could be used to bang the data in via configuration cycles. Or > >> other option would be one hardcoded PCI BAR for the configuration image. > >> Memory mapped configuration image also might create some pretty > >> interesting opportunities for dynamic reconfiguration. > > > So is this an extension to just to the FPGA or also to the PCI > > protocol? > > Just extension to the FPGA hardcore, and how boot is done. In embedded > applications the implementor has full access usually to the boot > process. > > > So how much additional work is required? I can assure you that if > > there were any significant number of users asking for something like > > this, it would appear. > > At least I have asked for this from the vendors, I hope they would > implement it also ;) > > >>> I seem to recall that there was support for a JTAG or some other > >>> serial interface on PCI, but it has been so long that I don't recall. > >> I think you are referring to SMBus. It is I2C style slow (10kHz-100kHz) > >> interface. I think it would be too slow for FPGA configuration. > > > Is that part of the PCI spec? I just remember that when I looked at > > PC/104+ and PCI/104 that they explicitly left out some serial control > > bus that I thought was JTAG. I don't remember it being SMBus which is > > It is part of PCI LB 3.0, check chapter 8. It's not part of the 2.2 > version. I looked it up and the PCI104 spec refers to JTAG signals from the PCI bus not being supported on PIC104. Of course, this is not part of PCIe I expect. RickArticle: 138614
Hal Murray wrote: (snip) > If I wanted the contents for a ROM like that, I'd make it > from the fonts on my PC. Pick one I like. I don't know > if it would be easier to decode whatever font format file > the system uses or take a picture of my screen and decode > the camera format. Graph paper would be fun too, at least > for the first few characters. I have somewhere the data sheet for the CG in the SOL computer, which is an interesting ROM. The characters are in a 7 by 9 matrix, but can be shifted down for some characters. So the storage array is 64 bits per character, and 128 characters. The character cell is 12 rows. It fits nicely into a 2716, as 16 rows of 8 bits by 128 characters. It might be the same one used in the VGT. > I was actually thinking that it would be fun to make an > old fashoned character display with a twist. Use variable > width fonts. :) I suppose it isn't so hard. You need a ROM of width for each character, and increment a counter appropriately. Not so good for editing program text, though. -- glenArticle: 138615
randy wrote: > Hi all: > I generated edf file and use it as source file for quartus, the > analysis and fitter are successful, but when I run timequest, it > report error as below: > Error: Can't write to database file /**.tiscmp.slow_900mv_0c.ddb. > Database error: Disk quota exceede > what cause this problem and how to solve it? thank you very much for > your comments. You've run out of disk space, either because there's no space left, or because your adminstrator has limited the disk space, called a "quota", regards Alan -- Alan Fitch Doulos http://www.doulos.comArticle: 138616
dracosilv wrote: > > I think I'm going to go with Verilog or VHDL (not 100% sure which yet, but > probably VHDL), since the logic seems pretty simple. I wonder what drives you towards VHDL - not to start a religious war here. The same functionality can look like module BUFF4(input e, input [3:0] I, output [3:0] O); assign O = (e == 1) ? I : 4'bz; endmodule -Alex.Article: 138617
Hal Murray wrote: > Without that code, you can't tell what sort of device it is so > you can't hand it off to the right driver to load the right > FPGA code. (You don't even know there is an FPGA to be loaded.) > > It might have some default device/manufacturer codes. If so, > that will work as long as you only have one of them in the system. The vendor would just have to allocate unique device-id for each chip type and use their own vendor-id. If there are many FPGAs my understanding is that with PCIe and P-to-P connections the topology is unique and the chips can be identified from the PCI topology. Same problem applies when there are multiple identical PCIe cards on the system. --KimArticle: 138618
Hi Can any1 tell me how to use an ODDR output to internal logic in XIlinx FPGAs...???? Is there any other way to serialize Double data rate signals in Xilinx FPGAs...???Article: 138619
"Vesh" <veshrajsharma@gmail.com> wrote in message
news:e2bb9d65-f5f5-4367-9947-772f317c7e7c@a5g2000pre.googlegroups.com...
> Hello,
> I am a final year student in electronics engineering and am doing my
> final year project in FPGA spartan 3E starter kit. I need to have a
> character generator ROM along with VGA controller core. Could anyone
> help me with this. I need to read characters from the character ROM
> and display them on the VGA monitor. Please help
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Article: 138620On 1 Mrz., 10:27, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > the time goes faster and faster each month :( > so there is less time to write magazine content > still the february issue is released with less > delay then last few issuehttp://groups.google.com/group/antti-brain/files?hl=en > > Antti Hi Antti, In Issue6 there'ssomething missing in your FCU comparision table: The PicoBlaze has Carry and ZERO flags too. Regards EilertArticle: 138621
"knight" <krsheshu@gmail.com> wrote in message news:f783afda-54f7-434f-9c00-9a0a8b162339@p6g2000pre.googlegroups.com... > > Hi > > Can any1 tell me how to use an ODDR output to internal logic in XIlinx > FPGAs...???? > Yes...Instantiate an IBUF... > Is there any other way to serialize Double data rate signals in Xilinx > FPGAs...??? > Yes...Use the fabric...Flipflops and gates... What are you trying to do? There's almost certainly a better way to achieve what you want than reading back the ODDR output. Cheers, Syms.Article: 138622
Hi, I'm changing from Xilinx to Altera and sometimes confused by Altera products. Now I'm trying to instantiate PCIE with SOPC Builder. The spec states there will be an Avalon-MM interface, but I can only find a TX interface in SOPC. Can anybody help me to understand this TX interface with Avalon-MM? thanks CYArticle: 138623
On Mar 2, 5:12 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "knight" <krshe...@gmail.com> wrote in message > > news:f783afda-54f7-434f-9c00-9a0a8b162339@p6g2000pre.googlegroups.com... > > > > > Hi > > > Can any1 tell me how to use an ODDR output to internal logic in XIlinx > > FPGAs...???? > > Yes...Instantiate an IBUF... > > > Is there any other way to serialize Double data rate signals in Xilinx > > FPGAs...??? > > Yes...Use the fabric...Flipflops and gates... > > What are you trying to do? There's almost certainly a better way to achieve > what you want than reading back the ODDR output. > > Cheers, Syms. Hi thanks a lot for the reply... But how can i instantiate an IBUF to get back an ODDR output...??? won't it require a hardware loopback...???Article: 138624
"Antti" <Antti.Lukats@googlemail.com> schrieb im Newsbeitrag news:aa5543a8-788e-42e0-b8dd-26549970042a@t7g2000yqa.googlegroups.com... > Hi > > the time goes faster and faster each month :( > so there is less time to write magazine content > still the february issue is released with less > delay then last few issue > http://groups.google.com/group/antti-brain/files?hl=en > > > Antti Thams Antti for promoting my new products, however the small modules are design studies only, but the new OHO_DY1 display module (which can be staggered) will be available soon. MIKE www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 mr@oho-elektronik.de Usst.ID: DE130097310
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