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Austin wrote: > > I don't know about anyone else, but it works fine, and posts > like this of sims poorly done are not helpful to anyone. > Well, there's another apology that you owe me. I'll add it to your tab. Quickly done, yes. Inexpensively done, sure. Unverified, yes, but clearly labeled as such. > > Anyone want my screenshot can email me directly, as posting big graphis > files is bad newsgroup behavior (and is blocked). > How about you put your money where your mouth is and go ahead and show us all your IBIS sim model, assumptions, and nodes plotted. What, you don't know how to upload a file and post a link? Tell you what, instead of you breaking out into a sweat, just go ahead and answer my question from last year [1]: "Where in Xilinx's V4 documentation might one find these pictures and eye diagrams, including real world vs. simulated waveforms at the driver, receiver, and points in between ? " and post us a link to any Xilinx app note for V4 that shows nodes along the entire net using a fast LVDS/PECL/CML driver with less than ideal back termination. Brian [1] http://groups.google.com/group/comp.arch.fpga/msg/3619e923a589ef59Article: 98076
John,
>
>Good SI analysis is so critical these days; it's nice to see
>someone else's results.
>
I wouldn't consider those "results" yet, more of a "preliminary model".
But I have used those attenuators in several real-world designs.
I have also done similar models in the past, and after a round
of lab verification, additions, and tweaking, they worked far
better than the Xilinx IBIS LVDS models/Hyperlynx of the time.
And just try modeling SSO, noise injection from DCI modulation,
and other such beasties with your typical combination of IBIS
model/simulator versions and feature support.
>
>Is the ADS5273 a non-standard LVDS "style" of driver?
>
The appellation "LVDS" has been applied to many parts
that swing to LVDS levels into a 100 ohm load, but don't
have the expected back termination or driver design.
IIRC, 40-140 ohm Rdiff was expected in one of the
early LVDS standards.
Unless I'm misinterpreting the ADS5273 datasheet,
the part is NOT back terminated:
Differential Output Impedance : 13 kohm
"The single-ended output impedance of the LVDS
drivers is very high because they are current-source
driven. If there are excessive reflections from the
receiver, it might be necessary to place a 100 ohm
termination resistor across the outputs of the LVDS
drivers to minimize the effect of reflections."
>
>The lack of back termination that you included in the
>"normal" LVDS driver makes me wonder if the greater problem
>is with the ADS5273 rather than the non-ideal FPGA input.
>
As I suggested in the 527x thread, I suspect TI
intentionally avoided the internal back termination
to avoid coupling the unpredictable and ugly reflections
off your typical FPGA input back into the analog stuff.
The reflection arrival time is not under the control
of the A/D chip designer, unlike the internal sequencing
of the front end sampler and output driver switching,
and the incoming reflections might hit say 50-60% of the
original output step amplitude.
>
>A technique used in telecomm systems that might be helpful for probing:
>rather than using a large attenuator between Rx and Tx with the raw probe
>point somewhere along the transmission line, consider using a
>reduced-amplitude probe point.
>
Good point, I didn't mention probes or probe loading models.
I'll try to keep a list of things to add to that document.
At 840 Mbps, a decent active or Zo probe should work fine.
I did have some notes on probing in one of the reference links;
I've copied them below.
I've also used broadband resistive couplers and power splitters
for really fast stuff like OC192.
If only this were microwave, I could break out the directional
couplers and isolators :)
Brian
>From [Ref 2]
http://groups.google.com/group/comp.arch.fpga/msg/a044806f313848e6
Also, in most high speed systems, there is a need to monitor
the link in some fashion, either as part of a system jitter/skew
or setup/hold verification, or perhaps a non-intrusive signal
tap for operational monitoring.
This is often done by placing a passive resistive coupler
in-line with the signal, or perhaps probe pads for one of the
low-loading differential active probes.
If the tap is placed close to the highly capacitive receiver
input, the ringback can leave the differential signal in limbo
at the probe point ( both inputs within the differential Vih/Vil
hysteresis switching threshold ) until the reflected pulse has
passed; if you place it farther up the line, the reflection can
re-clock the probe, or interfere with the next incoming bit.
Article: 98077For this word length table lookup is much better, than CORDIC and power series. http://en.wikipedia.org/wiki/CORDICArticle: 98078
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1141400003.663570.191020@i40g2000cwc.googlegroups.com... > yes > May I use the "configuration memory port" on the baseboard to write into atmel memory?Article: 98079
sorry about the vagueness of my project. here's what we are doing. ive posted it up before on this forum. http://classes.engr.oregonstate.edu/eecs/fall2005/ece441/groups/g1/skematic.htmArticle: 98080
I have bought ML403 borad with MontaVista linux, but I prefer to ppclinux rather. from my point, it is possible because v4-fx is embedded with ppc405 core. so can anyone give me some hints and step by step of the porting process about it? Thank you! Best regards, wickyArticle: 98081
"wicky" <wicky.zhang@gmail.com> schrieb im Newsbeitrag news:1141462801.291457.55090@i40g2000cwc.googlegroups.com... >I have bought ML403 borad with MontaVista linux, but I prefer to > ppclinux rather. from my point, it is possible because v4-fx is > embedded with ppc405 core. so can anyone give me some hints and step by > step of the porting process about it? Thank you! > > Best regards, > wicky > just a few days ago I posted to c.a.f. our success story using ppclinux basically just do it as described there http://www.itee.uq.edu.au/~pml/uclinux_powerpc/ works with V4FX too, tested. no issues. make system build kernel load to ram and watch linux to bootup AnttiArticle: 98082
"Marco T." <marc@blabla.com> schrieb im Newsbeitrag news:dubggf$n6a$1@nnrp.ngi.it... > > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1141400003.663570.191020@i40g2000cwc.googlegroups.com... >> yes >> > > May I use the "configuration memory port" on the baseboard to write into > atmel memory? > if that port has access to the atmel memory then yes? but why are you asking it, doesnt the memec board come with documentation !? AnttiArticle: 98083
"Antti Lukats" <antti@openchip.org> wrote in message news:dubmqm$hct$1@online.de... > "Marco T." <marc@blabla.com> schrieb im Newsbeitrag > news:dubggf$n6a$1@nnrp.ngi.it... >> >> "Antti" <Antti.Lukats@xilant.com> wrote in message >> news:1141400003.663570.191020@i40g2000cwc.googlegroups.com... >>> yes >>> >> >> May I use the "configuration memory port" on the baseboard to write into >> atmel memory? >> > if that port has access to the atmel memory then yes? > > but why are you asking it, doesnt the memec board come with documentation > !? > > Antti > no documentation about it... Only one example that stores code into bram... not so useful.Article: 98084
jtag instruction codes can be found in BSDL files your tcl script selects USER1 (instance with jtag_chaine=1) and send data to user logic basically all your assumptions seem correct I do use the BSCAN and user logic implemented custom jtag chains all the time, but from our own jtag component library so I can not tell if your tcl code should actually work, it seems like it might anttiArticle: 98085
"Marco T." <marc@blabla.com> schrieb im Newsbeitrag news:dubn68$pcc$1@nnrp.ngi.it... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dubmqm$hct$1@online.de... >> "Marco T." <marc@blabla.com> schrieb im Newsbeitrag >> news:dubggf$n6a$1@nnrp.ngi.it... >>> >>> "Antti" <Antti.Lukats@xilant.com> wrote in message >>> news:1141400003.663570.191020@i40g2000cwc.googlegroups.com... >>>> yes >>>> >>> >>> May I use the "configuration memory port" on the baseboard to write into >>> atmel memory? >>> >> if that port has access to the atmel memory then yes? >> >> but why are you asking it, doesnt the memec board come with documentation >> !? >> >> Antti >> > > no documentation about it... > > Only one example that stores code into bram... not so useful. > but they usually have some examples how to flash the serial rom at least other memec boards have some docu, are you sure that there is nothing relevant at memec online RDC ? did you look at all docs and examples at RDC ?? AnttiArticle: 98086
I want to know the default pio mode when device reset and powup,and if the udma mode is surported when device reset and power up!thanks!Article: 98087
"Antti Lukats" <antti@openchip.org> wrote in message news:dubnbo$irm$1@online.de... > "Marco T." <marc@blabla.com> schrieb im Newsbeitrag > news:dubn68$pcc$1@nnrp.ngi.it... >> >> "Antti Lukats" <antti@openchip.org> wrote in message >> news:dubmqm$hct$1@online.de... >>> "Marco T." <marc@blabla.com> schrieb im Newsbeitrag >>> news:dubggf$n6a$1@nnrp.ngi.it... >>>> >>>> "Antti" <Antti.Lukats@xilant.com> wrote in message >>>> news:1141400003.663570.191020@i40g2000cwc.googlegroups.com... >>>>> yes >>>>> >>>> >>>> May I use the "configuration memory port" on the baseboard to write >>>> into atmel memory? >>>> >>> if that port has access to the atmel memory then yes? >>> >>> but why are you asking it, doesnt the memec board come with >>> documentation !? >>> >>> Antti >>> >> >> no documentation about it... >> >> Only one example that stores code into bram... not so useful. >> > > but they usually have some examples how to flash the serial rom at least > other memec boards have some docu, are you sure that there is nothing > relevant at memec online RDC ? did you look at all docs and examples at > RDC ?? > > Antti > There are two examples: the first that implements a webserver; the second is a demo that send datas to the serial connetor, tests the ddr, read/write datas into flash. But software is stored into bram and there is no documentation about storing software into flash.Article: 98088
There is also the issue that FPGA's configuration data is stored in external FLASH where as CPLD's are programmed. It is actually quite easy to reprogram a FPGA on the fly and field update the external memory while the FPGA is still running. No special hardware or algorithms are required. Downloading a CPLD is usually done from a PC via a JTAG cable or via a External Chip Programmer. Simon "Peter Alfke" <peter@xilinx.com> wrote in message news:1141424214.234508.233260@p10g2000cwp.googlegroups.com... > There is a big difference in logic capabilities. Let's express that in > the number of flip-flops or registers: > > CPLDs are good for up to 200 flip-flops, they get disproportionally > expensive for larger designs. > Modern FPGAs start at 2,000 flip-flops, and go up to to 200,000 > flip-flops, plus many other circuits, like RAM, multipliers etc. > > CoolRunner CPLDs offer extremely low power consumption, and small > physical size, and low cost for the smallest parts. > FPGAs fit a much wider range of applications. > > The choice between the two technologies is usually quite clear-cut. > Peter Alfke, Xilinx Applications > ===================================== > Matt Clement wrote: > > Hey guys/gals > > > > What are the advantages and disadvantages of using a CPLD instead of using > > an FPGA for a design? > > > > Thanks >Article: 98089
fpga_toys@yahoo.com wrote: > Austin Lesea wrote: > <snip> Ok, thanks. I'll have a poke around in the FPGA editor and see what I come up with.Article: 98090
Nick Camilleri wrote: > Fixed-location tiles (or pre-defined, rectangular areas) is almost a > necessity, given the gargantuan increase in complexity for what you > propose, dynamic-linking of netlists at runtime. It shows you haven't > done your homework when it comes to understanding the problems that > are associated with PR. You're basically saying "I want a cell-phone > that can call anywhere in the world, can get perfect reception in a > tunnel, can transmit data to space stations, and measure the surface > tempature on Jupiter." Well, if it was that easy, we would have done > it by now. > > Nick I'm certain that your teams working on this were both tallented and put the best available effort given priorities to doing a good job. Neither I, nor anyone else, can do a good job evaluating the difficulty and probability of sucess for RC and PR for your existing chips and software architecture, without access to the design information you hold locked up. So, it's impossible for anyone outside your NDA circle to have done their homework. I've also spent 35 years walking into the middle of clients projects, which were frequently stalled, failed, and/or past contract ship/delivery dates. Nearly everyone of those teams were competent, and many top in their field. They had also reached the limits of their formal training, skills, and experience to find a solution to their project deadlock -- OR -- that were locked into failure by the product specifications forced on them, resources made available, or restrictions against using viable alternative designs, architectures, etc. Frequently the solution path for the projects was a combination of outside ideas, outside experience, and outside influence to change the product specifications, resource alloctions, and removing the road blocks to other viable solution strategies. I'm certain that if it was easy for you to do with the requirements, resources, and restrictions place on your developers, that you would have delivered a strong reliable RC and PR tools by now. I'm also certain that ourside your organization, free of the requirements, resource limitations, and organizational restrictions that a different team will respond to a different requirement set and find a viable solution limited only by the existing hardware architecture. And with that success, they will be able to clearly articulate the changes needed to make future Xilinx RC and PR product generations not only very viable, but a strong success for everyone involved, including Xilinx and your customers.Article: 98091
Great! But i am confused with the "uClinux" you used? why not ppclinux distribution? Another question, is it possible to patch the "uClinux" on V4-fx with RTAI which do support ppclinux? thank you! wickyArticle: 98092
In article <duap0m$9dd1@cliff.xsj.xilinx.com>, Nick Camilleri <nick.camilleri@xilinx.com> writes: |> If you know of a killer-app for partial reconfiguration, I'm sure we |> would be happy to listen and try to meet the market's needs. See, and that is the problem. As of now, research is actively pursuing what could become the next set of killer apps. Just check out for the vast efforts being currently put into "reconfigurable computing", "organic computing", "adaptive computing" to give a few buzzwords. Xilinx seemed to have *the* ultimate product for that, but despite all claims, PR support is hardly there. There have been some few successes in this field (e.g. Becker et al. from Univ. Karlsruhe), despite all hassles with varying ISE versions. But in the end, there are still too many obstacles to really *use* PR. Forgot the name, but in this very thread some other poster described his experiences and how they basically came down to getting to know which (sub)version of ISE supported what, and which versions were broken with respect to PR. Which is exactly our experience as well. A couple of weeks ago David Kramer posted in this group for specific help regarding problems with PR [1]. I didn't see one single answer from "you Xilinx guys" *here* regarding his topic. After all, fpga_toys has a point: You are advertising a feature which basically is broken. In hardware it's supported, but using your development software it's rather inaccessible without jumping through a good number of hoops. Personally, I'd be more than lucky if there would be an easy way to accomplish the following: - creating an internal bus connecting a number of same-sized "slots", i.e. regions within the FPGA to be filled with exchangeable functionality - being able to exchange the functionality of those slots on the fly (dynamical partial reconfiguration) - do that with Virtex-IIpro and Virtex-4FX I don't mind if that works only through a shell script (in fact, I'd prefer it that way), if it works at all without throwing INTERNAL_ERRORs and FATAL_ERRORs -- and if it works consistently and not with one specific subversion of one specific ISE version so that when I upgrade the software the design isn't broken or having to chose which chip family I can't use for being able to do PR. Don't ge me wrong: as a university researcher I am more than thankful for the support Xilinx gives us. But as of now I have a feeling that PR on Virtex-II/4 might vanish like XC6200 did vanish end of the 90s just because of the lack of proper software support: if a hardware feature is not properly accessible via the development software it won't be used. Therefore no multi-million dollar revenue will come from that, and following your argumentation you won't put major effort into it if you can't be sure that there's a multi-million dollar revenue to expect. That's a vicious circle only *you* can break: either by releasing software which supports PR without major obstacles, or put out enough information (could be under NDA, as I'm not that religious to demand that everything is open-sourced) so that fpga_toys (or whoever) is able to build supporting software. Rainer [1] http://groups.google.com/group/comp.arch.fpga/tree/browse_frm/thread/cc25adfd2f813f81Article: 98093
"wicky" <wicky.zhang@gmail.com> schrieb im Newsbeitrag news:1141476127.310105.11510@i40g2000cwc.googlegroups.com... > Great! > > But i am confused with the "uClinux" you used? why not ppclinux > distribution? > > Another question, is it possible to patch the "uClinux" on V4-fx with > RTAI which do support ppclinux? > > thank you! > > wicky > the uclinux is there actually only naming issue, it is actually FULL ppclinux with MMU support AnttiArticle: 98094
"Marco T." <marc@blabla.com> schrieb im Newsbeitrag news:dubove$q2j$1@nnrp.ngi.it... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dubnbo$irm$1@online.de... >> "Marco T." <marc@blabla.com> schrieb im Newsbeitrag >> news:dubn68$pcc$1@nnrp.ngi.it... >>> >>> "Antti Lukats" <antti@openchip.org> wrote in message >>> news:dubmqm$hct$1@online.de... >>>> "Marco T." <marc@blabla.com> schrieb im Newsbeitrag >>>> news:dubggf$n6a$1@nnrp.ngi.it... >>>>> >>>>> "Antti" <Antti.Lukats@xilant.com> wrote in message >>>>> news:1141400003.663570.191020@i40g2000cwc.googlegroups.com... >>>>>> yes >>>>>> >>>>> >>>>> May I use the "configuration memory port" on the baseboard to write >>>>> into atmel memory? >>>>> >>>> if that port has access to the atmel memory then yes? >>>> >>>> but why are you asking it, doesnt the memec board come with >>>> documentation !? >>>> >>>> Antti >>>> >>> >>> no documentation about it... >>> >>> Only one example that stores code into bram... not so useful. >>> >> >> but they usually have some examples how to flash the serial rom at least >> other memec boards have some docu, are you sure that there is nothing >> relevant at memec online RDC ? did you look at all docs and examples at >> RDC ?? >> >> Antti >> > > > There are two examples: the first that implements a webserver; the second > is a demo that send datas to the serial connetor, tests the ddr, > read/write datas into flash. > But software is stored into bram and there is no documentation about > storing software into flash. > Dear Marco, c.a.f. is not memec-avnet support. memec uses Xilinx XAPP800 based solution for the FPGA config in several boards, I assume also in the case of the mini module. For V4 board that I have there is memec docu and script how to program the seiral flash over SPI port using X_SPI, I assume something similar exists for the mini module also as the minimodule has parallel flash so it is logical that memec guys think that everyone uses parallel flash to store software applications, in that case it is possible to use the flash_writer.tcl - it is very unfriendly path but it works sometimes. if you want to use dataflash then just append your sw application code after the config bitstream and thats it. in your soc you need to implement spi bootloader what is about 30-40 lines of C code and can be written within a few hours. Too bad that memec hasnt provided a demo with that 40 lines, bad luck, you need to write them yourself. Of course you can use some existing code but that may take more time than rewriting from scratch. http://xilant.com/content/view/38/2/ there is a similar module where spi flash is used as config and sw storage (linux image) i had absolutly no problems impementing the bootloader, well actually the load process is 2 step, first a pre-boot loader (in BRAM) is loading u-boot, then u-boot is taking aver to provide a more felxible bootloader u-boot source code includes some dataflash support, for my case I had to add the ST25 SPI support myself AnttiArticle: 98095
yyqonline wrote: > Hi, everyone. > I want to do a presentation about the introduction about Xilinx > Chipscope on the meeting of my lab. Since I have used this software for > not a long time, I need some comments, tips, and other information > about Chipscope from you, the veteran designers of Fpga. > Any advice would be appreciated very much, and my email is > yyqonline@gmail.com. > Thanks a lot. > yours, > YuQing Youth > You need to actually read the manual and/or use it. ChipScope is a bunch of very different tools, including some very non-real-time, and some full real-time. Most people think of ChipScope ILA, but there's a lot more to it than that. GSArticle: 98096
Brian, Here are the apologies: I am sorry that you feel compelled to post on this subject compulsively. I am sorry to see that you discredit yourself in public by posting a spice fantasy. I am sorry I took your posting seriously enough to do a real simulation and show that there is no problem (which I knew already from the customers that are using our parts successfully). I am sorry that I have been unable to resolve this issue with you in a mutually positive way. AustinArticle: 98097
MM wrote: > Dear EDK experts, > > I have a top-level ISE project with an EDK subsystem. In that top-level > design I have a state machine, which has very little to do with the > processor subsystem, but requires several bits for control. What would be > the most natural way of doing this? The options I am aware of are as > follows: > > 1. Make the state machine a custom OPB peripheral; > 2. Control it with an OPB_GPIO module; > 3. Control it through DCR; > 4. Fully-custom control logic on the OPB bus. > > The GPIO approach seems the easiest to me (perhaps because I've never tried > using DCR), but I would like to know what others do in such cases. For one project, the GPIO approach might be easiest. But it is a pain when every time a new signal is desired, the EDK portion has to be recompiled. What I did was to start with the GPIO core and then modify it to output signals for address, read data, write data, and read/write control. Then I have a register implementation as part of my ISE project, and that is the only place I need to make changes. A little extra work up front, but well worth it in my opinion.Article: 98098
Rainer Buchty wrote: > That's a vicious circle only *you* can break: either by releasing software > which supports PR without major obstacles, or put out enough information > (could be under NDA, as I'm not that religious to demand that everything is > open-sourced) so that fpga_toys (or whoever) is able to build supporting > software. > > Rainer > > [1] http://groups.google.com/group/comp.arch.fpga/tree/browse_frm/thread/cc25adfd2f813f81 I'm not that religious about open source either. But I also see that some perception of value needs to justify the cost in corporate america, or the board will question wasting the dollars that the stock holders have a right to expect be spent for value. I don't see another solution at this time. I do know that RC on xilinx is dead with the ISE tax to use such a computer or accel card, and for a product that doesn't even support RC as it needs to be supported in a high value multiprocessing multiprocessor FPGA based computer. Clearly Xilinx thinks this will not be a high volume revenue source, and compared to dedicated sales they are probably right. So we can never expect support at the levels needed to support good RC and PR on their product line. It's not right to bitch at them for not doing a better job when the revenues aren't likely to cover the work. I do think that asking them to open up enough we can support ourselves is of value, and they have the right to decline. At least everyone will know the rules of the game, and not waste their energies on a dead end Xilinx RC and PR dream if they refuse. There are other vendors that might see this as their gold mine, and openly support developers helping them.Article: 98099
Nick Camilleri wrote:
> Fixed-location tiles (or pre-defined, rectangular areas) is almost a
> necessity, given the gargantuan increase in complexity for what you
> propose, dynamic-linking of netlists at runtime. It shows you haven't
> done your homework when it comes to understanding the problems that
> are associated with PR. You're basically saying "I want a cell-phone
> that can call anywhere in the world, can get perfect reception in a
> tunnel, can transmit data to space stations, and measure the surface
> tempature on Jupiter." Well, if it was that easy, we would have done
> it by now.
I've read Neal Steiners thesis and related papers several time over the
last couple years (etd-09112002-143335):
A Standalone Wire Database for Routing and Tracing in Xilinx
Virtex, Virtex-E, and Virtex-II FPGAs
Along with the papers for VPR and VPR for Virtex, JHDL docs, and
several related projects.
That however, doesn't describe the work necessary to do a good router
for Virtex-2, Pro, or Virtex-4 products .... which I believe is info
only available from Xilinx.
Any other suggestions for doing our homework?
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