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what you see is correct, the IR read back is always same as long as config status doesnt change, as long as USERn is in IR register and Test logic reset state has not been entered any shift DR commands go FPGA fabric Antti LukatsArticle: 98226
You can make and add an IP core just like you do for other custom things. You just won't connect it to a bus. You still need the same folder structure and files as you would for another core though...mpd, pao, etc. I have a couple of these "glue logic" cores in our project. Then you can just connect them internally however you want to. It is easier and cleaner than modifying the emc's logic...if you are even allowed to. Or you can follow Goran's advice and manually add it to the mhs. Either way.Article: 98227
Sorry in advance...I can't answer your question. I have one of my own. Have you been able to simulate without using the external RAM? I have a microblaze project that I have been able to get working in NC-Sim. Unfortunately, the simulation has to run a LONG time before the system is even initialized. NC-Sim starts getting bogged down and apparently the memory resources used are huge! I then cannot simulate what I am interested in. Do you have any advice? For your problem, I would think that you may have to use internal RAM resources that have simulation information instead of an exteranal device. You probably can do it with the external RAM, but I bet it is difficult. If you are trying to do timing sim, I guess the internal RAM would not give you the most realistic sim. However, if you are just trying to sim HW/SW interaction, it should be OK. I have not found much info on simulating a whole ppc/MB system. There is instruction on how to set it up, but once that is done, the info trickles off. My level of knowledge on NC-Sim is limited! Good luck!!Article: 98228
Antti wrote: > what you see is correct, the IR read back is always same as long as > config status doesnt change, > > as long as USERn is in IR register and Test logic reset state has not > been entered any shift DR commands go FPGA fabric > > Antti Lukats > Thanks for the information. Meanwhile I found the stupid bug: there was no valid data put on the tdo input of the bscan_virtex4 component (only an unused signal). Now I can read back the value I expected. FrankArticle: 98229
More specifically, for a tristate data bus as you mentioned for the processor that carries data, there is a bus arbitor somewhere. For your problem, you must check if the processor provides a bus arbitor that I think so. Otherwise it would generate bus conflicts. And the new module should have an input and an output to request the bus and gets the permission to drive the bus. WengArticle: 98230
thanks everyone to give those advices , I try to use the ISE 8.1 to do PR with the methode difference-based partial reconfiguration , =E7a marche , but I never find out the differents with the others version. and someone said the PlanAhead provides a single envirenement to manage the preceding guideline but it must call my local FAE, so I dont know how easy with it for the PR . if anyone knew it please told me! thanks a lot regards xunArticle: 98231
"vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1141713318.376695.52550@u72g2000cwu.googlegroups.com... > Hi all, > I am facing a problem with my design. In which i assigned tri > state buffers to drive a bus which is connected to sixteen identical > blocks. This bus is controlling the register updation. But in the > default configuration when all blocks are driving high impedance to the > bus the bus is going to '1' state by internal pull up. I want to know > is there any way to pull down the internal signals in the Xilinx FPGA > (specifically Virtex 4 or Virtex E). > regards > Sumesh V S If you're talking about an internal tristate which is emulated - not instantiated - in more recent Xilinx families and all Altera devices, you have two solutions I can think of: Use logic that looks for no TRI enables in order to drive the tristate low, or Invert your logic so the inputs to all the tristates are inverted and the destination of those tristates is also inverted; the undriven state is still a logic 1 but you're now inverting it at your input.Article: 98232
Can anyone recommend some rea$onable software for doing JTAG boundary scan? I have a design with some CPLD's that are Boundary scan capable so I thought it would be a nice way to look for shorts or opens on the boards. But I certainly am not looking to pay thousands of dollars for it. I have downloaded the files defining the boundary from Altera's site, but now I need the software to use it......preferably windows based. I could boot linux if that is the only option. ThanksArticle: 98233
Subhasri krishnan wrote: > Hi all, > I am trying to modify some code and I came across these constraints. > 'clk_in' is the input clock and 'clk' is generated using a DCM (its is > the Divide By 2 output). > > NET "clk_in" TNM_NET = "clk_in"; > TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %; > > TIMEGRP "rising_ffs" = RISING "clk"; > TIMEGRP "falling_ffs" = FALLING "clk"; > TIMESPEC "TS_pos_to_neg" = FROM "rising_ffs" TO "falling_ffs" 5 ns ; > > Is there something wrong with the last FROM : TO statement? Can the > same condition be specified using the Period statement? I think its > supposed to mean "delay between the rising and falling edge is to be > kept to 5ns". Yes, the same condition can be specified with a period statement. When ISE sees that opposite edges of the clock are being used, it will automatically cut the period in half (assuming a HIGH 50 % is applicable). So you just need: TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;Article: 98234
I have implemented a 8-bit synchronous counter by VHDL. The result is
that the LED display show continuously running the count from 0 to
F(in Hex). Now, I need to change the result which the LED display can
count from 0 to 9 only. How can I change in the VHDL code? Can anyone
answer me? Thanks a lot!!
The following VHDL code are about 8-bit synchronous counter:
Library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY counter_eg IS
PORT(
PB1, clk_25MHz : IN std_logic;
led0, led1, led2, led3, led4, led5, led6 : OUT std_logic);
END counter_eg;
ARCHITECTURE c OF counter_eg IS
COMPONENT counter
PORT(
Clock, Reset : IN std_logic;
count : OUT std_logic_vector(3 DOWNTO 0));
END COMPONENT;
COMPONENT dec_7seg
PORT(
hex_digit : IN std_logic_vector(3 DOWNTO 0);
segment_a, segment_b, segment_c, segment_d, segment_e,
segment_f, segment_g : OUT std_logic);
END COMPONENT;
COMPONENT clk_div
PORT(
clock_25MHz : IN std_logic;
clock_1MHz : OUT std_logic;
clock_100KHz : OUT std_logic;
clock_10KHz : OUT std_logic;
clock_1KHz : OUT std_logic;
clock_100Hz : OUT std_logic;
clock_10Hz : OUT std_logic;
clock_1Hz : OUT std_logic);
END COMPONENT;
SIGNAL count : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_1KHz : std_logic;
BEGIN
c0: clk_div port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz);
c1: counter port map (clock=>clk_1KHz, reset=>PB1, count=> count);
c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5,
led6);
END c;
Article: 98235sandypure@yahoo.com wrote: > I have implemented a 8-bit synchronous counter by VHDL. The result is > that the LED display show continuously running the count from 0 to > F(in Hex). Now, I need to change the result which the LED display can > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > answer me? Thanks a lot!! > The following VHDL code are about 8-bit synchronous counter: > Library IEEE; > USE IEEE.std_logic_1164.all; > USE IEEE.std_logic_arith.all; > USE IEEE.std_logic_unsigned.all; > > ENTITY counter_eg IS > PORT( > PB1, clk_25MHz : IN std_logic; > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); > END counter_eg; > > ARCHITECTURE c OF counter_eg IS > > COMPONENT counter > PORT( > Clock, Reset : IN std_logic; > count : OUT std_logic_vector(3 DOWNTO 0)); > > END COMPONENT; > > COMPONENT dec_7seg > PORT( > hex_digit : IN std_logic_vector(3 DOWNTO 0); > segment_a, segment_b, segment_c, segment_d, segment_e, > segment_f, segment_g : OUT std_logic); > END COMPONENT; > > COMPONENT clk_div > PORT( > clock_25MHz : IN std_logic; > clock_1MHz : OUT std_logic; > clock_100KHz : OUT std_logic; > clock_10KHz : OUT std_logic; > clock_1KHz : OUT std_logic; > clock_100Hz : OUT std_logic; > clock_10Hz : OUT std_logic; > clock_1Hz : OUT std_logic); > END COMPONENT; > > SIGNAL count : std_logic_vector(3 DOWNTO 0); > SIGNAL clk_1KHz : std_logic; > BEGIN > c0: clk_div port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz); > c1: counter port map (clock=>clk_1KHz, reset=>PB1, count=> count); > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, > led6); > > END c; > I'm not going to do your homework for you but here's a suggestion, how about decoding when the count equals 9 and using this to reset your counter. For your percentage I'm sure you can figure out how to code that in your vhdl. AlanArticle: 98236
Identity Hidden wrote: > That's nice, I guess I will give our discontinued SDR project another > chance. > What is the estimated time of ISE 9.1i release? January 2007 > > >Article: 98237
Sorry if this newsgroup is only for discussions on FPGA.
The FIFO I am trying to design is just a part of my Serial Peripheral
Interface (SPI) design to be used in a 32-bit microcontroller (ASIC). I
have two different FIFOs, one for transmit and one for receive. Here I
am talking about the receive FIFO, where I receive data on my wr_clk
(sent by an outside device and so is not free running. It actually
sends the clock only when it has data to send to my SPI) but I read
that data on rd_clk (this is internal to my design). In this case, the
FIFO can actually go FULL and the next time I receive data when the
FIFO is FULL, I set an overrun flag which is fine. The FIFO is 4 deep
and the clock I receive from an external device (wr_clk) can be as high
as 25 MHz. The same holds ture for my rd_clk.
I have gone through your paper "Simulation and Synthesis Techniques
for Asynchronous FIFO Design with Asynchronous Pointer Comparisons".
But I have a question on
pg.9 in "async_cmp.v" empty/full flag comparison module.
Say, the wr_ptr is one quadrant behind the rd_ptr (in our case, assume
rd_ptr = 11 (gray) and wr_ptr = 01). Now "dirset_n" will be active and
on it's negative edge "direction" will be set meaning that the FIFO is
going full. But when I load one more word into the FIFO and the rd/wr
pointers become equal, what would "direction" be? From the code given,
when there is no negative edge on "dirset_n" or "dirclr_n", "direction"
would always be tied to Vdd. This looks ok for the full flag logic as
per
assign afull_n = ~((wr_ptr == rd_ptr) && direction);
as the "direction" is still high even after the pointers became
equal.
But in case of empty logic,
assign aempty_n = ~((wr_ptr == rd_ptr) &&
!direction);
"direction" will be cleared only on the negative edge of "dirclr_n"
which happens when the rd_ptr is one quadrant behind the wr_ptr. But
when I read one more word from the FIFO, rd/wr pointers become equal
and "direction" will now be set meaning that "aempty_n" is not active
while it should have been as the FIFO is really empty now.
Can you please explain this at your convenience? Sorry if I am
wrong in my thought. Also please let me know what would be an effective
way to code the intended behavior (basically an SR flop doing what we
wanted).
Thank You
Aditya
Article: 98238sandypure@yahoo.com wrote: > I have implemented a 8-bit synchronous counter by VHDL. I'll give you a hint, the counter is not in this file, only the intantiation of the counter. but you can decode count=10 and trigger a reset. (in this file) as Alan just said. Aurash The result is > that the LED display show continuously running the count from 0 to > F(in Hex). Now, I need to change the result which the LED display can > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > answer me? Thanks a lot!! > The following VHDL code are about 8-bit synchronous counter: > Library IEEE; > USE IEEE.std_logic_1164.all; > USE IEEE.std_logic_arith.all; > USE IEEE.std_logic_unsigned.all; > > ENTITY counter_eg IS > PORT( > PB1, clk_25MHz : IN std_logic; > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); > END counter_eg; > > ARCHITECTURE c OF counter_eg IS > > COMPONENT counter > PORT( > Clock, Reset : IN std_logic; > count : OUT std_logic_vector(3 DOWNTO 0)); > > END COMPONENT; > > COMPONENT dec_7seg > PORT( > hex_digit : IN std_logic_vector(3 DOWNTO 0); > segment_a, segment_b, segment_c, segment_d, segment_e, > segment_f, segment_g : OUT std_logic); > END COMPONENT; > > COMPONENT clk_div > PORT( > clock_25MHz : IN std_logic; > clock_1MHz : OUT std_logic; > clock_100KHz : OUT std_logic; > clock_10KHz : OUT std_logic; > clock_1KHz : OUT std_logic; > clock_100Hz : OUT std_logic; > clock_10Hz : OUT std_logic; > clock_1Hz : OUT std_logic); > END COMPONENT; > > SIGNAL count : std_logic_vector(3 DOWNTO 0); > SIGNAL clk_1KHz : std_logic; > BEGIN > c0: clk_div port map (clock_25MHz=> clk_25MHz, clock_1KHz=>clk_1KHz); > c1: counter port map (clock=>clk_1KHz, reset=>PB1, count=> count); > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, > led6); > > END c; >Article: 98239
<sandypure@yahoo.com> wrote in message news:1141751267.321930.165700@v46g2000cwv.googlegroups.com... >I have implemented a 8-bit synchronous counter by VHDL. The result is > that the LED display show continuously running the count from 0 to > F(in Hex). Now, I need to change the result which the LED display can > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > answer me? Thanks a lot!! > How about gating the clock to something really fast when the count is 10 - 15 inclusive. The A-F will whizz by so fast, no-one will notice. If you get that to work, you deserve extra marks. HTH, Syms.Article: 98240
Alan, I want to ask how to decode in vhdl? When the count is at 9, press reset button is go back to 0 again. Alan Myler =E5=AF=AB=E9=81=93=EF=BC=9A > sandypure@yahoo.com wrote: > > > I have implemented a 8-bit synchronous counter by VHDL. The result is > > that the LED display show continuously running the count from 0 to > > F(in Hex). Now, I need to change the result which the LED display can > > count from 0 to 9 only. How can I change in the VHDL code? Can anyone > > answer me? Thanks a lot!! > > The following VHDL code are about 8-bit synchronous counter: > > Library IEEE; > > USE IEEE.std_logic_1164.all; > > USE IEEE.std_logic_arith.all; > > USE IEEE.std_logic_unsigned.all; > > > > ENTITY counter_eg IS > > PORT( > > PB1, clk_25MHz : IN std_logic; > > led0, led1, led2, led3, led4, led5, led6 : OUT std_logic); > > END counter_eg; > > > > ARCHITECTURE c OF counter_eg IS > > > > COMPONENT counter > > PORT( > > Clock, Reset : IN std_logic; > > count : OUT std_logic_vector(3 DOWNTO 0)); > > > > END COMPONENT; > > > > COMPONENT dec_7seg > > PORT( > > hex_digit : IN std_logic_vector(3 DOWNTO 0); > > segment_a, segment_b, segment_c, segment_d, segment_e, > > segment_f, segment_g : OUT std_logic); > > END COMPONENT; > > > > COMPONENT clk_div > > PORT( > > clock_25MHz : IN std_logic; > > clock_1MHz : OUT std_logic; > > clock_100KHz : OUT std_logic; > > clock_10KHz : OUT std_logic; > > clock_1KHz : OUT std_logic; > > clock_100Hz : OUT std_logic; > > clock_10Hz : OUT std_logic; > > clock_1Hz : OUT std_logic); > > END COMPONENT; > > > > SIGNAL count : std_logic_vector(3 DOWNTO 0); > > SIGNAL clk_1KHz : std_logic; > > BEGIN > > c0: clk_div port map (clock_25MHz=3D> clk_25MHz, clock_1KHz=3D>clk_1K= Hz); > > c1: counter port map (clock=3D>clk_1KHz, reset=3D>PB1, count=3D> coun= t); > > c2: dec_7seg port map (count, led0, led1, led2, led3, led4, led5, > > led6); > > > > END c; > > > > > I'm not going to do your homework for you but here's a suggestion, how > about decoding when the count equals 9 and using this to reset your > counter. For your percentage I'm sure you can figure out how to code > that in your vhdl. >=20 > AlanArticle: 98241
gating the clcok?? i don't understand!! Can you explain? Thanks!!Article: 98242
Symon, gating the clcok?? i don't understand!! Can you explain? Thanks!!Article: 98243
Aditya, "Sorry" that you are asking ASIC questions on a FPGA newsgroup? Don't be. Is it really that desparate? No one to talk to when you design an ASIC anymore? I don't mind the off topic question. It is instructive as it demonstrates just how hard it is to make an ASIC that actually works. And it gives all of the FPGA users a good feeling that they made the right decision, and did not even try to make an ASIC. Who needs those headaches. But I doubt that either Xilinx or Altera IC designers will offer to help you (much) with your ASIC design. We have enough work to do ourselves, and it is not in our interest to help ASIC designers design their ASICs. There are plenty of ASIC designers who are now FPGA users (as their bosses gave them a simple choice: design with FPGAs, or leave) that read this newsgroup. Perhaps they will help you. Austin Aditya wrote: > Sorry if this newsgroup is only for discussions on FPGA. > > The FIFO I am trying to design is just a part of my Serial Peripheral > Interface (SPI) design to be used in a 32-bit microcontroller (ASIC). I > have two different FIFOs, one for transmit and one for receive. Here I > am talking about the receive FIFO, where I receive data on my wr_clk > (sent by an outside device and so is not free running. It actually > sends the clock only when it has data to send to my SPI) but I read > that data on rd_clk (this is internal to my design). In this case, the > FIFO can actually go FULL and the next time I receive data when the > FIFO is FULL, I set an overrun flag which is fine. The FIFO is 4 deep > and the clock I receive from an external device (wr_clk) can be as high > as 25 MHz. The same holds ture for my rd_clk. > > I have gone through your paper "Simulation and Synthesis Techniques > for Asynchronous FIFO Design with Asynchronous Pointer Comparisons". > But I have a question on > pg.9 in "async_cmp.v" empty/full flag comparison module. > > Say, the wr_ptr is one quadrant behind the rd_ptr (in our case, assume > rd_ptr = 11 (gray) and wr_ptr = 01). Now "dirset_n" will be active and > on it's negative edge "direction" will be set meaning that the FIFO is > going full. But when I load one more word into the FIFO and the rd/wr > pointers become equal, what would "direction" be? From the code given, > when there is no negative edge on "dirset_n" or "dirclr_n", "direction" > would always be tied to Vdd. This looks ok for the full flag logic as > per > > assign afull_n = ~((wr_ptr == rd_ptr) && direction); > as the "direction" is still high even after the pointers became > equal. > > But in case of empty logic, > > assign aempty_n = ~((wr_ptr == rd_ptr) && > !direction); > > "direction" will be cleared only on the negative edge of "dirclr_n" > which happens when the rd_ptr is one quadrant behind the wr_ptr. But > when I read one more word from the FIFO, rd/wr pointers become equal > and "direction" will now be set meaning that "aempty_n" is not active > while it should have been as the FIFO is really empty now. > > Can you please explain this at your convenience? Sorry if I am > wrong in my thought. Also please let me know what would be an effective > way to code the intended behavior (basically an SR flop doing what we > wanted). > > Thank You > > Aditya >Article: 98244
Duane Clark wrote: > Subhasri krishnan wrote: > > Hi all, > > I am trying to modify some code and I came across these constraints. > > 'clk_in' is the input clock and 'clk' is generated using a DCM (its is > > the Divide By 2 output). > > > > NET "clk_in" TNM_NET = "clk_in"; > > TIMESPEC "TS_clk_in" = PERIOD "clk_in" 20 ns HIGH 50 %; > > > > TIMEGRP "rising_ffs" = RISING "clk"; > > TIMEGRP "falling_ffs" = FALLING "clk"; > > TIMESPEC "TS_pos_to_neg" = FROM "rising_ffs" TO "falling_ffs" 5 ns ; > > > > Is there something wrong with the last FROM : TO statement? Can the > > same condition be specified using the Period statement? I think its > > supposed to mean "delay between the rising and falling edge is to be > > kept to 5ns". > > Yes, the same condition can be specified with a period statement. When > ISE sees that opposite edges of the clock are being used, it will > automatically cut the period in half (assuming a HIGH 50 % is > applicable). So you just need: > TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %; Thanks both of you. I tried using the period statement and it worked!(when I used the FROM : TO the constraint was failing).Article: 98245
Sorry Laura, I was being sarcastic. Of course, gating the clock is BAD! Almost as bad as asking people on a newsgroup to do your homework for you! ;-) Cheers, Syms. <laura_pretty05@yahoo.com.hk> wrote in message news:1141754026.219843.19920@z34g2000cwc.googlegroups.com... > Symon, > gating the clcok?? i don't understand!! Can you explain? Thanks!! >Article: 98246
http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385 Well, I guess that about wraps it up for the attempt to disguise ASIC design as something different... AustinArticle: 98247
Matt Clement wrote:
> Can anyone recommend some rea$onable software for doing JTAG boundary scan?
> I have a design with some CPLD's that are Boundary scan capable so I thought
> it would be a nice way to look for shorts or opens on the boards. But I
> certainly am not looking to pay thousands of dollars for it.
It's an excellent way to debug boards that don't boot.
And worth the money for commercial use.
Probably not worth the time or money otherwise.
There is significant development time, even
with the best tools.
-- Mike Treseler
Article: 98248mike what kind of money are we talking for commercial use? what software packages would you suggest or recommend? thanks "Mike Treseler" <mike_treseler@comcast.net> wrote in message news:4764nlFe0g8cU1@individual.net... > Matt Clement wrote: >> Can anyone recommend some rea$onable software for doing JTAG boundary >> scan? >> I have a design with some CPLD's that are Boundary scan capable so I >> thought >> it would be a nice way to look for shorts or opens on the boards. But I >> certainly am not looking to pay thousands of dollars for it. > > It's an excellent way to debug boards that don't boot. > And worth the money for commercial use. > Probably not worth the time or money otherwise. > There is significant development time, even > with the best tools. > > -- Mike TreselerArticle: 98249
Some of you guys must go back to Wilf Corrigan's days at Fairchild and know the players at LSI. I suppose LSI couldn't move while this famously emollient character was in the driving seat ;-) Did LSI ever think of investing in X or A? Austin Lesea wrote > http://www.eetimes.com/news/semi/showArticle.jhtml;jsessionid=2VY5CYWYDOXWUQSNDBCSKH0CJUMEKJVN?articleID=181501385 > > Well, I guess that about wraps it up for the attempt to disguise ASIC > design as something different...
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