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> There are no charge pumps in FPGAs now since Virtex (roughly 7.5 years). Just doing a quick search I find the Coolrunner is using a charge pump for the programming voltage. Just search the data sheet for "charge" and you will find it.Article: 82951
Thanks ! It Worked .. But both are logically equal. What was my mistake ?Article: 82952
archilleswaterland@hotmail.com wrote: > Hi, > > I am using OV6620 Omnivision CMOS Image sensor. My module has > CLK fosc: 17.734MHz > PCLK: 112ns = 8.92MHz > > Does any body know how this is acheieved (mathematically ?) > > Thanks, > Archilles 112 ns * 145 / 288 = 56+7/18 ns 112 ns --> 8.92857 MHz 56+7/18 ns --> 17.73399 MHz You could do this with a phase-locked loop and two counters, one 8-bit and one 9-bit.Article: 82953
Petter Gustad <newsmailcomp6@gustad.com> wrote: >nospam <nospam@nospam.invalid> writes: > >> Eric Smith <eric@brouhaha.com> wrote: >>>Everything that is generated by the tools should not be checked into >>>the repository. >> >> Assuming you can rely on the tools to regenerate exact copies of everything >> else which you can't after a patch or service pack or new version. You >I always install the tools and SP's in a fresh location. I always keep >the previous releases. If someone is worried about adding a few MB of generated files to a repository then allocating a GB of storage every few months for every tool version and service pack would seem to be much more of a problem. The chances are the a new tool version will generate the same files, you may well never need to go back to that project anyway. Keeping a few MB of generated files rather than a GB install of the tool version which generated them sounds like a reasonable compromise to me. >I work in a UNIX environment where this is >easier, i.e. no shared registry where things gets messed up. My limited experience with Xilinx under Windows is that registry usage doesn't much mess up older versions. Windows explorer file associations do get messed up but ISE seems happy if from a command prompt you set the required environment variables and launch it.Article: 82954
Hi all, I am having a component Multiplier with unconstrained ports. But this is not my top_level_entity and ports are implicity constrained while instanciating this component. It simulates well but while synthezing Quartus says that ports must be constrained. I think that Quartus could infer it from instanciation syntax. Is there any solution to get around it Thanks. -- Mohammed A Khader.Article: 82955
nospam <nospam@nospam.invalid> writes: > Petter Gustad <newsmailcomp6@gustad.com> wrote: > >>nospam <nospam@nospam.invalid> writes: >> >>> Eric Smith <eric@brouhaha.com> wrote: >>>>Everything that is generated by the tools should not be checked into >>>>the repository. >>> >>> Assuming you can rely on the tools to regenerate exact copies of everything >>> else which you can't after a patch or service pack or new version. You > >>I always install the tools and SP's in a fresh location. I always keep >>the previous releases. > > If someone is worried about adding a few MB of generated files to a > repository then allocating a GB of storage every few months for every tool > version and service pack would seem to be much more of a problem. It's not the due to the storage itself since disk-space is cheap. All the EDA software installations are done on a server which is not backed up frequently. The CVS repository is backed up frequently. Data is also checked out of the CVS repository by several developers so a smaller repository will result in faster checkout. Some developers might check out the repository over ADSL/ISDN connections as well. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 82956
Hello,
Can you be more specific as to the exact message that Quartus gives? You
can cut ans paste the Quartus message in the reply. Also can you describe
what is meant by "implictly constrainedwhile instanciating" in the post?
Subroto Datta
Altera Corp.
"Mohammed A khader" <am.imak@gmail.com> wrote in message
news:1114002116.636763.217170@g14g2000cwa.googlegroups.com...
> Hi all,
>
> I am having a component Multiplier with unconstrained ports. But this
> is not my top_level_entity and ports are implicity constrained while
> instanciating this component.
>
> It simulates well but while synthezing Quartus says that ports must be
> constrained. I think that Quartus could infer it from instanciation
> syntax. Is there any solution to get around it
>
> Thanks.
>
> -- Mohammed A Khader.
>
Article: 82957Hi, I am trying to use the "DDR_MEM" Lattice template which is responsable for the datapath for DDR SDRAM controller. "DDR_MEM" can be found in the MODULE/IP MANAGER under ARCHITECTURE_MODULES --> IO --> DDR_MEM When instantiating that module and compiling my design I can see in the timing analysis that the bits on the bidirectional busses DQ and DQS have different Clock-To-Output times. In my opinion the busses should be routed into IO register cells when instantiating that special template. So there are three possibilities: 1. They are not routed into IO register cells so that the PERFORMANCE ANALYST does show different tCO 2. They ARE routed into IO register cells, but the PERFORMANCE ANALYST does not take them into timing calculation 3. I have to make any assignment so that the busses are routed into IO registers. But I have not found any assignment possibility in the PREFERENCE EDITOR. Has someone experienced similar or same problems ? Thank you in advance. Rgds AndréArticle: 82958
Hi, -- Error messages are...... Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26): ports must be constrained Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(27): ports must be constrained Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(28): ports must be constrained Error: Can't elaborate user hierarchy "Core:Core_Map|Datapath:Datapath_Map" Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings Error: Processing ended: Wed Apr 20 16:33:52 2005 Error: Elapsed time: 00:00:05 -- My Multiplier component is ......... entity Multiplier_Synth is port( Op1 : in signed; -- Operator 1 Op2 : in signed; -- Operator 2 Mult_Out : out signed -- Multiplication Result ); end entity Multiplier_Synth; architecture Multiplier_Synth_Arch of Multiplier_Synth is begin Mult_Out <= Op1 * Op2; end architecture Multiplier_Synth_Arch; -- And it has been instantiated in an entity called Datapath_Map as ...... signal Mux1_Out : WORD20; -- Output of Mux1 signal Mux2_Out : WORD; -- Output of Mux2 signal Mult_Out : signed(39 downto 0); -- Multiplier Output Multiplier_Map : entity work.Multiplier_Synth(Multiplier_Synth_Arch) port map( Op1 => Mux1_Out, Op2 => Mux2_Out, Mult_Out => Mult_Out ); Mux1_Out , Mux2_Out and Mult_Out are constrained signals . Hence Op1,Op2,Mult_Out implicitly can be constrained by bit length of 20,20,40 respectively. Thanks.. -- Mohammed A Khader.Article: 82959
Hi, Could anyone let me the typical time durations required for a. Scrubbing b. Readback c. Reconfiguration of a Virtex - II, 1M gate device? Thank you.Article: 82960
nospam wrote: > Eric Smith <eric@brouhaha.com> wrote: > > >>"Andy Peters" <Bassman59a@yahoo.com> writes: >> >>>I think you misunderstand my question, which is: what files are >>>necessary and what files are cruft? >> >>Your Verilog and/or VHDL files, and your UCF files are necessary. Anything >>else that you create yourself is necessary. All those things should be >>checked into your repository. >> >>Everything that is generated by the tools should not be checked into >>the repository. > > > Assuming you can rely on the tools to regenerate exact copies of everything > else which you can't after a patch or service pack or new version. You > also need whatever holds the tool configuration and options, is that more > than an npl file? > The project will indeed be completely recreated from the npl file. I have done this many times in the past (because I often create new projects by copying and modifying old projects). You probably also want to save cdf files, which contain Impact configurations. In general, if there are not large jumps in ISE versions, a new ISE version will read, and update if necessary, old npl file versions. Generally, going backwards will not work though. At least this has been my experience so far (using Xilinx tools for almost a decode).Article: 82961
Coolrunner is a CPLD. Austin lecroy7200@chek.com wrote: >>There are no charge pumps in FPGAs now since Virtex (roughly 7.5 > > years). > > Just doing a quick search I find the Coolrunner is using a charge pump > for the programming voltage. Just search the data sheet for "charge" > and you will find it. >Article: 82962
Praveen, Look it up in the data sheet. Pick the fastest config clock, and the widest config bus, and calculate hwo fast you can program a device. Austin Praveen wrote: > Hi, > > Could anyone let me the typical time durations required for > > a. Scrubbing > b. Readback > c. Reconfiguration > > of a Virtex - II, 1M gate device? > > Thank you. >Article: 82963
Hi,
To design an Altera Stratix FPGA I use a top level AHDL file. But
using AHDL I found a pretty strange behaviour (at least it seems so to
me). Following is the relevant extract from the AHDL file:
subdesign top
(
x[31..0] : bidir;
}
variable
xtri[31..0] : tri;
begin
xtri[] = B"11001100110011001100110011001100";
end;
when I synthesize the design and load it to the FPGA things work as
expected (the pins represented by x[] hold the assigned "11001100..."
sequence.
But when I simulate the design in quartus II (Processing -> Start
Simulation) with a predefined vwf file x is not set. All the values
stay "U Z" all the time.
This is pretty different behaviour of simulation and FPGA
implementation, isn't it? What I'd expect is the behavior the FPGA
displays.
thanks for any hint on how to get the simulation run as expected,
/ch
Article: 82964Mohammed A Khader wrote: > Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26): > ports must be constrained > -- My Multiplier component is ......... > entity Multiplier_Synth is > port( > Op1 : in signed; -- Operator 1 > Op2 : in signed; -- Operator 2 > Mult_Out : out signed -- Multiplication Result > ); > end entity Multiplier_Synth; Use generic parameters - e.g.: entity Multiplier_Synth is generic( width : integer:=16 ); port( Op1 : in signed(width-1 downto 0); Op2 : in signed(width-1 downto 0); Mult_Out : out signed(width*2-1 downto 0) ); end entity Multiplier_Synth; Generic parameters are overridden, if a generic mapping is used during instantiation. (Otherwise the given default value is used.) Because you have to define the bitwidth somewhere in your design, it does not matter where and how. Therefore Generic paramters are suitable. You can feed them from the very bottom to the top entity. RalfArticle: 82965
Hi! I want to make a XPower Estimation of a Design which has no connection to the pins/pads of the FPGA. I tried to do this using a stimuli file, vcd-file and testbench but the Values I get are far of from reality. Does anybody know whether there is a way to do an estimation like this one? Thanks for help. parityArticle: 82966
DQ and DQS should have different clock-to-output timing. DQS rising edge should be in the middle of DQ output window. So receiver can use DQS rising edge to clock in data contained in DQ valid window. What DDR is different from normal SDRAM is DDR is source synchronous driving device. DQS is used to clock in data sent by data sender. WengArticle: 82967
On 19 Apr 2005 16:35:39 -0700, Peter Alfke wrote: > Simple test for double-pulsing: > Just feed the signal under investigation as a clock into a toggling > fip-flop. In this very case, it would be even simpler (without scope). The size of a single transaction is programmed by the host. You could simply count the number of received words (feeded into the CRC calculator). SebastianArticle: 82968
On Tue, 19 Apr 2005 16:51:50 -0400, Brijesh wrote: > I sample the strobe signal at 133MHz and detect the edge. That way I kno > w when new data is present on the IOB's. So you have a clock domain crossing here. Could it be a problem of metastable flipflops? What are your constraints of the inter-domain paths? How many stages has your synchronizer logic? SebastianArticle: 82969
On 20 Apr 2005 03:48:55 -0700, Mohammed A khader wrote: > -- Concatenation of Low and High to form 32 Control Word > Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN > THIS LINE... > > Whats wrong with the last statment. I expect '&' operator to > concatenate the two signals. What could be the other meaning of '&' > operator. I think I am doing a silly mistake some where . Please help > me in resolving this.. With '&' you can (1) concatenate two arrays. For example, when using two arrays of std_login (aka std_logic_vector): "000" & "111" This will create a 6 element long array. With '&' you can (2) append or (3) prepend a single element to an array: "000" & '1' '0' & "111" This will create a 4 element long array. Note that it is syntactically different from "0" & "111", which I described in (1). With '&' you can (4) create a new array by concatenating two elements: '0' & '1' This will create a 2 element array. Now, this works not only with std_logic_vector, but with any array. For example, with this one: > type Regfile is array (natural range<>) of WORD; Now we have two different interpretations of data_out_high & data_out_low It can either produce a signed(0 to 31) (VHDL-93) according to (1), or a Regfile(0 to 1) according to (4). Laurent showed one way to avoid this problem. My first guess would have been something like Data32_Out <= unsigned(signed(data_out_high) & signed(data_out_low)); which is closer to your original code. Maybe the following would work: Data32_Out <= unsigned(signed'(data_out_high & data_out_low)); But I'm not sure. (Please note the tick.) [xp and f'up2 comp.lang.vhdl] SebastianArticle: 82970
Greetings,
Not exactly an answer to your question, but the 'pyparsing' module
for the Python language would make an excelent starting point, and the
author offers a Verilog mode (see http://pyparsing.sourceforge.net)
I don't know if you've come across Python but I've found it makes writing
VHDL parsers / generators trivial. It's somewhat more pleasent on the eyes
than Perl as well (we get enough eye strain from the HDLs... :-)
Cheers,
Chris
Kevin Neilson (kevin_neilson@removethiscomcast.net) wrote:
: Because of the deficiencies in Verilog or the tools, I often have to
: write Perl to generate Verilog. Examples of these deficiencies include:
: - Port list is not parameterizable without use of `defines
: - Many synthesizers don't understand preprocessing constant functions
: - Generate function in Verilog has limitations
: Rather than write Perl to generate Verilog modules, which is a
: cumbersome flow, it would be nice to have a Perl preprocessor. What I
: am thinking of is something that would look through your HDL, find
: formatted comments, parse parameters and `ifdefs, and then execute Perl
: and insert the results there. It would see something like this:
: .
: .
: .
: parameter NUM_UNITS=2;
: `define PARAM2 2
: // Perl Start
: // for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
: // print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
: // }
: // Perl End
: .
: .
: Then it would execute the Perl in the comments and append the output to
: the commented section, like this:
: .
: .
: .
: parameter NUM_UNITS=2;
: `define PARAM2 2
: // Perl Start
: // for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
: // print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
: // }
: // Perl End
: // Generated Perl Code Start
: adder adder0 (.I(i[0],.O(o[0]);
: adder adder1 (.I(i[1],.O(o[1]);
: adder adder2 (.I(i[2],.O(o[2]);
: adder adder3 (.I(i[3],.O(o[3]);.
: // Generated Perl Code End
: .
: .
: Of course this is a simple example that can be accomlished with a
: 'generate', but you get my point. Note that the Verilog parameters have
: been parsed and can be used as Perl variables. With this preprocessor
: you could also do a lot of floating-point preprocessing that uses
: functions like "sine" that don't exist in Verilog. Does anything like
: this exist? Or do I have to write my own?
: -Kevin
Article: 82971You are correct! Now that your posting again, why did you feel the need to change the subject line?Article: 82972
Hello, My first message was probably too specific : I would like to know whether it is possible to specify explicitely either at the level of the synthesizable VHDL model, or as a place & route constraint a timing constraint ensuring a correct setup time at the input of a flip-flop, when the clock of the flip flop is a combinatorial expression of its data input and of another signal (XOR). This other signal never change at a time where it may cause setup or hold violation. The target is a Virtex 2 FPGA, VHDL syntesis : Synplify pro, P&R : Xilinx ISE 6.2 The only way I found to ensure the setup time is to add a Xilinx BUFG buffer to delay the combinatorial expression w.r.t the data, or to force the placement of the combinatorial expression and of the flip flop. Is it possible to do it more cleanly ? Marc "Marc Le Roy" <nospam@please.com> a écrit dans le message news:<4260ba40$0$17370$626a14ce@news.free.fr>... > Hello, > > I am searching how to specify a relative timing constraint (and not a > placement constraint) that would be enforced either by the VHDL synthesis > tool or the place and route tool in the following case (decoding of a > serial link data/strobe like the one depicted in figure 5 of > http://products.sel.sony.com/semi/PDF/wpIEEE1394.pdf ) : > > * the serial link is made of one data line D and one strobe line S > > * the clock CLK at half bit rate is regenerated by an XOR between D and S > > * the data signal D is sampled on both the rising edge and the falling > edge of CLK. > > The problem is that when the clock edge is caused by a change on the D > line, the setup time is very dependant on the routing of D, S and CLK. > Manual placement constraints allow to solve the problem, but it is rather > tricky. I would prefer to find a way to specify a relative timing > contraint between D and CLK. > > MarcArticle: 82973
Hi, I am designing the following converter: LVDS -> some processing -> LVDS. Each LVDS Interface has 3 channels and 1 clock channel at about 300 MHz (differential clock rate). My question is if I should use GLCK pins for the incoming LVDS clock? Should I also use GLCK pins for the outgoing LVDS clock? I don't think so, because there is no OBUFGDS. Or does it make sense to use GCLK pins for OBUFDS? Another question is the bank assignment. Should I put the complete Interface (both LVDS) on the same bank? Or better each LVDS on its own bank? Or do banks not matter at all? regards, BenjaminArticle: 82974
We would like to interface a DSP, TMS320C67xx, to an ATA-5 harddisk directly. It must run in DMA mode (instead of PIO). Is it possible? Does anybody sell FPGA IP Core that can handle this task? Thanks for the attention.
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