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On 5 Dec 2005 14:21:02 -0800, juendme@yahoo.com wrote: >Second, since obviously not everyone here knows enough about binary >arithmetics to understand my questions, let me illustrate on an example >of adding/subtracting 2 3-bit signed numbers: > >Using 2's complement representation, we can represent the following >numbers with 3 bits: [...] >To store the valid result, we only need 4 bits. >However, if one of the numbers is unsigned, 4 bits are not enough. We >can illustrate that using the following example: Clearly if you add two sign bits together, you can store the result in ... one sign bit. And the surprise of this is ... ? - BrianArticle: 92751
On Mon, 05 Dec 2005 16:02:43 -0500, Ray Andraka <ray@andraka.com> wrote: >Brian Drummond wrote: >> Hi all, >> >> I'm looking for ideas why a design using 43 DSP48s as multipliers might >> not fit a V4LX25 with 48 DSPs... >A couple of possibilities: > First, check to make sure you don't have a C port conflict. The two >DSP-48's in a single DSP48 slice share the C-Port, so either both must >use the same value on the CPort, or one must not use the CPort. The >software looks for a specific combination of controls for the CPort to >flag it as unused. If you don't match the template, it may not allow >the two DSP48's to occupy the same slice. Thanks Ray, you were spot on; this was it! I still don't know where to look for the template, because I am letting the synthesis tools infer the slice usage. And it was doing so in a way incompatible with the target part. So I needed some way of controlling synthesis better than "mult_style=LUT" or "use_DSP=NO" :-) And I found it: (though the label doesn't QUITE describe the problem!) "Answer Record: 18498 6.3i XST - XST creates incorrect logic with a multiply subtract function for Virtex-4" suggests attribute KEEP: string; attribute KEEP of mult_registered_output : signal is "true"; which forces the internal adder to be bypassed, thus ensuring neither mult uses the C port. If I get into capacity trouble I'll find a way to place this on half of the identical components, to use the C port in alternate mults, but I'm OK for now. Xilinx could definitely improve documentation on this problem; "Keep" is also mentioned (without linking to further info) as a footnote under "Use_DSP=NO" which I wouldn't normally have considered, since I NEED the DSPs... it doesn't appear at all in the "hints on using DSPs" documents OR the "inferring functions in DSPs" documents where it would actually be useful. I'm sure the synthesis tool could also count C ports used as well as DSPs used, to give a better indication of capacity problems AND a clearer idea of the solution. >The second possibility is that if you are using ISE7.1, you have to have >service pack 4. Check. >A third possibility is that the placer doesn't do a very good job >figuring out placement of DSP48's, especially when there are some >cascaded. That was my first thought; hand placing them changed the error message to the C port one; which with your answer, led me to the solution. Thanks again, - BrianArticle: 92752
you need to compile the simmprim vhdl library first. in your $XILINX directory under /vhdl/src/simprims (replace $XILINX with your actual xilinx installation dir) Aurash bachimanchi@gmail.com wrote: > Hi all, > to be more clear about my problem with timing simulation > after i implement it using xilinx it is creating one TIME_SIM.VHD and > TIME_SIM.SDF file under the folder "timing" > it has an identifier "X_INV_PP" in both files when i compile > TIME_SIM.VHD it is giving an error > "Unknown identifier "X_INV_PP"" > Cannot find component declaration > did anyone come across similar kind of problem.please help me out > > thanks, > > > Regards > Ramakrishna >Article: 92753
Hello, We have a problem here with the NIOS2 IDE. After installing I tried to compile the simple hello_world example and got the following: **** Incremental build of configuration Debug for project hello_world_0 **** make -s all Creating generated_all.mk... C:/altera/quartus51/sopc_builder/bin/sopc_builder: not found make: *** [C:/Users/link/fpga/software/hello_world_0_syslib/Debug/system_description/../ob j/generated_all.mk-t] Error 1 Build completed I checked the installation several times. The c:/altera/quartus51/sopc_builder/bin/sopc_builder definitely exists there. I looked at the makefiles but found no solution there. Somehow the makefile is not able to call sopc_builder. I use Quartus 5.1 and Windows XP. Thanks in advance for any hint. MichaelArticle: 92754
Hi Michael, a problem I had long time ago was that I had "non-standard" characters like ² oder German "Umlaute" in the "/Users/link/". Can't remember the errors I got but maybe it is the same problem... Regards, Thomas www.entner-electronics.com "Michael" <michael@nokia.com> schrieb im Newsbeitrag news:I8flf.15971$Nb2.283459@news1.nokia.com... > Hello, > We have a problem here with the NIOS2 IDE. After installing > I tried to compile the simple hello_world example and got the > following: > > **** Incremental build of configuration Debug for project hello_world_0 > **** > make -s all > Creating generated_all.mk... > C:/altera/quartus51/sopc_builder/bin/sopc_builder: not found > make: *** > [C:/Users/link/fpga/software/hello_world_0_syslib/Debug/system_description/../ob > j/generated_all.mk-t] Error 1 > Build completed > > I checked the installation several times. The > c:/altera/quartus51/sopc_builder/bin/sopc_builder definitely > exists there. I looked at the makefiles but found no > solution there. Somehow the makefile is not able to call > sopc_builder. I use Quartus 5.1 and Windows XP. Thanks > in advance for any hint. > > Michael > >Article: 92755
Thomas Entner wrote: > Hi Michael, > > a problem I had long time ago was that I had "non-standard" characters like > ² oder German "Umlaute" in the "/Users/link/". Can't remember the errors I > got but maybe it is the same problem... Thanks Thomas for the reply. That is true and the reason why the kit may not be installed in "c:program files" because there is a blank in. I already had to reinstall everything because of this. Grrr. I will check if there is still a similar problem elsewhere. Michael.Article: 92756
Hi, I need a link to a free VHDL SPI core to deal with a temp sensor in serial mode. Thanks for your help. MarcoArticle: 92757
Hi Jim, I disagree with your opinion: "You should be aware that 'Clarity' and 'Patent' are often mutually exclusive". I found that a Xilinx patent defines a 1-bit CPU that is capable to do addition, subtraction and multiplication. While doing addition and subtranction, the patent correctly lists its equation. But in claim area, it describes it in a XOR and inverter to describe the adder/subtractor. I found that I cannot change the equation for the LUT, but it is easy for me to change the logic to another logic implementing same equation. That is the reason why I want to use logical equation in claims, not gate circuit descriptions. For example, you can concisely describe an addition/subtraction with a logical equation, but there are many different logical circuits to implement the same equation. Weng Jim Granville wrote: > Weng Tianxiang wrote: > > Hi, > > I am writing a patent application for FPGA and have no prior > > experiences with patent writing. > > > > I found that in Xilinx patents, all lookup table equations are > > described in AND/OR/Multiplexer circuits in its claims. Describing a > > logic connection for a lookup table in claims is much more complex in > > English than presenting an equivalent logic equation. > > > > For example, a lookup table has the equation: > > Out <= (A*B) + (C*D); > > > > It is much more concise and simpler than describing the circuit in > > AND/OR gate circuits. > > > > Do you have experiences with and any advices on writing an equivalent > > logic equation in a patent claim field ? > > You should be aware that 'Clarity' and 'Patent' are often mutually > exclusive :) > Patent lawyers have motivation to obfuscate, for many reasons. > Patents are merely a license to litigate, (and an income stream for the > lawyer) so they tend to break them into many small claims, that can be > argued. > If there is prior art, it also helps to sound a lot different, even if > you are the same. > This also helps to get over the first hurdle, of Patent examiner. > > Most (all?) FPGA patents will be electronic searchable, so scan those > yourself, and then "work your claim into the gaps" between those patents. > > -jgArticle: 92758
glen herrmannsfeldt wrote: > porterboy76@yahoo.com wrote: > > > I am looking for the homepage of Xilinx Research Labs, but Google is > > not helping me. Does anybody know if they even have a homepage. I'd > > like to know what type of research they do at Xilinx, whether it is all > > at the solid state and IC level, or whether they undertake higher level > > algorithmic research as well. > > Post to comp.arch.fpga and ask there. > > -- glenArticle: 92759
porterboy76@yahoo.com a écrit : > glen herrmannsfeldt wrote: > >>porterboy76@yahoo.com wrote: >> >> >>>I am looking for the homepage of Xilinx Research Labs, but Google is >>>not helping me. Does anybody know if they even have a homepage. Hi, They used to have one (well, Satnam Singh had his page until he left Xilinx). >>> I'd like to know what type of research they do at Xilinx, whether it is all >>>at the solid state and IC level, or whether they undertake higher level >>>algorithmic research as well. From what I know (i.e. academic perspective) Xilinx folks mostly focus on higher level problems (system level design, hardware compilation, runtime reconfiguration, etc.). If you want to have more details have a look to some FPGA related academic conference proceedings such as FPL or FCCM, you will probably find some papers by people from Xilinx. Besides, I am sure that Peter Alfke and Austin Lesea will be glad to answer your questions. >> >>Post to comp.arch.fpga and ask there. >> >>-- glen > >Article: 92760
Xilinx Research Labs - has an internal webpage (visible only to Xilinx employees on our network). All of the information therein is marked confidential. If you have interest in applying for employment (summer intern, or regular position) with Xilinx, please forward your resume to our website HR links. Or, you may send it to me, and I will forward it to the appropriate person. Please do not send anything if a position is not already open (ie posted) on the website. If you are associated with a school, university, or other research lab and wish to join us in research, obtain hardware or software; please contact: http://www.xilinx.com/univ/ (xup@xilinx.com) Thank you for considering Xilinx, Austin porterboy76@yahoo.com wrote: > glen herrmannsfeldt wrote: > >>porterboy76@yahoo.com wrote: >> >> >>>I am looking for the homepage of Xilinx Research Labs, but Google is >>>not helping me. Does anybody know if they even have a homepage. I'd >>>like to know what type of research they do at Xilinx, whether it is all >>>at the solid state and IC level, or whether they undertake higher level >>>algorithmic research as well. >> >>Post to comp.arch.fpga and ask there. >> >>-- glen > >Article: 92761
paddy3118@netscape.net wrote: f'up to comp.lang.vhdl > I got thinking about recursive design of circuits in VHDL I created a > recursive circuit Hmm .. what do you mean with "recursive circuit"? Eighter the transistors / cells / macroblocks are implemented or not. You may design a component, that is used by a controller (like a FSM), that realizes a recursive algorithm, but then not the circuit is recursive - only the algorithm is. > When this gets synthesized and layed out I guess that the regularity is > lost unless layed out by hand. Why do you care about regularity of the layout of a digital circuit? Except for signal delays there is no reason to think about the layout - AFAIK. A HDL is such a wounderful thing, that seperates layout problems from functional behavoir. RalfArticle: 92762
In fact the problem was with Chipscope server, when I tryed to launch
it, it gace the following message:
----DEGIN----
cs_server.sh
/opt/Xilinx/ISE7.1
application-specific initialization failed: Can't find a usable
init.tcl in the following directories:
/usr/local/lib/tcl8.4 /opt/Xilinx/chipscope/bin/lib/tcl8.4
/opt/Xilinx/chipscope/lib/tcl8.4 /opt/Xilinx/chipscope/bin/library
/opt/Xilinx/chipscope/library /opt/Xilinx/chipscope/tcl8.4.3/library
/opt/Xilinx/tcl8.4.3/library /usr/local/lib/tcl8.4
This probably means that Tcl wasn't installed properly.
CS%
/opt/Xilinx/chipscope/bin/lin/cs_server.sh: line 26: 4504 Segmentation
fault cse $args
----END----
The solution was to copy the tcl8.4 directory (from the
$CHIPSCOPE/bin/lin/xilinx/bin/lib/tcl8.4) to /usr/local/lib ... after
that all was normal. I don't undestand why I had such an error, even
changing the environment variables (LD_LIBRARY_PATH, PATH, XILINX,
CHIPSCOPE) didn't change the error messages displayed by the server,
this means that the paths are hard coded and don't use environment
variables, very strange for me to see this kind of errors from Xilinx.
Article: 92763Hello everyone and happy holidays. But for me, I am stuck with something that I think is not working. Ive got an XUP virtex2 pro board from digilent. I have also read that the board contains an embedded USB platform downloader and that this JTAG downloader should be compatible with chipscope. In my case, I went on and tried it with the evaluation version of chipscope that Xilinx is giving online. Impact reports properly the JTAG chain and enumerates properly the three components in that chain, through the platform usb cable. I tried to download a bitfile to the board and it works very well. But there are two bugs that I noticed. When I try to do a readback of the XCF32 configuration memory, impact blocks. When I try to use chipscope, it fails and does not detect any devices. I think i tried everywhere for a solution, on xilinx website, here, and on google. Now, as far as i remember, there was a point when impact did an update of the firmware for the platform usb's CPLD. My questions are: Does xilinx provides a link to the latest firmware? Is XUP V2Pro 's platform USB compatible with chipscope 7.1? Are there any issues with these two systems? Finally, can anyone suggest me a solution. If anyone has got the same problems? Thanks guys JAArticle: 92764
Are you using the latest ISE/Chipscope service packs? I'm pretty sure they are required. What operating system are you running? Paul jaxato@gmail.com wrote: > > Hello everyone and happy holidays. > > But for me, I am stuck with something that I think is not working. Ive > got an XUP virtex2 pro board from digilent. I have also read that the > board contains an embedded USB platform downloader and that this JTAG > downloader should be compatible with chipscope. In my case, I went on > and tried it with the evaluation version of chipscope that Xilinx is > giving online. > > Impact reports properly the JTAG chain and enumerates properly the > three components in that chain, through the platform usb cable. I tried > to download a bitfile to the board and it works very well. But there > are two bugs that I noticed. > > When I try to do a readback of the XCF32 configuration memory, impact > blocks. > When I try to use chipscope, it fails and does not detect any devices. > > I think i tried everywhere for a solution, on xilinx website, here, and > on google. > > Now, as far as i remember, there was a point when impact did an update > of the firmware for the platform usb's CPLD. > > My questions are: > > Does xilinx provides a link to the latest firmware? > Is XUP V2Pro 's platform USB compatible with chipscope 7.1? > Are there any issues with these two systems? > Finally, can anyone suggest me a solution. If anyone has got the same > problems? > > Thanks guys > JAArticle: 92765
Austin Lesea wrote² : > > If you are associated with a school, university, or other research lab > and wish to join us in research Hi, I had a glance to the XUP webpage, but it mostly focus on teaching resources. Let's say "I have a friend of mine" ;) who is an academic considering going for a sabbatical, and who would be *very* interested to join Xilinx Labs during that time, should I also go through this channel ? Thanks in advance, Steven >, obtain hardware or software; please > contact: > > http://www.xilinx.com/univ/ > > (xup@xilinx.com) > > Thank you for considering Xilinx, > > Austin >Article: 92766
Simon Peacock wrote: > You may want to check the stockings by the fireplace. > > Simon > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dn20o1$t57$1@online.de... > >>ISE 8.1 release was planned for mid nov, now its mid december soon, I > > wonder... I got 8.1 this morning by electronic delivery. I haven't tried installing it yet. I'll wait till I have the current projects out of the way before subjecting myself to being a guinea pig again.Article: 92767
Brian Drummond wrote: >>A couple of possibilities: >> First, check to make sure you don't have a C port conflict. The two >>DSP-48's in a single DSP48 slice share the C-Port, so either both must >>use the same value on the CPort, or one must not use the CPort. The >>software looks for a specific combination of controls for the CPort to >>flag it as unused. If you don't match the template, it may not allow >>the two DSP48's to occupy the same slice. > > > Thanks Ray, you were spot on; this was it! I still don't know where to > look for the template, because I am letting the synthesis tools infer > the slice usage. > Brian, Not sure for an inference template. The magic incantation I referred to is documented in v2.0.1 of the V4 DSP guide (oct 18,2005) at the bottom of page 26. I don't believe it was documented in the earlier versions of the guide. This is one of those things that if you want any control over the design, you are better off instantiating the DSP48s. Of course that makes your code less portable. The problem with inferring them is the behavior can change drastically between versions and vendors of the synthesis tools.Article: 92768
Austin, FWIW, there is fairly low complexity work-around for the FIFOs that can be made to come at least close to the FIFO16 maximum performance. It involves operating the FIFO16 as a synchronous FIFO with one side clocked by the rising edge and one side with the falling edge of the same clock. This is cascaded with a small coregen async fifo. The small (15 deep) async FIFO can be made to run at the max FIFO16 speed with some minor modifications and/or floorplanning around the flag counters. This looks like it will completely avoid the potential flag issues in the FIFO16 for both async and sync operation. For synchronous use, the FIFO16 can be clocked by opposite edges of the same clock, which is fine for lower performance designs. For high speed designs, either use the above async fifo clocked on the FIFO16 side by the falling edge of the fifo clock, or use a double rank register with the first rank clocked by the rising edge, passing data to the second rank which is clocked by the falling edge, which then passes the data onto the write side of the fifo16. Placing the register ranks in adjacent columns will meet the max timing of the fifo16 without the hit you'd normally get by running one side on the negative clock. I passed this solution on to your applications folks through Jim Simkins. Hopefully it will make it into an app-note or answer record as a work-around.Article: 92769
Hello, For your info, here's my current system: XP SP2, ISE7.1.04i, chipscope 7.1i First, I really think that the JTAG interface of ISE and Chipscope are different, as downloading a bit file works when I use impact. For impact does not work when I try to do a readback on the XCF32 chip. But the problem with chipscope is different. It simply does not detect any device in my JTAG chain at all. So ive got the updates intalled and got the latest version of chipscope. Any suggestions? Thanks JA Paul Hartke wrote: > Are you using the latest ISE/Chipscope service packs? I'm pretty sure > they are required. What operating system are you running? Paul > > jaxato@gmail.com wrote: > > > > Hello everyone and happy holidays. > > > > But for me, I am stuck with something that I think is not working. Ive > > got an XUP virtex2 pro board from digilent. I have also read that the > > board contains an embedded USB platform downloader and that this JTAG > > downloader should be compatible with chipscope. In my case, I went on > > and tried it with the evaluation version of chipscope that Xilinx is > > giving online. > > > > Impact reports properly the JTAG chain and enumerates properly the > > three components in that chain, through the platform usb cable. I tried > > to download a bitfile to the board and it works very well. But there > > are two bugs that I noticed. > > > > When I try to do a readback of the XCF32 configuration memory, impact > > blocks. > > When I try to use chipscope, it fails and does not detect any devices. > > > > I think i tried everywhere for a solution, on xilinx website, here, and > > on google. > > > > Now, as far as i remember, there was a point when impact did an update > > of the firmware for the platform usb's CPLD. > > > > My questions are: > > > > Does xilinx provides a link to the latest firmware? > > Is XUP V2Pro 's platform USB compatible with chipscope 7.1? > > Are there any issues with these two systems? > > Finally, can anyone suggest me a solution. If anyone has got the same > > problems? > > > > Thanks guys > > JAArticle: 92770
It doesn't look like you are using the Chipscope service pack; I think that is required. The latest is 7.1.04i. I've never done a readback of the XCF32 myself. Just curious, why do you want to do a readback? Paul jaxato@gmail.com wrote: > > Hello, > > For your info, here's my current system: > > XP SP2, ISE7.1.04i, chipscope 7.1i > > First, I really think that the JTAG interface of ISE and Chipscope are > different, as downloading a bit file works when I use impact. For > impact does not work when I try to do a readback on the XCF32 chip. But > the problem with chipscope is different. It simply does not detect any > device in my JTAG chain at all. > So ive got the updates intalled and got the latest version of > chipscope. > > Any suggestions? > > Thanks > JA > > Paul Hartke wrote: > > Are you using the latest ISE/Chipscope service packs? I'm pretty sure > > they are required. What operating system are you running? Paul > > > > jaxato@gmail.com wrote: > > > > > > Hello everyone and happy holidays. > > > > > > But for me, I am stuck with something that I think is not working. Ive > > > got an XUP virtex2 pro board from digilent. I have also read that the > > > board contains an embedded USB platform downloader and that this JTAG > > > downloader should be compatible with chipscope. In my case, I went on > > > and tried it with the evaluation version of chipscope that Xilinx is > > > giving online. > > > > > > Impact reports properly the JTAG chain and enumerates properly the > > > three components in that chain, through the platform usb cable. I tried > > > to download a bitfile to the board and it works very well. But there > > > are two bugs that I noticed. > > > > > > When I try to do a readback of the XCF32 configuration memory, impact > > > blocks. > > > When I try to use chipscope, it fails and does not detect any devices. > > > > > > I think i tried everywhere for a solution, on xilinx website, here, and > > > on google. > > > > > > Now, as far as i remember, there was a point when impact did an update > > > of the firmware for the platform usb's CPLD. > > > > > > My questions are: > > > > > > Does xilinx provides a link to the latest firmware? > > > Is XUP V2Pro 's platform USB compatible with chipscope 7.1? > > > Are there any issues with these two systems? > > > Finally, can anyone suggest me a solution. If anyone has got the same > > > problems? > > > > > > Thanks guys > > > JAArticle: 92771
I'd like to get 2 circuits programmed into FPGA $500 per board. this is an OLD circuit (1970's), so it shouldn't be difficult for an FPGA programmer to implement. This would hopefully include PCB layout. For S100 bus I pay for the finished product. aiiadict AT gmail DOT calm yeah, calm = comArticle: 92772
Hello Paul. That was it for chipscope, now ive got 60 days to try it. I was afraid that my USB platform configurator was damaged or something. But it turned out that the latest update did it. I was under the false impression that I had the latest chipscope version, but again, It was a question of upgrading it. As for the readback, I am very software oriented and I think this pushes me to try things out. So I tried to readback the XCF32 chip. Which deadlocked Impact. Any clues about this? Thanks alot anyways! Merry xmas! JAArticle: 92773
Hi, The ChipScope 7.1 (no service pack version) opens the Platform USB cable at the highest speed by default. This is too fast for many boards. Try selecting a lower speed. Later ChipScope 7.1 service packs, has a lower default speed setting for the Platform USB cable. / Jan Paul Hartke wrote: >It doesn't look like you are using the Chipscope service pack; I think >that is required. The latest is 7.1.04i. > >I've never done a readback of the XCF32 myself. Just curious, why do >you want to do a readback? > >Paul > >jaxato@gmail.com wrote: > > >>Hello, >> >>For your info, here's my current system: >> >>XP SP2, ISE7.1.04i, chipscope 7.1i >> >>First, I really think that the JTAG interface of ISE and Chipscope are >>different, as downloading a bit file works when I use impact. For >>impact does not work when I try to do a readback on the XCF32 chip. But >>the problem with chipscope is different. It simply does not detect any >>device in my JTAG chain at all. >>So ive got the updates intalled and got the latest version of >>chipscope. >> >>Any suggestions? >> >>Thanks >>JA >> >>Paul Hartke wrote: >> >> >>>Are you using the latest ISE/Chipscope service packs? I'm pretty sure >>>they are required. What operating system are you running? Paul >>> >>>jaxato@gmail.com wrote: >>> >>> >>>>Hello everyone and happy holidays. >>>> >>>>But for me, I am stuck with something that I think is not working. Ive >>>>got an XUP virtex2 pro board from digilent. I have also read that the >>>>board contains an embedded USB platform downloader and that this JTAG >>>>downloader should be compatible with chipscope. In my case, I went on >>>>and tried it with the evaluation version of chipscope that Xilinx is >>>>giving online. >>>> >>>>Impact reports properly the JTAG chain and enumerates properly the >>>>three components in that chain, through the platform usb cable. I tried >>>>to download a bitfile to the board and it works very well. But there >>>>are two bugs that I noticed. >>>> >>>>When I try to do a readback of the XCF32 configuration memory, impact >>>>blocks. >>>>When I try to use chipscope, it fails and does not detect any devices. >>>> >>>>I think i tried everywhere for a solution, on xilinx website, here, and >>>>on google. >>>> >>>>Now, as far as i remember, there was a point when impact did an update >>>>of the firmware for the platform usb's CPLD. >>>> >>>>My questions are: >>>> >>>>Does xilinx provides a link to the latest firmware? >>>>Is XUP V2Pro 's platform USB compatible with chipscope 7.1? >>>>Are there any issues with these two systems? >>>>Finally, can anyone suggest me a solution. If anyone has got the same >>>>problems? >>>> >>>>Thanks guys >>>>JA >>>> >>>>Article: 92774
aiiadict@gmail.com wrote: > I'd like to get 2 circuits programmed into FPGA > > $500 per board. > > this is an OLD circuit (1970's), so it shouldn't be difficult > for an FPGA programmer to implement. > > This would hopefully include PCB layout. > > For S100 bus > > I pay for the finished product. > > aiiadict AT gmail DOT calm > > yeah, calm = com I'm just being curious, but what does the board and FPGA need to do? -Dave Pollum
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