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Messages from 147975

Article: 147975
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: "BrandonD" <BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Wed, 09 Jun 2010 11:45:53 -0500
Links: << >>  << T >>  << A >>
By being familiar with synthesis, I mean I'm a student and have had some
coursework with the design and synthesis, but projects ended there. To be
honest, they were more on the design aspect so I am familiar with the
synthesis process but not too experienced with it.

I do not use any gated clocks and all of my sequential logic runs of the
same edge of the same 50 MHz clock except for the reset logic when the DCM
is stabilizing. 

I have not set any OFFSET IN/OUT constraints, do you know where I can get
more information about doing that?

Thanks,
Brandon

>On 6/9/2010 8:01 AM, BrandonD wrote:
>> Hi,
>>
>> I'm somewhat familiar with synthesis and Verilog but I am quite new to
>> running the designs on FPGAs. I have a complex design of a processor
that I
>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
design
>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1
but
>> it does not seem to run correctly when programmed on the FPGA.
>>
>> ISE says that all timing constraints have been met and the static
timing
>> report shows that it does too. What I am going to do now is look at the
>> post-par simulation and see if there's a problem. Is there anything
that
>> maybe is a common mistake that I should also look into?
>>
>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.
Any
>> suggestions will be appreciated.
>>
>> Thanks,
>> Brandon
>>
>> 	
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
>
>Anything other than single clock synchronous logic isn't represented in 
>your timing constraints; so anywhere that you're using a clock other 
>than your derived 50 is worth another look.  This includes any logic 
>running off of a combinationally gated clock.  You said you're used to 
>synthesis but not FPGAs; if that means ASICs then one thing to be aware 
>of is that clock nets are a lot more sacred in FPGAs.
>
>Unless you've specified your external OFFSET IN/OUT constraints properly 
>(this is rare), then your constraints don't properly cover your 
>relationships to external hardware.  Worth another look.
>
>-- 
>Rob Gaddi, Highland Technology
>Email address is currently out of order
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 147976
Subject: Re: How to Disable IP Core after Evaluation Period
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 9 Jun 2010 18:37:22 +0000 (UTC)
Links: << >>  << T >>  << A >>
Anssi Saari <as@sci.fi> wrote:
 
>> Sudhir Singh <Sudhir.Singh@email.com> wrote:
  
>>> I am just wondering if there are any standard ways of disabling an ip
>>> core after an evaluation period of say 30 days. I am trying to provide
>>> a potential customer a ip core  but don't want them to continue using
>>> it after the eval license period expires. The core will run on Xilinx
>>> Spartan3 FPGAs.

(then I wrote)

>> Considering the ability to change the date on the computer,
>> it is pretty hard to stop people from using something past 
>> a given date.   Once the bit file is generated, it is pretty
>> much impossible.
 
> Well, at least the licensable Xilinx IP I've used included some kind
> of timer in the bitfile itself if there's no license, so that the
> block works for a few hours and then quits. 

Yes, I had forgotten about the ones that count clock cycles.
But that doesn't help if you want a specific time or date.

Even so, one could probably find a way to disable the counter.
(I don't know if reset will reset the counter or not, otherwise
one can always reload the device.)

I was unsure from your original post if you meant the ability
to generate bitfiles, or the ability to use them.

If the device has internet access, you could use an NTP server
to get the date/time.  That would take a lot of logic, though!

-- glen



Article: 147977
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: "BrandonD" <BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Wed, 09 Jun 2010 14:15:40 -0500
Links: << >>  << T >>  << A >>
By being familiar with synthesis, I mean I'm a student and have had some
coursework with the design and synthesis, but projects ended there. To be
honest, they were more on the design aspect so I am familiar with the
synthesis process but not too experienced with it.

I do not use any gated clocks and all of my sequential logic runs of the
same edge of the same 50 MHz clock except for the reset logic when the DCM
is stabilizing. 

I have not set any OFFSET IN/OUT constraints, do you know where I can get
more information about doing that?

Thanks,
Brandon

>On 6/9/2010 8:01 AM, BrandonD wrote:
>> Hi,
>>
>> I'm somewhat familiar with synthesis and Verilog but I am quite new to
>> running the designs on FPGAs. I have a complex design of a processor
that I
>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
design
>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1
but
>> it does not seem to run correctly when programmed on the FPGA.
>>
>> ISE says that all timing constraints have been met and the static
timing
>> report shows that it does too. What I am going to do now is look at the
>> post-par simulation and see if there's a problem. Is there anything
that
>> maybe is a common mistake that I should also look into?
>>
>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.
Any
>> suggestions will be appreciated.
>>
>> Thanks,
>> Brandon
>>
>> 	
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
>
>Anything other than single clock synchronous logic isn't represented in 
>your timing constraints; so anywhere that you're using a clock other 
>than your derived 50 is worth another look.  This includes any logic 
>running off of a combinationally gated clock.  You said you're used to 
>synthesis but not FPGAs; if that means ASICs then one thing to be aware 
>of is that clock nets are a lot more sacred in FPGAs.
>
>Unless you've specified your external OFFSET IN/OUT constraints properly 
>(this is rare), then your constraints don't properly cover your 
>relationships to external hardware.  Worth another look.
>
>-- 
>Rob Gaddi, Highland Technology
>Email address is currently out of order
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 147978
Subject: Re: How to Disable IP Core after Evaluation Period
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 9 Jun 2010 20:18:41 GMT
Links: << >>  << T >>  << A >>
On Tue, 08 Jun 2010 16:53:43 -0700, Sudhir Singh wrote:

> Hi Guys,
> 
> I am just wondering if there are any standard ways of disabling an ip
> core after an evaluation period of say 30 days. I am trying to provide a
> potential customer a ip core  but don't want them to continue using it
> after the eval license period expires. The core will run on Xilinx
> Spartan3 FPGAs.
> 
> Any suggestions will be much appreciated.
> 
> Regards
> Sudhir

Xilinx doesn't have a mechanism yet for generating an IP license, they 
plan to have one that uses a new IEEE standard but that won't happen for 
a year.

Altera does have tools that allow you to encrypt your source code and 
then generate a flexlm license that can restrict the type of FPGA it can 
go into, allow simulation only or just synthesis, and the time limits for 
the IP. However once you've generated a bit file it's good forever, there 
is no way to have a bit file that's time limited.

Article: 147979
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: Gabor <gabor@alacron.com>
Date: Wed, 9 Jun 2010 15:05:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 9, 12:45=A0pm, "BrandonD"
<BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> By being familiar with synthesis, I mean I'm a student and have had some
> coursework with the design and synthesis, but projects ended there. To be
> honest, they were more on the design aspect so I am familiar with the
> synthesis process but not too experienced with it.
>
> I do not use any gated clocks and all of my sequential logic runs of the
> same edge of the same 50 MHz clock except for the reset logic when the DC=
M
> is stabilizing.
>
> I have not set any OFFSET IN/OUT constraints, do you know where I can get
> more information about doing that?
>
> Thanks,
> Brandon
>
>
>
>
>
> >On 6/9/2010 8:01 AM, BrandonD wrote:
> >> Hi,
>
> >> I'm somewhat familiar with synthesis and Verilog but I am quite new to
> >> running the designs on FPGAs. I have a complex design of a processor
> that I
> >> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
> design
> >> synthesizes and goes through translate, map and par in Xilinx ISE 10.1
> but
> >> it does not seem to run correctly when programmed on the FPGA.
>
> >> ISE says that all timing constraints have been met and the static
> timing
> >> report shows that it does too. What I am going to do now is look at th=
e
> >> post-par simulation and see if there's a problem. Is there anything
> that
> >> maybe is a common mistake that I should also look into?
>
> >> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.
> Any
> >> suggestions will be appreciated.
>
> >> Thanks,
> >> Brandon
>
> >> --------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0
> >> Posted throughhttp://www.FPGARelated.com
>
> >Anything other than single clock synchronous logic isn't represented in
> >your timing constraints; so anywhere that you're using a clock other
> >than your derived 50 is worth another look. =A0This includes any logic
> >running off of a combinationally gated clock. =A0You said you're used to
> >synthesis but not FPGAs; if that means ASICs then one thing to be aware
> >of is that clock nets are a lot more sacred in FPGAs.
>
> >Unless you've specified your external OFFSET IN/OUT constraints properly
> >(this is rare), then your constraints don't properly cover your
> >relationships to external hardware. =A0Worth another look.
>
> >--
> >Rob Gaddi, Highland Technology
> >Email address is currently out of order
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

You may want to look at the "blogs" section of the Xilinx
web forums.  There is a 5-part piece on timing constraints
that is quite useful when you're getting started.

Also if you have severe problems, like it looks like
nothing works at all, you could have a loop in the
reset generation logic.  Remember that the output of
a DCM does not toggle until locked, so using it to
release reset to the DCM will lock up the system
because the reset prevents the DCM from locking.

Regards,
Gabor

Article: 147980
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Wed, 09 Jun 2010 15:11:04 -0700
Links: << >>  << T >>  << A >>
On 6/9/2010 9:45 AM, BrandonD wrote:
> By being familiar with synthesis, I mean I'm a student and have had some
> coursework with the design and synthesis, but projects ended there. To be
> honest, they were more on the design aspect so I am familiar with the
> synthesis process but not too experienced with it.
>
> I do not use any gated clocks and all of my sequential logic runs of the
> same edge of the same 50 MHz clock except for the reset logic when the DCM
> is stabilizing.
>
> I have not set any OFFSET IN/OUT constraints, do you know where I can get
> more information about doing that?
>
> Thanks,
> Brandon
>
>> On 6/9/2010 8:01 AM, BrandonD wrote:
>>> Hi,
>>>
>>> I'm somewhat familiar with synthesis and Verilog but I am quite new to
>>> running the designs on FPGAs. I have a complex design of a processor
> that I
>>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
> design
>>> synthesizes and goes through translate, map and par in Xilinx ISE 10.1
> but
>>> it does not seem to run correctly when programmed on the FPGA.
>>>
>>> ISE says that all timing constraints have been met and the static
> timing
>>> report shows that it does too. What I am going to do now is look at the
>>> post-par simulation and see if there's a problem. Is there anything
> that
>>> maybe is a common mistake that I should also look into?
>>>
>>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz clock.
> Any
>>> suggestions will be appreciated.
>>>
>>> Thanks,
>>> Brandon
>>>
>>> 	
>>> 					
>>> ---------------------------------------		
>>> Posted through http://www.FPGARelated.com
>>
>> Anything other than single clock synchronous logic isn't represented in
>> your timing constraints; so anywhere that you're using a clock other
>> than your derived 50 is worth another look.  This includes any logic
>> running off of a combinationally gated clock.  You said you're used to
>> synthesis but not FPGAs; if that means ASICs then one thing to be aware
>> of is that clock nets are a lot more sacred in FPGAs.
>>
>> Unless you've specified your external OFFSET IN/OUT constraints properly
>> (this is rare), then your constraints don't properly cover your
>> relationships to external hardware.  Worth another look.
>>
>> --
>> Rob Gaddi, Highland Technology
>> Email address is currently out of order
>> 	
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

I hope this is a stupid question but....it does simulate correctly, right?

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 147981
Subject: Re: How to Disable IP Core after Evaluation Period
From: Gabor <gabor@alacron.com>
Date: Wed, 9 Jun 2010 15:12:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 9, 2:37=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Anssi Saari <a...@sci.fi> wrote:
> >> Sudhir Singh <Sudhir.Si...@email.com> wrote:
> >>> I am just wondering if there are any standard ways of disabling an ip
> >>> core after an evaluation period of say 30 days. I am trying to provid=
e
> >>> a potential customer a ip core =A0but don't want them to continue usi=
ng
> >>> it after the eval license period expires. The core will run on Xilinx
> >>> Spartan3 FPGAs.
>
> (then I wrote)
>
> >> Considering the ability to change the date on the computer,
> >> it is pretty hard to stop people from using something past
> >> a given date. =A0 Once the bit file is generated, it is pretty
> >> much impossible.
> > Well, at least the licensable Xilinx IP I've used included some kind
> > of timer in the bitfile itself if there's no license, so that the
> > block works for a few hours and then quits.
>
> Yes, I had forgotten about the ones that count clock cycles.
> But that doesn't help if you want a specific time or date.
>
> Even so, one could probably find a way to disable the counter.
> (I don't know if reset will reset the counter or not, otherwise
> one can always reload the device.)
>
> I was unsure from your original post if you meant the ability
> to generate bitfiles, or the ability to use them.
>
> If the device has internet access, you could use an NTP server
> to get the date/time. =A0That would take a lot of logic, though!
>
> -- glen

Where I have seen evaluation versions of IP with hardware time
limits, the clock cycles they count are internal to the core
and generated with a ring oscillator to prevent reset without
re-configuration.  If your system can live with periodic
reconfiguration, then obviously this method can be bypassed
as well.

Regards,
Gabor

Article: 147982
Subject: Re: How to Disable IP Core after Evaluation Period
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 9 Jun 2010 23:39:42 +0000 (UTC)
Links: << >>  << T >>  << A >>
Gabor <gabor@alacron.com> wrote:
(snip)
 
> Where I have seen evaluation versions of IP with hardware time
> limits, the clock cycles they count are internal to the core
> and generated with a ring oscillator to prevent reset without
> re-configuration.  If your system can live with periodic
> reconfiguration, then obviously this method can be bypassed
> as well.

Some devices naturally need a clock.  I thought I remembered
this test on an ethernet MAC, which would be pretty hard to use
without a clock.  

On the other hand, how hard is it to find the carry chains in
a design?  If you can find the counter, it probably isn't so
hard to disable it without doing anything else to the design.

-- glen

Article: 147983
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: "BrandonD" <BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 10 Jun 2010 01:47:48 -0500
Links: << >>  << T >>  << A >>
It does simulate behaviorally correctly. I forgot to mention that part.

You were right about the loop of the reset signal back to the DCM. I did
exactly that. I've fixed that problem and it still appears to be working
incorrectly. I am going to try post-par simulation to see how that looks. 

I will read up on the constraints as well.


>On 6/9/2010 9:45 AM, BrandonD wrote:
>> By being familiar with synthesis, I mean I'm a student and have had
some
>> coursework with the design and synthesis, but projects ended there. To
be
>> honest, they were more on the design aspect so I am familiar with the
>> synthesis process but not too experienced with it.
>>
>> I do not use any gated clocks and all of my sequential logic runs of
the
>> same edge of the same 50 MHz clock except for the reset logic when the
DCM
>> is stabilizing.
>>
>> I have not set any OFFSET IN/OUT constraints, do you know where I can
get
>> more information about doing that?
>>
>> Thanks,
>> Brandon
>>
>>> On 6/9/2010 8:01 AM, BrandonD wrote:
>>>> Hi,
>>>>
>>>> I'm somewhat familiar with synthesis and Verilog but I am quite new
to
>>>> running the designs on FPGAs. I have a complex design of a processor
>> that I
>>>> am trying to get running on a Virtex 5 FPGA in a BEE3 module. The
>> design
>>>> synthesizes and goes through translate, map and par in Xilinx ISE
10.1
>> but
>>>> it does not seem to run correctly when programmed on the FPGA.
>>>>
>>>> ISE says that all timing constraints have been met and the static
>> timing
>>>> report shows that it does too. What I am going to do now is look at
the
>>>> post-par simulation and see if there's a problem. Is there anything
>> that
>>>> maybe is a common mistake that I should also look into?
>>>>
>>>> I am using a DCM to turn the 100 MHz system clock into a 50 MHz
clock.
>> Any
>>>> suggestions will be appreciated.
>>>>
>>>> Thanks,
>>>> Brandon
>>>>
>>>> 	
>>>> 					
>>>> ---------------------------------------		
>>>> Posted through http://www.FPGARelated.com
>>>
>>> Anything other than single clock synchronous logic isn't represented
in
>>> your timing constraints; so anywhere that you're using a clock other
>>> than your derived 50 is worth another look.  This includes any logic
>>> running off of a combinationally gated clock.  You said you're used to
>>> synthesis but not FPGAs; if that means ASICs then one thing to be
aware
>>> of is that clock nets are a lot more sacred in FPGAs.
>>>
>>> Unless you've specified your external OFFSET IN/OUT constraints
properly
>>> (this is rare), then your constraints don't properly cover your
>>> relationships to external hardware.  Worth another look.
>>>
>>> --
>>> Rob Gaddi, Highland Technology
>>> Email address is currently out of order
>>> 	
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
>
>I hope this is a stupid question but....it does simulate correctly,
right?
>
>-- 
>Rob Gaddi, Highland Technology
>Email address is currently out of order
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 147984
Subject: Re: How to Disable IP Core after Evaluation Period
From: Sudhir Singh <Sudhir.Singh@email.com>
Date: Thu, 10 Jun 2010 00:07:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 10, 11:39=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
> Gabor <ga...@alacron.com> wrote:
>
> (snip)
>
> > Where I have seen evaluation versions of IP with hardware time
> > limits, the clock cycles they count are internal to the core
> > and generated with a ring oscillator to prevent reset without
> > re-configuration. =A0If your system can live with periodic
> > reconfiguration, then obviously this method can be bypassed
> > as well.
>
> Some devices naturally need a clock. =A0I thought I remembered
> this test on an ethernet MAC, which would be pretty hard to use
> without a clock. =A0
>
> On the other hand, how hard is it to find the carry chains in
> a design? =A0If you can find the counter, it probably isn't so
> hard to disable it without doing anything else to the design.
>
> -- glen


Hi Guys,

Thanks for your replies. I think counting clock cycles will be a
viable option for me.

Cheers
Sudhir

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From: Matthieu Michon <prenom.nom@gmail.com>
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Subject: Re: Design passes synthesis and routing but fails on FPGA
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On Wed, 9 Jun 2010 15:05:23 -0700 (PDT)
Gabor <gabor@alacron.com> wrote:

(...)
> Also if you have severe problems, like it looks like
> nothing works at all, you could have a loop in the
> reset generation logic.  Remember that the output of
> a DCM does not toggle until locked, so using it to
> release reset to the DCM will lock up the system
> because the reset prevents the DCM from locking.
> 
> Regards,
> Gabor


To follow on with the DCM feature, performing an initial DCM reset with the timings in compliance with the user-guide and datasheet is a must (with special care when dealing with early Virtex-4 revisions, altough it is not the case here).


I suggest to the OP that he should focus on verifying the obvious (pwr-supply levels, input clock waveform, pin-mapping, UCF file, JTAG connection, DCM lock and status outputs).

-- 
Matthieu Michon <prenom.nom@gmail.com>

Article: 147985
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Thu, 10 Jun 2010 03:24:36 -0500
Links: << >>  << T >>  << A >>
If you are convinced that your simulation of the design is correct then you
really need to use Chipscope to see what is going on inside the device. 

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 147986
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: "BrandonD" <BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 10 Jun 2010 05:28:44 -0500
Links: << >>  << T >>  << A >>
I am getting some warnings during post-par simulation that may be a clue.
When I load my routed design in Modelsim, I am getting 14 warnings like
this for different nets:

Instance 'top.fab.\fs1/ras/reset_n_inv_shift1 ' - No solution possible for
delayed timing check nets. Setting negative limit to zero.

In the static timing report for the OFFSET IN BEFORE timing constraint
(which I have not set so it must be determined by ISE) I have a total
minimum clock path delay of -0.678 ns. 

For the OFFSET OUT AFTER constraint I have a maximum clock path delay of
-0.256 ns. I wasn't sure if this meant something as the path for these
delays are from the input clock buffer to the DCM. 

I don't believe the warnings in the simulation are normal but are negative
delay values normal?

Thanks,
Brandon


>If you are convinced that your simulation of the design is correct then
you
>really need to use Chipscope to see what is going on inside the device. 
>
>Jon	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 147987
Subject: Re: Design passes synthesis and routing but fails on FPGA
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Thu, 10 Jun 2010 05:47:36 -0500
Links: << >>  << T >>  << A >>
You shouldnt really need to do a post p&r sim. I have done designs running
at > 300 MHz without a post p&r sim. As I said if you have access to
Chipscope then you really need to use it.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 147988
Subject: Alternative to Chipscope
From: apple <sys.apple2@gmail.com>
Date: Thu, 10 Jun 2010 11:13:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
I would like to have capabilities of Chipscope for Xilinx FPGA's

are there any free alternatives to it?

a.t

Article: 147989
Subject: Re: Alternative to Chipscope
From: CP <methusalem@gmail.com>
Date: Thu, 10 Jun 2010 11:55:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
have a look at this http://vmagic.sf.net and buid your own.
We have done that using matlab here, but it's in german, I'm afraid:
http://wwwhni.uni-paderborn.de/sct/projekte/hardware-in-the-loop-simulation-mit-raptor2000/hilde-offline-fpga-in-the-loop/

Article: 147990
Subject: Re: Alternative to Chipscope
From: rickman <gnuarm@gmail.com>
Date: Thu, 10 Jun 2010 14:45:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 10, 2:13=A0pm, apple <sys.app...@gmail.com> wrote:
> I would like to have capabilities of Chipscope for Xilinx FPGA's
>
> are there any free alternatives to it?

There is a poorman's FPGA debugging tool called "an I/O port".  I have
yet to learn to use chipscope or similar tools.  I have a few I/Os
available on my device which I tied to a header, often a 0.1" spaced
header with 0.025" square pins (if I have room).  I use a regular
scope or logic analyzer.  Since the number of I/Os is limited, I
typically use a mux to select which signals come to the I/O header.
Of course this has some limitations, mainly the PITA of often spinning
a new build to get the signals into the mux I want.  But that's not
really different from chipscope.  I guess they have a tool that routes
the muxed signals on your existing design using unused resources, so
in theory it doesn't disturb the design.  But I've never had a problem
where the design was sensitive to this.

If you use good techniques for designing your FPGA and do a good job
of simulating, I expect you will seldom need chipscope or similar
tools.

Rick

Article: 147991
Subject: Re: Alternative to Chipscope
From: Andy Peters <google@latke.net>
Date: Thu, 10 Jun 2010 14:51:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 10, 11:13=A0am, apple <sys.app...@gmail.com> wrote:
> I would like to have capabilities of Chipscope for Xilinx FPGA's
>
> are there any free alternatives to it?

It's actually pretty easy to write a logic analyzer core. Integrating
it into a design isn't too bad if you instantiate it in your code. But
ChipScope's Core Inserter feature is pretty great and is superior to
instantiating the core.

Writing host software to display it in a pretty manner is difficult if
you don't know how to do it.

Basically, ChipScope is one of Xilinx' shining lights, and is worth
the cost.

-a

Article: 147992
Subject: Is it possible to get consistent implementation results?
From: "BrandonD" <BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 10 Jun 2010 19:49:25 -0500
Links: << >>  << T >>  << A >>
Hi,

I'm working with Xilinx ISE 10.1 and I am having troubles with timing
constraints.

I've successfully implemented my design with a 20 ns cycle time and found
that I needed to change something in the design.

I make my changes and re-synthesize and implement design and I no longer
meet the same timing constraint. Okay, I've changed the logic slightly so
it's not going to be exactly the same, the static timing report says that I
need a minimum cycle time of say 22 ns.

So I only change the timing constraint to reflect a 25 ns and re-run the
process and it fails again saying I need a 32 ns cycle time now. Okay, so I
change the cycle time to 35 ns and then I need a 46 ns cycle time.

I think this is understandable because with a relaxed constraint some
optimizations or paths may not be chosen. When do you try it again with the
same constraint and when do you relax the constraint? 

Thanks,
Brandon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 147993
Subject: Re: Is it possible to get consistent implementation results?
From: rickman <gnuarm@gmail.com>
Date: Thu, 10 Jun 2010 18:49:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 10, 8:49=A0pm, "BrandonD"
<BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> Hi,
>
> I'm working with Xilinx ISE 10.1 and I am having troubles with timing
> constraints.
>
> I've successfully implemented my design with a 20 ns cycle time and found
> that I needed to change something in the design.
>
> I make my changes and re-synthesize and implement design and I no longer
> meet the same timing constraint. Okay, I've changed the logic slightly so
> it's not going to be exactly the same, the static timing report says that=
 I
> need a minimum cycle time of say 22 ns.
>
> So I only change the timing constraint to reflect a 25 ns and re-run the
> process and it fails again saying I need a 32 ns cycle time now. Okay, so=
 I
> change the cycle time to 35 ns and then I need a 46 ns cycle time.
>
> I think this is understandable because with a relaxed constraint some
> optimizations or paths may not be chosen. When do you try it again with t=
he
> same constraint and when do you relax the constraint?

Actually, that doesn't make sense to me since the timing constraints
are supposed to be used in routing.  From what I have seen, synthesis,
such as Synplify, is often driven by a variety of specs, but not
necessarily the "constraints" that Xilinx lets you input.  Under the
Lattice tools I have to enter a separate timing constraint to have it
sent to Synplify when I use the GUI.  Even this is just one master
clock speed and so can't have the detail to constrain the paths that
have to be fast and relax the paths that don't need to run at full
speed.  There are also settings for "optimize for speed" or "optimize
for power".

I can't imagine what is going on that a path or paths can be de-
optimized repeatedly to always be just out of reach of your timing
constraint.  Have you looked at the paths to see if it is the same
path each time?  If path A fails with a 20 ns constraint and path B
fails with a 25 ns constraint what is path B doing under the 20 ns
constraint?  How does the tool make it meet 20 ns (or maybe just under
22 ns) and be slower otherwise?  Repeat with path C under the 35 ns,
etc.  See if you can figure out what is changing in the result.  There
has to be something odd going on.

Rick

Article: 147994
Subject: Re: Is it possible to get consistent implementation results?
From: Symon <symon_brewer@hotmail.com>
Date: Fri, 11 Jun 2010 10:28:38 +0100
Links: << >>  << T >>  << A >>
On 6/11/2010 1:49 AM, BrandonD wrote:
> Hi,
>
> I'm working with Xilinx ISE 10.1 and I am having troubles with timing
> constraints.
>
> I've successfully implemented my design with a 20 ns cycle time and found
> that I needed to change something in the design.
>
Hi Brandon,
It strikes me that if you are using a modern FPGA and can't meet a 20ns 
timing constraint, you have bigger problems than Xilinx's crappy software.
However, there are folks here who are queuing up to help. Tell us which 
device you are using and a bit about the portion of your design which 
fails timing.
Once that rafter is out of the way, we can look at the straws.
Cheers, Syms.

Article: 147995
Subject: Re: Is it possible to get consistent implementation results?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Fri, 11 Jun 2010 10:40:52 +0100
Links: << >>  << T >>  << A >>
"BrandonD" <BdOn003@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> writes:

> Hi,
>
> I'm working with Xilinx ISE 10.1 and I am having troubles with timing
> constraints.
>
> I've successfully implemented my design with a 20 ns cycle time and found
> that I needed to change something in the design.
>
> I make my changes and re-synthesize and implement design and I no longer
> meet the same timing constraint. Okay, I've changed the logic slightly so
> it's not going to be exactly the same, the static timing report says that I
> need a minimum cycle time of say 22 ns.
>
> So I only change the timing constraint to reflect a 25 ns and re-run the
> process and it fails again saying I need a 32 ns cycle time now. Okay, so I
> change the cycle time to 35 ns and then I need a 46 ns cycle time.
>
> I think this is understandable because with a relaxed constraint some
> optimizations or paths may not be chosen. When do you try it again with the
> same constraint and when do you relax the constraint? 

That looks quite weird.

BUT - I'm a bit confused -why would you relax the constraint?  

You set your constraint to match the physical system you are
targetting. Unless you can change that system to match your new
constraint, you can't just go changing constraints - are you planning
to slow your clock down as well?  Or have you overconstrained the
design?

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 147996
Subject: how to interface a ddr2 memory controller to a processor
From: rana <randeelw@gmail.com>
Date: Fri, 11 Jun 2010 04:14:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi all,

i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is
16. i must provide 2, 32 bit data to the controller before writing it
to memory. As well as when reading from a memory location it gives out
2, 32 bit data out.
my processor is a master AHB, has a 32 bit address and 32 bit data
bus.
How can i connect these 2 together?
problem is ahb sends out 32 bit data but i have to write to 64 bit
data to memory.
also the burst is 4, so it will write to 2, 32 bit memory locations,
so there would be a 32 bit memory location that would be written with
redundant data(if i write 64 bit data to memory).

thank you,
randeel.

Article: 147997
Subject: Re: Alternative to Chipscope
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Fri, 11 Jun 2010 12:52:58 +0100
Links: << >>  << T >>  << A >>
"apple" <sys.apple2@gmail.com> wrote in message 
news:20d4dfc1-6146-4ae7-a050-0343f93536d2@q39g2000prh.googlegroups.com...
>I would like to have capabilities of Chipscope for Xilinx FPGA's
> are there any free alternatives to it?


Not free and not a direct alternative but I came up with a prototpype of this...

http://www.1pin-interface.com/

..for debugging my own designs. I found it invaluable for board and device debug
so produced the 1 Pin Interface.

It doesn't give you the low level logic analyser access that Chipscope does but
it works at the next layer giving you easy access to internal status or
control registers.

All that's needed is 1 FPGA IO pin and a GND.



Nial.



Article: 147998
Subject: Re: Is it possible to get consistent implementation results?
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Fri, 11 Jun 2010 12:55:09 +0100
Links: << >>  << T >>  << A >>
Answering "Is it possible to get consistent implementation results?".

Yes, if your constraints are set up properly you should get reliable
expected performance _every_ time you build the device (as long as
the constraits are met).


Nial. 



Article: 147999
Subject: Re: how to interface a ddr2 memory controller to a processor
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Fri, 11 Jun 2010 09:10:44 -0500
Links: << >>  << T >>  << A >>
You dont have to write all of the data into memory, you can use the data
masks.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com



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