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Hello,=20 For those of you who do DSP modeling in Python, I've recently released a pa= ckage that supports fixed point arithmetic. The existing open source tools = are lackluster and MATLAB doesn't nicely fit into our simulation/testing wo= rkflow. Just trying to get the word out for a higher adoption rate! Documentation is here: https://fixedpoint.readthedocs.io Gihub repo is here: https://github.com/Schweitzer-Engineering-Laboratories/fixedpoint Compatible with Python 3.8.0 and later. Install from PyPI with pip: pip install fixedpointArticle: 161701
On Wednesday, May 6, 2020 at 11:31:20 AM UTC-4, Rick C wrote: > On Wednesday, May 6, 2020 at 9:54:45 AM UTC-4, Mohammed Billoo wrote: > > Sorry, yes I meant in simulation. I imagine there are many good resources online that show how to set up a testbench for this purpose in Vivado. > > I assume Vivado is a simulation tool? That is agnostic to the issue. You simply need to learn how to use the HDL you are using. Once you know that you can write the test bench to operate the other side of the interface from the FPGA. > > What sort of interfaces do you have? It looks like there is non-synthesizable VHDL that will allow me to read in a file, convert from unsigned to a std logic vector and pass it to my module as a DUT. > > -- > > Rick C. > > + Get 1,000 miles of free Supercharging > + Tesla referral code - https://ts.la/richard11209Article: 161702
On Wednesday, May 6, 2020 at 6:50:44 PM UTC-4, Mohammed Billoo wrote: > On Wednesday, May 6, 2020 at 11:31:20 AM UTC-4, Rick C wrote: > > On Wednesday, May 6, 2020 at 9:54:45 AM UTC-4, Mohammed Billoo wrote: > > > Sorry, yes I meant in simulation. I imagine there are many good resou= rces online that show how to set up a testbench for this purpose in Vivado. > >=20 > > I assume Vivado is a simulation tool? That is agnostic to the issue. = You simply need to learn how to use the HDL you are using. Once you know t= hat you can write the test bench to operate the other side of the interface= from the FPGA. =20 > >=20 > > What sort of interfaces do you have? >=20 > It looks like there is non-synthesizable VHDL that will allow me to read = in a file, convert from unsigned to a std logic vector and pass it to my mo= dule as a DUT.=20 Not sure what you mean by "there is", but yes, your test bench does not nee= d to be synthesized since it is not going to be part of the design compiled= for your FPGA. It will be up to you to write it and make it work like the= environment your FPGA will work in. =20 There were times I even simulated analog hardware like an RC filter to proc= ess the output of a single bit DAC and produce an "analog" output. The sim= ulator allows plotting the value of an integer as a waveform reproducing my= output signal like an oscilloscope. The test bench could sample that anal= og signal, create a sound file which could then be played back outside the = simulation.=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209Article: 161703
zack_sheffield@selinc.com writes: > For those of you who do DSP modeling in Python, I've recently released > a package that supports fixed point arithmetic. The existing open > source tools are lackluster and MATLAB doesn't nicely fit into our > simulation/testing workflow. Just trying to get the word out for a > higher adoption rate! Interesting. When I went looking some months ago I found spfpm (https://pypi.python.org/pypi/spfpm) which was fairly recently updated. So how does yours compare? At least compatibility seems tighter for yours as spfpm works with Python 3.3 and later. My need was mostly for conversion of floats to VHDL sfixed/ufixed formats for FPGA testing but in the end I didn't need it.Article: 161704
On Wednesday, May 6, 2020 at 11:57:04 PM UTC-7, Anssi Saari wrote: > Zack Sheffield writes: >=20 > > For those of you who do DSP modeling in Python, I've recently released > > a package that supports fixed point arithmetic. The existing open > > source tools are lackluster and MATLAB doesn't nicely fit into our > > simulation/testing workflow. Just trying to get the word out for a > > higher adoption rate! >=20 > Interesting. When I went looking some months ago I found spfpm > (https://pypi.python.org/pypi/spfpm) which was fairly recently > updated. So how does yours compare? At least compatibility seems tighter > for yours as spfpm works with Python 3.3 and later. >=20 > My need was mostly for conversion of floats to VHDL sfixed/ufixed > formats for FPGA testing but in the end I didn't need it. * spfpm has support for various transcendental functions (log, sqrt, sin, c= os, tan) whereas fixedpoint does not. As an RTL engineer frustrated with th= e lack of python tools to more closely model VHDL constructs, I opted to no= t include these, as ieee libraries do not support these operations for fixe= d point (ufixed, sfixed, signed, unsigned) types. * fixedpoint offers several methods/functions for resizing bits of an exist= ing object. It appears that to accomplish this with spfpm, a new object mus= t be created (which is expensive).=20 * fixedpoint is (at least currently) limited to python 3.8 whereas spfpm (a= s you mentioned) is compatible back to 3.3. Version 3.8 simplified the code= base greatly, so I opted to stick with it. * Unit tests for spfpm cover very few corner cases. Unit tests for fixedpoi= nt in most cases iterate over at least 1024 random values. Bit accuracy for= fixedpoint is validated against MATLAB's fixed point designer. * fixedpoint offers several different rounding schemes (convergent, nearest= , toward inf, toward -inf, toward 0, away from 0, floor, ceil) and overflow= handling schemes (clamp/saturate, wrap).=20 * fixedpoint has configurable alerts (error, warning, ignore) for overflow,= implicit cast errors, and property mismatches (e.g., adding 2 objects with= different rounding schemes). * I can't find any documentation on spfpm other than the docstring in the s= ource file. fixedpoint documents most (if not all) aspects at https://fixed= point.readthedocs.io.=20 * fixedpoint has rich string formatting support (using f-strings, format fu= nction, or the str.format method) * fixedpoint is typed (if you like that sort of thing). * Overall, fixedpoint more closely resembles VHDL constructs than spfpm. Hope this helps!Article: 161705
zack_sheffield@selinc.com writes: > * fixedpoint is (at least currently) limited to python 3.8 whereas > spfpm (as you mentioned) is compatible back to 3.3. Version 3.8 > simplified the code base greatly, so I opted to stick with it. Thanks for the answers! I also like your clear three clause BSD license, spfpm has a messy PSF license which basically consists of a bunch of license texts that were bundled with Python itself. Out of curiousity and as something of a Python enthusiast, what features in Python 3.8 were so useful for fixedpoint?Article: 161706
On Friday, May 8, 2020 at 2:10:23 AM UTC-7, Anssi Saari wrote: > Out of curiousity and as something of a Python enthusiast, what features > in Python 3.8 were so useful for fixedpoint? Three main things: * walrus operator (https://docs.python.org/3/whatsnew/3.8.html#assignment-e= xpressions) allowed combining of lines of code all over the place. * Positional-only parameters (https://docs.python.org/3/whatsnew/3.8.html#p= ositional-only-parameters) and keyword arguments allowed for built-in error= checking of keyword arguments. * logging calls got a stacklevel keyword argument (https://docs.python.org/= 3/library/logging.html#logging.Logger.debug), which basically allows me to = wrap logging calls in a single method but always point to the line (outside= of that method) where I wanted the log to originate from. These 3 things greatly enhanced readability and reduced SLOC.Article: 161707
Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81xx) in a PGA package. I've found the M2064 data sheet, but I can't seem to track down the M2018 data sheet from MMI/AMD. I'm also looking for the MMI XACT tools of the same era that would support generating the data pattern (what we might call a configuration bitstream these days) from RTL. Any and all pointers are appreciated! --- Zach (replace the ask me with pobox, and the please with zmetzing)Article: 161708
On Friday, May 15, 2020 at 12:50:45 PM UTC-4, Zach Metzinger wrote: > Hello, >=20 > I'm a collector and tinkerer of old, archaic devices, and I recently=20 > came across a MMI M2018-20CP (date code 81xx) in a PGA package. >=20 > I've found the M2064 data sheet, but I can't seem to track down the=20 > M2018 data sheet from MMI/AMD. I'm also looking for the MMI XACT tools=20 > of the same era that would support generating the data pattern (what we= =20 > might call a configuration bitstream these days) from RTL. >=20 > Any and all pointers are appreciated! You can fix your sig so newsreaders automatically remove it in replies. =20 As to your problem, not so sure. I know who AMD is, but is MMI one of the = CPLD makers? Did Xilinx buy MMI? XACT is a Xilinx trademark for their ver= y ancient development software. I used to have copies, but gave them away = to someone who said he would give it a good home. I don't think the dongle= ever turned up, but they are easy to make (it was a down counter with a ca= rry out after some number of pulses) and there are software cracks. If I f= ind who that guy is I'll let him know someone in c.a.f is looking for him.= =20 So is this what you are looking for, Xilinx software?=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209Article: 161709
On 05/15/20 13:23, Rick C wrote: > You can fix your sig so newsreaders automatically remove it in replies. Not sure what you're referring to. I do that to avoid automatic scraping of my email address. > XACT is a Xilinx trademark for their very ancient development software. I used to have copies, but gave them away to someone who said he would give it a good home. I don't think the dongle ever turned up, but they are easy to make (it was a down counter with a carry out after some number of pulses) and there are software cracks. If I find who that guy is I'll let him know someone in c.a.f is looking for him. I need XACT that supports the M2018, which Xilinx had a cross part for (XC2018-xx). I can probably figure out the dongle situation with a debugger. Before anyone says "just use something recent": This is for a period-piece design, so modern wouldn't be appropriate. I've got hundreds of FPGAs and CPLDs, spanning many decades. I doubt Xilinx will care much that I'm asking for obsolete software. :-) I did find the data sheet from archive.org, buried in the MMI LCA Applications Handbook, so I have a pinout now. Also looks like I'm about 19 years behind someone else on the quest: https://groups.google.com/forum/#!topic/comp.arch.fpga/1lPu9RgVN00 --- ZachArticle: 161710
On 05/15/20 13:39, Zach Metzinger wrote: > I need XACT that supports the M2018, which Xilinx had a cross part for > (XC2018-xx). I can probably figure out the dongle situation with a > debugger. Nevermind! I seem to have solved this problem 4 years ago, and bit-rot got those neurons. --- ZachArticle: 161711
On Friday, May 15, 2020 at 2:39:32 PM UTC-4, Zach Metzinger wrote: > On 05/15/20 13:23, Rick C wrote: >=20 > > You can fix your sig so newsreaders automatically remove it in replies. >=20 > Not sure what you're referring to. I do that to avoid automatic scraping= =20 > of my email address. Not talking about that. BTW, I can't see what you've entered as the fake e= mail address through google groups, so no idea what I'm altering. =20 I'm talking about the dashes. If you start your sig with a line of two das= hes and a space and nothing else, it is a flag to newsreaders of the start = of a sig and it is automatically trimmed in a reply. Many people don't bot= her with that, but the polite ones do.=20 Mine is that way.=20 > > XACT is a Xilinx trademark for their very ancient development software= . I used to have copies, but gave them away to someone who said he would g= ive it a good home. I don't think the dongle ever turned up, but they are = easy to make (it was a down counter with a carry out after some number of p= ulses) and there are software cracks. If I find who that guy is I'll let h= im know someone in c.a.f is looking for him. >=20 > I need XACT that supports the M2018, which Xilinx had a cross part for=20 > (XC2018-xx). I can probably figure out the dongle situation with a debugg= er. >=20 > Before anyone says "just use something recent": This is for a=20 > period-piece design, so modern wouldn't be appropriate. I've got=20 > hundreds of FPGAs and CPLDs, spanning many decades. >=20 > I doubt Xilinx will care much that I'm asking for obsolete software. :-) Not certain they still offer it, but at one time they still had a download = of the "classic" software buried in a corner of the web site. You might fi= nd it if you nose around or maybe a google search XACT site:xilinx.com ??? > I did find the data sheet from archive.org, buried in the MMI LCA=20 > Applications Handbook, so I have a pinout now. >=20 > Also looks like I'm about 19 years behind someone else on the quest: >=20 > https://groups.google.com/forum/#!topic/comp.arch.fpga/1lPu9RgVN00 Wow! That's from 2001! The guy I gave my tools to was likely posting here= , but it would have been in the last 10 years. I did a quick search and di= dn't find the email so I'm doing a full search of all my email for the last= 20 years. It will take a bit even on a modern computer.=20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209Article: 161712
On Friday, May 15, 2020 at 2:57:01 PM UTC-4, Zach Metzinger wrote: > On 05/15/20 13:39, Zach Metzinger wrote: > > > I need XACT that supports the M2018, which Xilinx had a cross part for > > (XC2018-xx). I can probably figure out the dongle situation with a > > debugger. > > Nevermind! I seem to have solved this problem 4 years ago, and bit-rot > got those neurons. > > --- Zach Oh, how did you solve it? -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209Article: 161713
On 05/15/20 14:06, Rick C wrote: > Oh, how did you solve it? A friend of mine had this laying around (XACT 5.1), and I still have it sitting in a box from him. Hurrah! --- ZachArticle: 161714
On Friday, May 15, 2020 at 4:15:41 PM UTC-4, Zach Metzinger wrote: > On 05/15/20 14:06, Rick C wrote: > > Oh, how did you solve it? > > A friend of mine had this laying around (XACT 5.1), and I still have it > sitting in a box from him. Do you have the parallel port dongle? People have explained in very high level terms how to crack the software so you don't need the dongle. Since PCs don't have parallel ports anymore, that might be the best way to go anyhow. Good luck, -- Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209Article: 161715
Zach Metzinger <please@ask.me> wrote: > On 05/15/20 14:06, Rick C wrote: > > Oh, how did you solve it? > > A friend of mine had this laying around (XACT 5.1), and I still have it > sitting in a box from him. Hmm, perhaps it would be a good idea to have an archive of old FPGA tools. It could be worth submitting it to the Internet Archive (archive.org) - they let you upload old software and documents. I assume they have some kind of copyright waiver to allow them to do this. They don't have a whole lot of FPGA tools at present, but they have some nice Xilinx 5.25" floppies... https://archive.org/details/XilinxBorgDisks TheoArticle: 161716
On Friday, May 15, 2020 at 5:51:43 PM UTC-4, Theo wrote: > Zach Metzinger <please@ask.me> wrote: > > On 05/15/20 14:06, Rick C wrote: > > > Oh, how did you solve it? > >=20 > > A friend of mine had this laying around (XACT 5.1), and I still have it= =20 > > sitting in a box from him. >=20 > Hmm, perhaps it would be a good idea to have an archive of old FPGA tools= . >=20 > It could be worth submitting it to the Internet Archive (archive.org) - t= hey > let you upload old software and documents. I assume they have some kind = of > copyright waiver to allow them to do this. >=20 > They don't have a whole lot of FPGA tools at present, but they have some > nice Xilinx 5.25" floppies... > https://archive.org/details/XilinxBorgDisks >=20 > Theo Wow! I've got a very popular schematic editor (and expensive) from that ti= me frame (early 90's) sitting in my basement on 3.5" floppies, 10 or 20 of = them. I can't recall the name. I think it had "view" in the name, but not= Labview, that was something very different. We used it for the FPGA desig= ns before HDL. I still have this. Forgot all about it. =20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209
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