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Messages from 159150

Article: 159150
Subject: Re: Four_Bit_Counter in VHDL
From: Marvin L <user123random@gmail.com>
Date: Thu, 25 Aug 2016 23:18:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
rickman: Someone told me to use http://i.imgur.com/C5KOrve.png but it says try to AVOID this. Any advice ?

Article: 159151
Subject: Re: Four_Bit_Counter in VHDL
From: rickman <gnuarm@gmail.com>
Date: Fri, 26 Aug 2016 02:56:01 -0400
Links: << >>  << T >>  << A >>
On 8/26/2016 2:18 AM, Marvin L wrote:
> rickman: Someone told me to use http://i.imgur.com/C5KOrve.png but it says try to AVOID this. Any advice ?

Async loads generally show you are solving the problem wrong.  Why can't 
you use a synchronous load?

-- 

Rick C

Article: 159152
Subject: Re: Four_Bit_Counter in VHDL
From: Marvin L <user123random@gmail.com>
Date: Thu, 25 Aug 2016 23:59:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
rickman: this is the requirement given to me.

When a LOAD push-button is pressed, the counter is loaded asynchronously with a 4 bit VALUE set on a 4-bit DIP switch.



--> and then someone suggested to me that I do synchronization to handle it synchronously... I am not sure now 

Article: 159153
Subject: Re: Four_Bit_Counter in VHDL
From: Marvin L <user123random@gmail.com>
Date: Fri, 26 Aug 2016 00:54:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
I already done synchronization as stated in https://www.doulos.com/knowhow/fpga/synchronisation/

My code is at http://pastebin.com/qwMHucpN but I am getting value of x for Port_counter.

Please see http://i.imgur.com/Ir0nASQ.png

Is it because of the separate process for LOAD that I am using ?

Article: 159154
Subject: Re: Four_Bit_Counter in VHDL
From: rickman <gnuarm@gmail.com>
Date: Fri, 26 Aug 2016 04:17:55 -0400
Links: << >>  << T >>  << A >>
On 8/26/2016 3:54 AM, Marvin L wrote:
> I already done synchronization as stated in https://www.doulos.com/knowhow/fpga/synchronisation/
>
> My code is at http://pastebin.com/qwMHucpN but I am getting value of x for Port_counter.
>
> Please see http://i.imgur.com/Ir0nASQ.png
>
> Is it because of the separate process for LOAD that I am using ?

If the requirement is to use an async load, then that is the requirement.

Again, you are assigning a signal in two processes.  The async and sync 
logic need to be in the same process.  BTW, they way you coded this, 
your reset is synchronous, not async.  Just a practical note, in FPGAs a 
fixed value can be loaded asynchronously (that makes it the same as a 
pre/reset).  But a signal can not be assigned to a FF asynchronously. 
It is *very* seldom this would ever be a requirement.  This is just an 
exercise...


process(clk, load) begin
   -- everything before the if(rising_edge(... is async
     if (load = '1') then
         temp <= Value;
     elsif (rising_edge(clk) and clk_enable = '1') then
         if(reset = '1') then
          --Do reset
             temp <= "0000";
         else
             if (AUTO_MANUAL = '1') then
             --Auto-counting
                 if UP_DOWN = '1' then
                     if temp < "1111" then
                         temp <= temp + 1;
                     else
                         temp <= "1111";
                     end if;
                 else
                     if temp > "0000" then
                         temp <= temp - 1;
                     else
                         temp <= "0000";
                     end if;
                 end if;
             else
                 --Manual Counting

             end if;
         end if;
     end if;
end process;


-- 

Rick C

Article: 159155
Subject: Re: Four_Bit_Counter in VHDL
From: Mike Perkins <spam@spam.com>
Date: Fri, 26 Aug 2016 11:12:22 +0100
Links: << >>  << T >>  << A >>
On 26/08/2016 08:54, Marvin L wrote:
> I already done synchronization as stated in https://www.doulos.com/knowhow/fpga/synchronisation/

What are you synchronising? I presume this is the load input? If so then 
your load signal is no long an asynchronous signal and can implement a 
more reliable synchronous load.

> My code is at http://pastebin.com/qwMHucpN but I am getting value of x for Port_counter.
>
> Please see http://i.imgur.com/Ir0nASQ.png
>
> Is it because of the separate process for LOAD that I am using ?

A signal should only be defined in a single process. If you assume that 
you won't go wrong in that respect. As an example your 'temp' is 
assigned a value in two independent processes. It's like a contention in 
hardware.


-- 
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

Article: 159156
Subject: Re: Low End FPGAs
From: Jon Elson <jmelson@wustl.edu>
Date: Fri, 26 Aug 2016 14:03:52 -0500
Links: << >>  << T >>  << A >>
Rob Gaddi wrote:

> So I'm looking at various platforms for general purpose, fairly low-end
> FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera
> Cyclone V E all have options in the sort of
> 
>   * 170ish IO
>   * Enough logic to do PLDy sort of tasks
>   * $20ish in ~100p quantity.
> 
> I've used Vivado, and Vivado's got its issues.  I've used the latest
> Quartus Prime, and Quartus Prime's got its issues.  Haven't used Diamond
> yet, but I'm guessing Diamond's got its issues.
> 
> Has anyone been playing with any (or even better multiple) of these and
> got any opinions one way or another on which to go with? Or do I just
> roll a die?
> 
The smallest Xilinx Spartan 3E is quite affordable, if you need just a 
little logic.  There's also the CoolRunner II and XC9536XL for really small 
jobs, these are only $1 - $2 each.

Jon

Article: 159157
Subject: Re: Low End FPGAs
From: Rob Gaddi <rgaddi@highlandtechnology.invalid>
Date: Fri, 26 Aug 2016 19:11:32 -0000 (UTC)
Links: << >>  << T >>  << A >>
Jon Elson wrote:

> Rob Gaddi wrote:
>
>> So I'm looking at various platforms for general purpose, fairly low-end
>> FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera
>> Cyclone V E all have options in the sort of
>> 
>>   * 170ish IO
>>   * Enough logic to do PLDy sort of tasks
>>   * $20ish in ~100p quantity.
>> 
>> I've used Vivado, and Vivado's got its issues.  I've used the latest
>> Quartus Prime, and Quartus Prime's got its issues.  Haven't used Diamond
>> yet, but I'm guessing Diamond's got its issues.
>> 
>> Has anyone been playing with any (or even better multiple) of these and
>> got any opinions one way or another on which to go with? Or do I just
>> roll a die?
>> 
> The smallest Xilinx Spartan 3E is quite affordable, if you need just a 
> little logic.  There's also the CoolRunner II and XC9536XL for really small 
> jobs, these are only $1 - $2 each.
>
> Jon

My concern is longevity for new designs.  Xilinx's decision to not bring
any of the Spartan family forward to Vivado sounds a whole lot like
"Well, we're not NOT supporting them, but..."

Altera's decision to drop Quartus support for Cyclone III, even though
they still support the Cyclone IV which is nothing but a die shrink, is
equally irksome.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 159158
Subject: Re: Low End FPGAs
From: Emilian Miron <emilian.miron@gmail.com>
Date: Fri, 26 Aug 2016 13:28:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
I've been very happy playing with Max 10. There's a dev board for 30$ which is really cheap but has 8K logic elements, sdram, etc.
https://www.arrow.com/en/products/bemicromax10/arrow-development-tools

For a medium design (Z80 CPU and peripherals) my compilation times were ~10-15 minutes if I remember correctly with the free edition of Quartus.

I also found the free included SignalTap logic analyzer very useful in debugging the design-- I've heard that Xilinx charges for the logic analyzer part which swayed me in Altera's direction.

The chip itself is also pretty cheap in small quantities (~~10$)
http://www.mouser.com/ProductDetail/Altera/10M08SCU169C8G/?qs=sGAEpiMZZMvzv9EAOJZmO9CMfHSxRLPsX%252b1%252bhuEUWwU%3d

What applications are you looking to implement and what other factors are important to you?

On Friday, August 26, 2016 at 3:11:35 PM UTC-4, Rob Gaddi wrote:
> Jon Elson wrote:
> 
> > Rob Gaddi wrote:
> >
> >> So I'm looking at various platforms for general purpose, fairly low-end
> >> FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera
> >> Cyclone V E all have options in the sort of
> >> 
> >>   * 170ish IO
> >>   * Enough logic to do PLDy sort of tasks
> >>   * $20ish in ~100p quantity.
> >> 
> >> I've used Vivado, and Vivado's got its issues.  I've used the latest
> >> Quartus Prime, and Quartus Prime's got its issues.  Haven't used Diamond
> >> yet, but I'm guessing Diamond's got its issues.
> >> 
> >> Has anyone been playing with any (or even better multiple) of these and
> >> got any opinions one way or another on which to go with? Or do I just
> >> roll a die?
> >> 
> > The smallest Xilinx Spartan 3E is quite affordable, if you need just a 
> > little logic.  There's also the CoolRunner II and XC9536XL for really small 
> > jobs, these are only $1 - $2 each.
> >
> > Jon
> 
> My concern is longevity for new designs.  Xilinx's decision to not bring
> any of the Spartan family forward to Vivado sounds a whole lot like
> "Well, we're not NOT supporting them, but..."
> 
> Altera's decision to drop Quartus support for Cyclone III, even though
> they still support the Cyclone IV which is nothing but a die shrink, is
> equally irksome.
> 
> -- 
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
> 
> Email address domain is currently out of order.  See above to fix.


Article: 159159
Subject: Help me choose an FPGA to design network protocols
From: PM X <pinaki2@gmail.com>
Date: Fri, 26 Aug 2016 15:47:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,
I have over a decade of experience in hardware design, but almost all of it=
 is in ASIC. I had done some FPGA projects in school, but nothing after tha=
t. So after all these years, I want to work on some personal FPGA projects =
(mainly to prepare myself for future job interviews). I have the following =
two questions.

1. What is an FPGA board that I can buy for this purpose? I am probably loo=
king to do something not too basic (since I already have a lot of experienc=
e in design), at the same time I do not want to make it a super complicated=
 full time project either. I prefer Xilinx (but I am open) and something le=
ss than $250 will be good. Note that question #2 might also affect the choi=
ce of board.

2. Once I have the FPGA board, I would like to implement some design involv=
ing network protocol (like TCP/IP, UDP, etc.). However, I have not worked o=
n these network layers before and don't have an extensive knowledge on them=
 either (other than what I had read in school long ago), so I do not have a=
 very clear picture of what to do. Is there any open source design availabl=
e on this? Or any projects with specific definitions that I can understand =
and then start implementing?

Thanks!

Article: 159160
Subject: Re: Low End FPGAs
From: Jon Elson <elson@pico-systems.com>
Date: Fri, 26 Aug 2016 21:02:06 -0500
Links: << >>  << T >>  << A >>
Rob Gaddi wrote:


> My concern is longevity for new designs.  Xilinx's decision to not bring
> any of the Spartan family forward to Vivado sounds a whole lot like
> "Well, we're not NOT supporting them, but..."
> 
Fortunately, Xilinx does archive their older tools.  I just had to bring 
back an ise ver 10.1 system to make a change to a legacy design on Spartan 
2E.  I'm running ise 14.7 for my current products using 95**XL and Spartan 
3A, and happy with them, no desire to update and learn any new software.
> Altera's decision to drop Quartus support for Cyclone III, even though
> they still support the Cyclone IV which is nothing but a die shrink, is
> equally irksome.
> 
Glad to know Xilinx isn't the only outfit doing this.

Jon

Article: 159161
Subject: Re: Low End FPGAs
From: Jon Elson <elson@pico-systems.com>
Date: Fri, 26 Aug 2016 21:04:54 -0500
Links: << >>  << T >>  << A >>
Emilian Miron wrote:

> I've heard that Xilinx charges for the logic
> analyzer part which swayed me in Altera's direction.
> 
No, I don't think that is true.  I'm pretty sure ChipScope is included even 
in the WebPack, although it probably has size limits or something.  At least 
for the versions I'm using.

Jon

Article: 159162
Subject: Re: Looking for Xilinx HW-130/HW-120 Adapters
From: Tim Regeant <TimRegeant@gmail.com>
Date: Sat, 27 Aug 2016 01:00:20 -0400
Links: << >>  << T >>  << A >>
BTW, will pay cash for any of these adapters.  Thanks for looking.


On 8/25/2016 9:38 AM, Tim Regeant wrote:
> My project needs to program a Xilinx XC7336 44PLCC.
>
> I have the software now and the HW-130 programming unit.
>
> Also have the HW-137-PC44/VQ44 adapter which I assumed would work with
> the XC7336, but as it turns out it does not.
>
> So I need to find the adapter(s) below.  If anyone can help out please
> let me know.
>
> HW-133-PC44
> HW-133-PC68
> HW-133-PC84
>
> For reference here is webpage showing the HW-133-PC68 adapter (middle
> image):  http://www.digital-circuitry.com/MyLAB_IC_PROG_HW-130.htm
>
> Also at this Xilinx support page
> http://www.xilinx.com/support/answers/961.html it mentions the HW-120
> adapters are mostly compatible with the HW-130 programmer.
>
> So I could alternatively use these adapters if anyone has them:
>
> HW-126-PC44
> HW-126-PC68
> HW-126-PC84
>
> Thanks for any help you may offer!
>
>


Article: 159163
Subject: Re: Looking for Xilinx HW-130/HW-120 Adapters
From: Tim Regeant <TimRegeant@gmail.com>
Date: Sat, 27 Aug 2016 01:15:07 -0400
Links: << >>  << T >>  << A >>
This webpage has pictures of some of the adapters.  Maybe it will ring a 
bell :)

http://www.digital-circuitry.com/MyLAB_IC_PROG_HW-130.htm


On 8/27/2016 1:00 AM, Tim Regeant wrote:
> BTW, will pay cash for any of these adapters.  Thanks for looking.
>
>
> On 8/25/2016 9:38 AM, Tim Regeant wrote:
>> My project needs to program a Xilinx XC7336 44PLCC.
>>
>> I have the software now and the HW-130 programming unit.
>>
>> Also have the HW-137-PC44/VQ44 adapter which I assumed would work with
>> the XC7336, but as it turns out it does not.
>>
>> So I need to find the adapter(s) below.  If anyone can help out please
>> let me know.
>>
>> HW-133-PC44
>> HW-133-PC68
>> HW-133-PC84
>>
>> For reference here is webpage showing the HW-133-PC68 adapter (middle
>> image):  http://www.digital-circuitry.com/MyLAB_IC_PROG_HW-130.htm
>>
>> Also at this Xilinx support page
>> http://www.xilinx.com/support/answers/961.html it mentions the HW-120
>> adapters are mostly compatible with the HW-130 programmer.
>>
>> So I could alternatively use these adapters if anyone has them:
>>
>> HW-126-PC44
>> HW-126-PC68
>> HW-126-PC84
>>
>> Thanks for any help you may offer!
>>
>>
>


Article: 159164
Subject: Re: Help me choose an FPGA to design network protocols
From: rickman <gnuarm@gmail.com>
Date: Sat, 27 Aug 2016 01:28:41 -0400
Links: << >>  << T >>  << A >>
On 8/26/2016 6:47 PM, PM X wrote:
> Hi all, I have over a decade of experience in hardware design, but
> almost all of it is in ASIC. I had done some FPGA projects in school,
> but nothing after that. So after all these years, I want to work on
> some personal FPGA projects (mainly to prepare myself for future job
> interviews). I have the following two questions.
>
> 1. What is an FPGA board that I can buy for this purpose? I am
> probably looking to do something not too basic (since I already have
> a lot of experience in design), at the same time I do not want to
> make it a super complicated full time project either. I prefer Xilinx
> (but I am open) and something less than $250 will be good. Note that
> question #2 might also affect the choice of board.

There are lots of boards available under $100 but likely won't have 
networking support.  Here is one with Ethernet for $200.

https://www.arrow.com/en/products/sf2plus-dev-kit/arrow-development-tools#page-8

It uses a Microsemi Smartfusion2 part which contains an ARM CM4 I believe.


> 2. Once I have the FPGA board, I would like to implement some design
> involving network protocol (like TCP/IP, UDP, etc.). However, I have
> not worked on these network layers before and don't have an extensive
> knowledge on them either (other than what I had read in school long
> ago), so I do not have a very clear picture of what to do. Is there
> any open source design available on this? Or any projects with
> specific definitions that I can understand and then start
> implementing?

This is often done with a CPU rather than hardware.  TCP/IP protocols 
are very complicated.

As for Open Source, what's wrong with Linux?  Or do I misunderstand?

-- 

Rick C

Article: 159165
Subject: Re: Help me choose an FPGA to design network protocols
From: PM X <pinaki2@gmail.com>
Date: Sat, 27 Aug 2016 10:20:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Friday, August 26, 2016 at 10:28:45 PM UTC-7, rickman wrote:
> On 8/26/2016 6:47 PM, PM X wrote:
> > Hi all, I have over a decade of experience in hardware design, but
> > almost all of it is in ASIC. I had done some FPGA projects in school,
> > but nothing after that. So after all these years, I want to work on
> > some personal FPGA projects (mainly to prepare myself for future job
> > interviews). I have the following two questions.
> >
> > 1. What is an FPGA board that I can buy for this purpose? I am
> > probably looking to do something not too basic (since I already have
> > a lot of experience in design), at the same time I do not want to
> > make it a super complicated full time project either. I prefer Xilinx
> > (but I am open) and something less than $250 will be good. Note that
> > question #2 might also affect the choice of board.
>=20
> There are lots of boards available under $100 but likely won't have=20
> networking support.  Here is one with Ethernet for $200.
>=20
> https://www.arrow.com/en/products/sf2plus-dev-kit/arrow-development-tools=
#page-8
>=20
> It uses a Microsemi Smartfusion2 part which contains an ARM CM4 I believe=
.
>=20

Sorry, I have some more newbie type questions. How does a board like the ab=
ove supposed to work considering the ARM core in there? My understanding is=
 that whatever design I implement in HDL runs in the actual FPGA, and any a=
dditional software program that I also want to run goes to the ARM processo=
r? So we have two separate runs going on - one in the FPGA and the other in=
 the ARM - and these two can communicate with each other?

One other thing I am confused about is that, are the development boards alw=
ays made by third parties using the FPGA from companies like Xilinx? Or doe=
s Xilinx ever make their own development board?

I am thinking about getting a board with Xilinx FPGA, probably one of the o=
lder Virtex ones. Found this on ebay: http://www.ebay.com/itm/XILINX-VIRTEX=
-4-XC4VFX100-FPGA-kit-Development-board-XKF4/181791876772 , any comments?

>=20
> > 2. Once I have the FPGA board, I would like to implement some design
> > involving network protocol (like TCP/IP, UDP, etc.). However, I have
> > not worked on these network layers before and don't have an extensive
> > knowledge on them either (other than what I had read in school long
> > ago), so I do not have a very clear picture of what to do. Is there
> > any open source design available on this? Or any projects with
> > specific definitions that I can understand and then start
> > implementing?
>=20
> This is often done with a CPU rather than hardware.  TCP/IP protocols=20
> are very complicated.
>=20
> As for Open Source, what's wrong with Linux?  Or do I misunderstand?

I meant some part of the TCP/IP stack implemented in actual hardware and ru=
nning in the FPGA. For example, a TCP Offload Engine, which implements the =
whole TCP/IP stack in hardware. Now, I understand that is something enormou=
s and do not want to work on something that big for just a side/hobby proje=
ct. But something in that area with less complexity is what I am looking fo=
r. I just don't have a good idea of what that could be, so having some clea=
r definition will help.

Article: 159166
Subject: Re: Low End FPGAs
From: thomas.entner99@gmail.com
Date: Sat, 27 Aug 2016 13:43:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
Am Samstag, 27. August 2016 04:05:02 UTC+2 schrieb Jon Elson:
> Emilian Miron wrote:
> 
> > I've heard that Xilinx charges for the logic
> > analyzer part which swayed me in Altera's direction.
> > 
> No, I don't think that is true.  I'm pretty sure ChipScope is included even 
> in the WebPack, although it probably has size limits or something.  At least 
> for the versions I'm using.
> 
> Jon

This has changed recently, luckily... Unfortunately, the user experience of ChipScope is in no way comparable with SignalTap, at least IMHO.

Thomas

www.entner-electronics.com - Home of EEBlaster

Article: 159167
Subject: Re: Low End FPGAs
From: thomas.entner99@gmail.com
Date: Sat, 27 Aug 2016 13:54:13 -0700 (PDT)
Links: << >>  << T >>  << A >>

> > My concern is longevity for new designs.  Xilinx's decision to not brin=
g
> > any of the Spartan family forward to Vivado sounds a whole lot like
> > "Well, we're not NOT supporting them, but..."
> >=20
> Fortunately, Xilinx does archive their older tools.  I just had to bring=
=20
> back an ise ver 10.1 system to make a change to a legacy design on Sparta=
n=20
> 2E.  I'm running ise 14.7 for my current products using 95**XL and Sparta=
n=20
> 3A, and happy with them, no desire to update and learn any new software.

Also Altera allows you to download their old software. In both cases this m=
ay help you out in short term, but in long term you may have issues install=
ing this versions on a modern system. (e.g. if you want to maintain a FLEX1=
0K design - not sure if MAX+PLUS II installs on Win 10 64b...) (of course i=
t is more Microsoft to blame here...)

> > Altera's decision to drop Quartus support for Cyclone III, even though
> > they still support the Cyclone IV which is nothing but a die shrink, is
> > equally irksome.
> >=20
> Glad to know Xilinx isn't the only outfit doing this.
>=20
> Jon

From my outside view the difference is, that Vivado does not support old de=
vices as it is "too much of a challange" for Xilinx, while Quartus stops su=
pporting older devices because of political decisions form Altera (which ar=
e not clear to me? Urging people into new devices? In reality it is more fo=
rcing customers to stay at older versions... For some parts it may make sen=
se from a maintenance point of view, but as someone already mentioned e.g. =
Cyclone III and IV are internally the same).

Both is equally frustrating....

Thomas

www.entner-electronics.com - Home of EEBlaster

Article: 159168
Subject: Re: Low End FPGAs
From: thomas.entner99@gmail.com
Date: Sat, 27 Aug 2016 14:04:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
Altera: I would also consider the MAX10 family
Xilinx: The have announced Spartan-7 some time ago, but beside this (remarkingly low content) announcement, I do not know about the status of this. So it seems you have to look at Artix-7 as you already do
Lattice: MachXO2/3 should be you part

My very personal opinion on software rating:
1. Quartus (esp. small designs benefit from the "more responsive" feeling of the GUI - I am talking about 15.0 here, have not used Prime yet)
2. Vivado (Although I like the integrated simulator a lot)
3. Diamond (however, have not used it since a while)

But for sure you can get your work done with all of them, so this discussion is highly subjective.

Thomas

www.entner-electronics.com - Home of EEBlaster


Article: 159169
Subject: Re: Help me choose an FPGA to design network protocols
From: rickman <gnuarm@gmail.com>
Date: Sun, 28 Aug 2016 02:09:22 -0400
Links: << >>  << T >>  << A >>
On 8/27/2016 1:20 PM, PM X wrote:
> On Friday, August 26, 2016 at 10:28:45 PM UTC-7, rickman wrote:
>> On 8/26/2016 6:47 PM, PM X wrote:
>>> Hi all, I have over a decade of experience in hardware design,
>>> but almost all of it is in ASIC. I had done some FPGA projects in
>>> school, but nothing after that. So after all these years, I want
>>> to work on some personal FPGA projects (mainly to prepare myself
>>> for future job interviews). I have the following two questions.
>>>
>>> 1. What is an FPGA board that I can buy for this purpose? I am
>>> probably looking to do something not too basic (since I already
>>> have a lot of experience in design), at the same time I do not
>>> want to make it a super complicated full time project either. I
>>> prefer Xilinx (but I am open) and something less than $250 will
>>> be good. Note that question #2 might also affect the choice of
>>> board.
>>
>> There are lots of boards available under $100 but likely won't have
>>  networking support.  Here is one with Ethernet for $200.
>>
>> https://www.arrow.com/en/products/sf2plus-dev-kit/arrow-development-tools#page-8
>>
>>
>> It uses a Microsemi Smartfusion2 part which contains an ARM CM4 I believe.
>>
>
> Sorry, I have some more newbie type questions. How does a board like
> the above supposed to work considering the ARM core in there? My
> understanding is that whatever design I implement in HDL runs in the
> actual FPGA, and any additional software program that I also want to
> run goes to the ARM processor? So we have two separate runs going on
> - one in the FPGA and the other in the ARM - and these two can
> communicate with each other?

Hmmm....  Yes, the ARM will run software written in your favorite 
sequential language (C, Python, etc) while the FPGA doesn't exactly 
"run" anything.  HDL stands for Hardware Description Language.  The HDL 
doesn't so much get compiled to something that "runs" like a computer 
program, but rather it is compiled to a configuration file that controls 
how the various elements of the FPGA hardware are interconnected.  The 
hardware needed in the FPGA is "described".

Exactly how the two communicate depends on the vendor.  Xilinx and 
Altera have similar offerings which their own interfaces between the CPU 
and the FPGA fabric.  But basically the CPU program will perform port 
I/Os or perhaps DMA is used to move data between the FPGA and memory.  I 
haven't done a project with this chip as yet.


> One other thing I am confused about is that, are the development
> boards always made by third parties using the FPGA from companies
> like Xilinx? Or does Xilinx ever make their own development board?

The only boards I've seen made by the FPGA vendors tend to be a bit 
pricier than the ones made by third parties.  That's not to say third 
parties don't make pricey boards, they span a wider range I guess.  FPGA 
vendors make boards so they can sell their chips.  Board vendors are 
selling boards and so make them as fully functional as they can for the 
price.


> I am thinking about getting a board with Xilinx FPGA, probably one of
> the older Virtex ones. Found this on ebay:
> http://www.ebay.com/itm/XILINX-VIRTEX-4-XC4VFX100-FPGA-kit-Development-board-XKF4/181791876772
> , any comments?

Why an older FPGA?  Is it price?

As you may have figured out, I'm not a big fan of Xilinx.  I keep 
hearing about all manner of issues with their in house tool, Vivaldo. 
It used to be XST, but the scrapped that.  In fact, my very first FPGA 
design was a Xilinx and during a four month project (or maybe six, I 
don't recall exactly) I had to ditch tools twice.  The first time was to 
drop the Orcad VHDL tool as it was largely non-functional, switching to 
the Xilinx tool.  Then a second time when Xilinx dropped their earlier 
tool and only supported a new one.  Later they came out with XST and now 
Vivaldo.  I don't get that they have to keep tossing tools.  It makes it 
hard to maintain lifetime support for your product.

On the other hand Lattice ditched the chip I have designed on a board I 
am still making good money from, *very* good money.  Fortunately there 
is sufficient inventory that I won't have to redesign the board for a 
number of years.  At least they use third party synthesis so it isn't a 
problem to keep supporting products over their lifetime.


>>> 2. Once I have the FPGA board, I would like to implement some
>>> design involving network protocol (like TCP/IP, UDP, etc.).
>>> However, I have not worked on these network layers before and
>>> don't have an extensive knowledge on them either (other than what
>>> I had read in school long ago), so I do not have a very clear
>>> picture of what to do. Is there any open source design available
>>> on this? Or any projects with specific definitions that I can
>>> understand and then start implementing?
>>
>> This is often done with a CPU rather than hardware.  TCP/IP
>> protocols are very complicated.
>>
>> As for Open Source, what's wrong with Linux?  Or do I
>> misunderstand?
>
> I meant some part of the TCP/IP stack implemented in actual hardware
> and running in the FPGA. For example, a TCP Offload Engine, which
> implements the whole TCP/IP stack in hardware. Now, I understand that
> is something enormous and do not want to work on something that big
> for just a side/hobby project. But something in that area with less
> complexity is what I am looking for. I just don't have a good idea of
> what that could be, so having some clear definition will help.

I have *no* idea what that could be.  As I mentioned, my understanding 
is the TCP/IP protocol in particular is *very* complex and people don't 
want to implement their own software on a CPU, much less in hardware. 
I'm not sure what an "offload engine" would be other than a dedicated 
CPU, optimized for TCP/IP.  But if you have a CM4 in the device, why not 
use that?

To make a hybrid implementation with part of the TCP/IP stack in the CPU 
and part in the FPGA fabric would require you to intimately understand 
this algorithm.  I believe I've read that a lot of the details are not 
in any specification, rather are coded in the applications.  So you 
might need to reverse engineer one or more implementations.

-- 

Rick C

Article: 159170
Subject: Re: Help me choose an FPGA to design network protocols
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Sun, 28 Aug 2016 08:11:43 +0100
Links: << >>  << T >>  << A >>
On 27/08/16 18:20, PM X wrote:
> I meant some part of the TCP/IP stack implemented in actual hardware and running in the FPGA. For example, a TCP Offload Engine, which implements the whole TCP/IP stack in hardware. Now, I understand that is something enormous and do not want to work on something that big for just a side/hobby project. But something in that area with less complexity is what I am looking for. I just don't have a good idea of what that could be, so having some clear definition will help.

Protocol stack offload engines have two fundamental "issues".

Firstly the time and latency required to get the packets
to/from the main CPU. That significantly affects performance.

Secondly the point that TCP is and end-to-end protocol
and will correct protocol errors between or in the
endpoints. An offload engine becomes the endpoint, so
errors between the offload engine and the main CPU will
not be corrected.

The processing required to reliably transfer packets
to/from the main CPU bears a lot of similarity to TCP!

TCP in FPGA makes sense where
  - the lowest latency is required, and
  - where simplifying assumptions can be made, and
  - where the end terminal logic is also done in the FPGA
e.g. high frequency trading, where they put the business
trading rules in hardware to minimise latency


Article: 159171
Subject: Re: Low End FPGAs
From: already5chosen@yahoo.com
Date: Sun, 28 Aug 2016 05:58:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Friday, August 26, 2016 at 3:04:34 AM UTC+3, Rob Gaddi wrote:
> So I'm looking at various platforms for general purpose, fairly low-end
> FPGAs, and it looks like the Lattice ECP5, Xilinx Artix-7, and Altera
> Cyclone V E all have options in the sort of
> 
>   * 170ish IO
>   * Enough logic to do PLDy sort of tasks
>   * $20ish in ~100p quantity.
> 
> I've used Vivado, and Vivado's got its issues.  I've used the latest
> Quartus Prime, and Quartus Prime's got its issues.  Haven't used Diamond
> yet, but I'm guessing Diamond's got its issues.
> 
> Has anyone been playing with any (or even better multiple) of these and
> got any opinions one way or another on which to go with? Or do I just
> roll a die?
> 
> -- 
> Rob Gaddi, Highland Technology -- www.highlandtechnology.com
> 
> Email address domain is currently out of order.  See above to fix.

Unless you have very good relationships with your local Altera reps, getting what you want with Cyclone V E sounds almost impossible.
On the other hand, Cyclone IV E (e.g. EP4CE6) should be easily in your range.

Even if your logic requirement are higher than EP4CE6, EP4CE15 still can be cheaper option than 5CEA2.


Article: 159172
Subject: Re: Low End FPGAs
From: rickman <gnuarm@gmail.com>
Date: Sun, 28 Aug 2016 10:15:27 -0400
Links: << >>  << T >>  << A >>
On 8/27/2016 4:43 PM, thomas.entner99@gmail.com wrote:
> Am Samstag, 27. August 2016 04:05:02 UTC+2 schrieb Jon Elson:
>> Emilian Miron wrote:
>>
>>> I've heard that Xilinx charges for the logic analyzer part which
>>> swayed me in Altera's direction.
>>>
>> No, I don't think that is true.  I'm pretty sure ChipScope is
>> included even in the WebPack, although it probably has size limits
>> or something.  At least for the versions I'm using.
>>
>> Jon
>
> This has changed recently, luckily... Unfortunately, the user
> experience of ChipScope is in no way comparable with SignalTap, at
> least IMHO.

If they can't be compared, how would anyone know which is better?...

-- 

Rick C

Article: 159173
Subject: Re: Low End FPGAs
From: rickman <gnuarm@gmail.com>
Date: Sun, 28 Aug 2016 10:20:01 -0400
Links: << >>  << T >>  << A >>
On 8/27/2016 4:54 PM, thomas.entner99@gmail.com wrote:
>
>>> My concern is longevity for new designs.  Xilinx's decision to not bring
>>> any of the Spartan family forward to Vivado sounds a whole lot like
>>> "Well, we're not NOT supporting them, but..."
>>>
>> Fortunately, Xilinx does archive their older tools.  I just had to bring
>> back an ise ver 10.1 system to make a change to a legacy design on Spartan
>> 2E.  I'm running ise 14.7 for my current products using 95**XL and Spartan
>> 3A, and happy with them, no desire to update and learn any new software.
>
> Also Altera allows you to download their old software. In both cases this may help you out in short term, but in long term you may have issues installing this versions on a modern system. (e.g. if you want to maintain a FLEX10K design - not sure if MAX+PLUS II installs on Win 10 64b...) (of course it is more Microsoft to blame here...)
>
>>> Altera's decision to drop Quartus support for Cyclone III, even though
>>> they still support the Cyclone IV which is nothing but a die shrink, is
>>> equally irksome.
>>>
>> Glad to know Xilinx isn't the only outfit doing this.
>>
>> Jon
>
> From my outside view the difference is, that Vivado does not support old devices as it is "too much of a challange" for Xilinx, while Quartus stops supporting older devices because of political decisions form Altera (which are not clear to me? Urging people into new devices? In reality it is more forcing customers to stay at older versions... For some parts it may make sense from a maintenance point of view, but as someone already mentioned e.g. Cyclone III and IV are internally the same).
>
> Both is equally frustrating....

It is simple economics.  Verification is the expensive part of software. 
  Removing the verification effort for older devices is a big time and 
money savings with little cost in terms of sales.

I learned a long time ago that FPGA companies focus on whatever is the 
latest generation not caring one whit about sales of older generations. 
The return for efforts promoting the older generations will always be a 
lot less than for promoting the latest generation.  So the lack of full 
support at some point is inevitable.

-- 

Rick C

Article: 159174
Subject: Need help finding Synario Futurenet 6.10
From: Tim Regeant <TimRegeant@gmail.com>
Date: Sun, 28 Aug 2016 11:49:44 -0400
Links: << >>  << T >>  << A >>
Anyone know where I can find this vintage software?

I am looking for the verion 6.10 free with dongle not required.

I think Synario was the one to release the free version.

Used to be at the ftp site ftp://ftp.synario.com but can't reach it now.

Thanks for any help you can offer.



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