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On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin wrote: > I have a design that will use a DDS synthesizer to generate an internal > trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The > required upper frequency limit is maybe 20 MHz. The FPGA will have the > usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at > maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC > lowpass filter and a comparator. Standard stuff. > > But could such a clock be generated entirely inside the FPGA? > > Just using the MSB of the DDS phase accumulator works, but it will have > one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've > got to look into some sort of outboard analog filtering to clean up that > single-bit clock, but I'm not optimistic. DDS is just too weird. > > Do you suppose that one of the FPGA PLLs be used to clean up the DDS > clock, scrub the jitter somehow? That could maybe be used over a modest > range, octave maybe, followed by some dividers. > > Any other ideas for making a programmable-frequency clock with DDS sort > of resolution, but without all that outboard analog stuff? > > I've been playing with sorta DDS in LT Spice, using a quantizer to > approximate the DDS accumulator and DAC, but that's obviously not the > best tool for this. I sat in on a seminar on using FPGAs in comms circuits once, a long time ago. I made some comment that essentially boiled down to "trust the FPGA clock to not jitter", and was hooted down by the entire audience. I haven't forgotten... -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.comArticle: 159226
Maybe you get a better jitter than the MSB by using an iodelay oscillator. Never done this, but xapp872 describes it.Article: 159227
On 9/4/2016 3:13 PM, Mike Perkins wrote: > On 04/09/2016 19:11, John Larkin wrote: >> >> >> I have a design that will use a DDS synthesizer to generate an >> internal trigger rate for a pulse generator. The chip will be a ZYNQ >> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >> will have the usual, 48 bit or so, phase accumulator and sine lookup >> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >> turn drives an LC lowpass filter and a comparator. Standard stuff. >> >> But could such a clock be generated entirely inside the FPGA? >> >> Just using the MSB of the DDS phase accumulator works, but it will >> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >> MHz. I've got to look into some sort of outboard analog filtering to >> clean up that single-bit clock, but I'm not optimistic. DDS is just >> too weird. >> >> Do you suppose that one of the FPGA PLLs be used to clean up the DDS >> clock, scrub the jitter somehow? That could maybe be used over a >> modest range, octave maybe, followed by some dividers. > > That isn't how FPGA PLLs work. They add jitter rather than removing it! Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a standard analog PLL and so *would* remove jitter. >> Any other ideas for making a programmable-frequency clock with DDS >> sort of resolution, but without all that outboard analog stuff? >> >> I've been playing with sorta DDS in LT Spice, using a quantizer to >> approximate the DDS accumulator and DAC, but that's obviously not the >> best tool for this. > > The jitter of a clock derived from within a FPGA would simply be related > to the clock frequency used. > > If you use a 250MHz clock, as per the max frequency of many cheap FPGAs, > then jitter will be 4ns (+ a small bit). Yes, you are clearly thinking of a digital PLL based on the digital fabric of the FPGA. I assume John was talking about the dedicated PLLs found in most FPGAS. > What jitter spec are you looking for? What is the range of frequencies > you require? > > Would a VCO / PLL be a better bet to filter the digital jitter, using > the MSB of your phase accumulator as the reference? > -- Rick CArticle: 159228
On 05/09/2016 11:57, rickman wrote: > On 9/4/2016 3:13 PM, Mike Perkins wrote: >> On 04/09/2016 19:11, John Larkin wrote: >>> >>> >>> I have a design that will use a DDS synthesizer to generate an >>> internal trigger rate for a pulse generator. The chip will be a ZYNQ >>> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >>> will have the usual, 48 bit or so, phase accumulator and sine lookup >>> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >>> turn drives an LC lowpass filter and a comparator. Standard stuff. >>> >>> But could such a clock be generated entirely inside the FPGA? >>> >>> Just using the MSB of the DDS phase accumulator works, but it will >>> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >>> MHz. I've got to look into some sort of outboard analog filtering to >>> clean up that single-bit clock, but I'm not optimistic. DDS is just >>> too weird. >>> >>> Do you suppose that one of the FPGA PLLs be used to clean up the DDS >>> clock, scrub the jitter somehow? That could maybe be used over a >>> modest range, octave maybe, followed by some dividers. >> >> That isn't how FPGA PLLs work. They add jitter rather than removing it! > > Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a > standard analog PLL and so *would* remove jitter. > > >>> Any other ideas for making a programmable-frequency clock with DDS >>> sort of resolution, but without all that outboard analog stuff? >>> >>> I've been playing with sorta DDS in LT Spice, using a quantizer to >>> approximate the DDS accumulator and DAC, but that's obviously not the >>> best tool for this. >> >> The jitter of a clock derived from within a FPGA would simply be related >> to the clock frequency used. >> >> If you use a 250MHz clock, as per the max frequency of many cheap FPGAs, >> then jitter will be 4ns (+ a small bit). > > Yes, you are clearly thinking of a digital PLL based on the digital > fabric of the FPGA. I assume John was talking about the dedicated PLLs > found in most FPGAS. Most of my experience is with Xilinx who I don't believe use analogue PLLs. Most FPGA PLLs are based on a variable length ring of gates which will have jitter as gates are switched in and out of the loop. Can you provide an example of a truly analogue PLL in a mainstream FPGA? -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.ukArticle: 159229
On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin wrote: > I have a design that will use a DDS synthesizer to generate an > internal trigger rate for a pulse generator. The chip will be a ZYNQ > 7020. The required upper frequency limit is maybe 20 MHz. The FPGA > will have the usual, 48 bit or so, phase accumulator and sine lookup > stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in > turn drives an LC lowpass filter and a comparator. Standard stuff. > > But could such a clock be generated entirely inside the FPGA? > > Just using the MSB of the DDS phase accumulator works, but it will > have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 > MHz. I've got to look into some sort of outboard analog filtering to > clean up that single-bit clock, but I'm not optimistic. DDS is just > too weird. > > Do you suppose that one of the FPGA PLLs be used to clean up the DDS > clock, scrub the jitter somehow? That could maybe be used over a > modest range, octave maybe, followed by some dividers. > > Any other ideas for making a programmable-frequency clock with DDS > sort of resolution, but without all that outboard analog stuff? > > I've been playing with sorta DDS in LT Spice, using a quantizer to > approximate the DDS accumulator and DAC, but that's obviously not the > best tool for this. Changing from a Zynq 7020 to a '030 or '015 would give you transceivers (GTX or GTP, respectively). This allows you to position the output transitions with much more precision. This would reduce your purely digital DDS jitter from 10ns p-p down to less than 100ps p-p (for the '030 GTX in mid-speed grade) or 160ps p-p (for the '015 GTP in the fastest speed grade or ~270ps in the slowest speed grade). IOW, the '015 gives you about a 40 times reduction in p-p jitter for about the same cost as the '020. Plus, the higher effective sampling rate changes the spectral characteristics of the jitter and you will find it easier to locate a clean band in which to position your output signal. You might be tempted to use one of the onboard PLLs to clean this up, but they generate about that amount of jitter all by themselves, so there's probably not much net gain in doing that (along with some pitfalls). The transceivers have another advantage - they have independent power supplies and PLLs so you won't have activity in the FPGA fabric causing output jitter as you do with normal logic outputs. I'm sure you (or someone in your company) will know how to connect up a DDS to a transceiver to do this. Ask if you need hints. Regards, AllanArticle: 159230
On 09/04/2016 11:11 AM, John Larkin wrote: > > > I have a design that will use a DDS synthesizer to generate an > internal trigger rate for a pulse generator. The chip will be a ZYNQ > 7020. The required upper frequency limit is maybe 20 MHz. The FPGA > will have the usual, 48 bit or so, phase accumulator and sine lookup > stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in > turn drives an LC lowpass filter and a comparator. Standard stuff. > > But could such a clock be generated entirely inside the FPGA? > > Just using the MSB of the DDS phase accumulator works, but it will > have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 > MHz. I've got to look into some sort of outboard analog filtering to > clean up that single-bit clock, but I'm not optimistic. DDS is just > too weird. Is the analog signal from your sine generator used elsewhere in the system? If not, I don't see any advantage to using an external asynchronous analog comparator on an analog signal. You will pick up at least one clock cycle of jitter re-syncing the incoming analog signal to the digital clock. Then you have the jitter from the delays out to the DAC, the filter delays and the comparator jitter to add in. If the digital logic for the timing generator is not in the same clock domain as the system receiving it, you will pick up at least one clock cycle of jitter in the clock boundary transition. The only way I can think of to reduce the total jitter is the use as fast a clock as you can, and keep everything in one clock domain. Then you only have the clock source jitter that effects the entire system. Good Luck, BobHArticle: 159231
On 9/5/2016 7:47 AM, Mike Perkins wrote: > On 05/09/2016 11:57, rickman wrote: >> On 9/4/2016 3:13 PM, Mike Perkins wrote: >>> On 04/09/2016 19:11, John Larkin wrote: >>>> >>>> >>>> I have a design that will use a DDS synthesizer to generate an >>>> internal trigger rate for a pulse generator. The chip will be a ZYNQ >>>> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >>>> will have the usual, 48 bit or so, phase accumulator and sine lookup >>>> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >>>> turn drives an LC lowpass filter and a comparator. Standard stuff. >>>> >>>> But could such a clock be generated entirely inside the FPGA? >>>> >>>> Just using the MSB of the DDS phase accumulator works, but it will >>>> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >>>> MHz. I've got to look into some sort of outboard analog filtering to >>>> clean up that single-bit clock, but I'm not optimistic. DDS is just >>>> too weird. >>>> >>>> Do you suppose that one of the FPGA PLLs be used to clean up the DDS >>>> clock, scrub the jitter somehow? That could maybe be used over a >>>> modest range, octave maybe, followed by some dividers. >>> >>> That isn't how FPGA PLLs work. They add jitter rather than removing it! >> >> Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a >> standard analog PLL and so *would* remove jitter. >> >> >>>> Any other ideas for making a programmable-frequency clock with DDS >>>> sort of resolution, but without all that outboard analog stuff? >>>> >>>> I've been playing with sorta DDS in LT Spice, using a quantizer to >>>> approximate the DDS accumulator and DAC, but that's obviously not the >>>> best tool for this. >>> >>> The jitter of a clock derived from within a FPGA would simply be related >>> to the clock frequency used. >>> >>> If you use a 250MHz clock, as per the max frequency of many cheap FPGAs, >>> then jitter will be 4ns (+ a small bit). >> >> Yes, you are clearly thinking of a digital PLL based on the digital >> fabric of the FPGA. I assume John was talking about the dedicated PLLs >> found in most FPGAS. > > Most of my experience is with Xilinx who I don't believe use analogue PLLs. > > Most FPGA PLLs are based on a variable length ring of gates which will > have jitter as gates are switched in and out of the loop. > > Can you provide an example of a truly analogue PLL in a mainstream FPGA? Xilinx uses a DLL, but I thought they also had a PLL capability. Everyone else uses a PLL. Lattice data sheet for the XP2 says... sysCLOCK™ PLLs • Up to four analog PLLs per device • Clock multiply, divide and phase shifting Altera Cyclone V says this... Phase-locked loops (PLLs) • Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB) • Integer mode and fractional mode I don't think you can do zero delay buffering if the adjustment is digital. Later in the document they say this... • Jitter attenuation and PLL-based clock recovery Superior jitter tolerance That's pretty compelling. -- Rick CArticle: 159232
On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote: > On 09/04/2016 11:11 AM, John Larkin wrote: >> >> >> I have a design that will use a DDS synthesizer to generate an internal >> trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The >> required upper frequency limit is maybe 20 MHz. The FPGA will have the >> usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at >> maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC >> lowpass filter and a comparator. Standard stuff. >> >> But could such a clock be generated entirely inside the FPGA? >> >> Just using the MSB of the DDS phase accumulator works, but it will have >> one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've >> got to look into some sort of outboard analog filtering to clean up >> that single-bit clock, but I'm not optimistic. DDS is just too weird. > > Is the analog signal from your sine generator used elsewhere in the > system? If not, I don't see any advantage to using an external > asynchronous analog comparator on an analog signal. You will pick up at > least one clock cycle of jitter re-syncing the incoming analog signal to > the digital clock. Then you have the jitter from the delays out to the > DAC, the filter delays and the comparator jitter to add in. > > If the digital logic for the timing generator is not in the same clock > domain as the system receiving it, you will pick up at least one clock > cycle of jitter in the clock boundary transition. > > The only way I can think of to reduce the total jitter is the use as > fast a clock as you can, and keep everything in one clock domain. Then > you only have the clock source jitter that effects the entire system. I had assumed that the pulse generator was outside the FPGA, and only the trigger rate was being generated inside the FPGA. It's not quite clear from the OP. AllanArticle: 159233
On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote: > On 09/04/2016 11:11 AM, John Larkin wrote: >> >> >> I have a design that will use a DDS synthesizer to generate an internal >> trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The >> required upper frequency limit is maybe 20 MHz. The FPGA will have the >> usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at >> maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC >> lowpass filter and a comparator. Standard stuff. >> >> But could such a clock be generated entirely inside the FPGA? >> >> Just using the MSB of the DDS phase accumulator works, but it will have >> one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've >> got to look into some sort of outboard analog filtering to clean up >> that single-bit clock, but I'm not optimistic. DDS is just too weird. > > Is the analog signal from your sine generator used elsewhere in the > system? If not, I don't see any advantage to using an external > asynchronous analog comparator on an analog signal. You will pick up at > least one clock cycle of jitter re-syncing the incoming analog signal to > the digital clock. Then you have the jitter from the delays out to the > DAC, the filter delays and the comparator jitter to add in. > > If the digital logic for the timing generator is not in the same clock > domain as the system receiving it, you will pick up at least one clock > cycle of jitter in the clock boundary transition. > > The only way I can think of to reduce the total jitter is the use as > fast a clock as you can, and keep everything in one clock domain. Then > you only have the clock source jitter that effects the entire system. > > Good Luck, > BobH I can't speak to what John is doing, but if he needs a variable-frequency pulse train with small jitter for some external purpose, then he needs some sort of DDS or PLL technique. Assuming that the FPGA clock is good and steady, one could get a finer than one-clock resolution by playing tricks like using four or eight output pins to a current DAC, which then charges a cap, which then feeds a comparator. Then one wouldn't need to have a whole DDS inside -- but one would still need some external analog stuff, and one would still need to depend on the FPGA to have a nice consistent clock edge. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159234
Den mandag den 5. september 2016 kl. 17.19.49 UTC+2 skrev rickman: > On 9/5/2016 7:47 AM, Mike Perkins wrote: > > On 05/09/2016 11:57, rickman wrote: > >> On 9/4/2016 3:13 PM, Mike Perkins wrote: > >>> On 04/09/2016 19:11, John Larkin wrote: > >>>> > >>>> > >>>> I have a design that will use a DDS synthesizer to generate an > >>>> internal trigger rate for a pulse generator. The chip will be a ZYNQ > >>>> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA > >>>> will have the usual, 48 bit or so, phase accumulator and sine lookup > >>>> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in > >>>> turn drives an LC lowpass filter and a comparator. Standard stuff. > >>>> > >>>> But could such a clock be generated entirely inside the FPGA? > >>>> > >>>> Just using the MSB of the DDS phase accumulator works, but it will > >>>> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 > >>>> MHz. I've got to look into some sort of outboard analog filtering to > >>>> clean up that single-bit clock, but I'm not optimistic. DDS is just > >>>> too weird. > >>>> > >>>> Do you suppose that one of the FPGA PLLs be used to clean up the DDS > >>>> clock, scrub the jitter somehow? That could maybe be used over a > >>>> modest range, octave maybe, followed by some dividers. > >>> > >>> That isn't how FPGA PLLs work. They add jitter rather than removing it! > >> > >> Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a > >> standard analog PLL and so *would* remove jitter. > >> > >> > >>>> Any other ideas for making a programmable-frequency clock with DDS > >>>> sort of resolution, but without all that outboard analog stuff? > >>>> > >>>> I've been playing with sorta DDS in LT Spice, using a quantizer to > >>>> approximate the DDS accumulator and DAC, but that's obviously not the > >>>> best tool for this. > >>> > >>> The jitter of a clock derived from within a FPGA would simply be related > >>> to the clock frequency used. > >>> > >>> If you use a 250MHz clock, as per the max frequency of many cheap FPGAs, > >>> then jitter will be 4ns (+ a small bit). > >> > >> Yes, you are clearly thinking of a digital PLL based on the digital > >> fabric of the FPGA. I assume John was talking about the dedicated PLLs > >> found in most FPGAS. > > > > Most of my experience is with Xilinx who I don't believe use analogue PLLs. > > > > Most FPGA PLLs are based on a variable length ring of gates which will > > have jitter as gates are switched in and out of the loop. > > > > Can you provide an example of a truly analogue PLL in a mainstream FPGA? > > Xilinx uses a DLL, but I thought they also had a PLL capability. > Everyone else uses a PLL. Lattice data sheet for the XP2 says... > used to use a DLL, I am quite sure Zynq has a real pll http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf -LasseArticle: 159235
On 9/5/2016 1:15 PM, Tim Wescott wrote: > On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote: > >> On 09/04/2016 11:11 AM, John Larkin wrote: >>> >>> >>> I have a design that will use a DDS synthesizer to generate an internal >>> trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The >>> required upper frequency limit is maybe 20 MHz. The FPGA will have the >>> usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at >>> maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC >>> lowpass filter and a comparator. Standard stuff. >>> >>> But could such a clock be generated entirely inside the FPGA? >>> >>> Just using the MSB of the DDS phase accumulator works, but it will have >>> one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've >>> got to look into some sort of outboard analog filtering to clean up >>> that single-bit clock, but I'm not optimistic. DDS is just too weird. >> >> Is the analog signal from your sine generator used elsewhere in the >> system? If not, I don't see any advantage to using an external >> asynchronous analog comparator on an analog signal. You will pick up at >> least one clock cycle of jitter re-syncing the incoming analog signal to >> the digital clock. Then you have the jitter from the delays out to the >> DAC, the filter delays and the comparator jitter to add in. >> >> If the digital logic for the timing generator is not in the same clock >> domain as the system receiving it, you will pick up at least one clock >> cycle of jitter in the clock boundary transition. >> >> The only way I can think of to reduce the total jitter is the use as >> fast a clock as you can, and keep everything in one clock domain. Then >> you only have the clock source jitter that effects the entire system. >> >> Good Luck, >> BobH > > I can't speak to what John is doing, but if he needs a variable-frequency > pulse train with small jitter for some external purpose, then he needs > some sort of DDS or PLL technique. > > Assuming that the FPGA clock is good and steady, one could get a finer > than one-clock resolution by playing tricks like using four or eight > output pins to a current DAC, which then charges a cap, which then feeds > a comparator. Then one wouldn't need to have a whole DDS inside -- but > one would still need some external analog stuff, and one would still need > to depend on the FPGA to have a nice consistent clock edge. When you say "whole DDS", it's not that much circuitry. Besides, John said he is using a 48 bit phase accumulator with a table lookup which will give terrible phase jitter. A table lookup is a very poor choice given the much better ways of high resolution phase to sine conversions possible. I'm not at all familiar with how you would control the current DAC if you don't use a DDS. Are you suggesting the conversion of phase directly to analog to create a sawtooth wave with the DAC? I don't think you want to charge a cap. That would give a curved ramp sawtooth. Maybe I'm not following at all. I don't know the Zynq parts, but nearly all other FPGAs have proper analog PLLs which will greatly reduce jitter. I believe the input frequency range is somewhat limited, so there may need to be some extra circuitry with the PLL to get the proper output frequency from the acceptable input frequencies. -- Rick CArticle: 159236
Bump. Still looking for these adapters. Please contact me if you have any. Thanks. On 8/31/2016 12:10 AM, Tim Regeant wrote: > My project needs to program a Xilinx XC7336 44PLCC. > > I have the software now and the HW-130 programming unit. > > Also have the HW-137-PC44/VQ44 adapter which I assumed would work with > the XC7336, but as it turns out it does not. > > So I need to find the adapter(s) below. If anyone can help out please > let me know. > > HW-133-PC44 > HW-133-PC68 > HW-133-PC84 > > For reference here is webpage showing the HW-133-PC68 adapter (middle > image): http://www.digital-circuitry.com/MyLAB_IC_PROG_HW-130.htm > > Also at this Xilinx support page > http://www.xilinx.com/support/answers/961.html it mentions the HW-120 > adapters are mostly compatible with the HW-130 programmer. > > So I could alternatively use these adapters if anyone has them: > > HW-126-PC44 > HW-126-PC68 > HW-126-PC84 > > Thanks for any help you may offer!Article: 159237
Dear All Could someone explain me how to make rectangle or/and text on video coming from camera. OSD for video I use Hamsterworks's and Anton's projects and they works separately, but how to add them together ? ref. links: http://hamsterworks.co.nz/mediawiki/index.php/OV7670_camera https://www.youtube.com/watch?v=WK5FT5RD1sU I use VHDL code and ML402, It highly appreciate your efforts for helping me , to get some link and explanation.. I cannot understand how is it works, and whether someone implemented this, i thought just to use rgb outpot 8 bit devided to 4 bits video and 4 bits for rectangle or text))): https://groups.google.com/forum/#!searchin/comp.arch.fpga/OSD$20vhdl%7Csort:relevance/comp.arch.fpga/Jryi-S8zyAo/Qh2mwRmtRHYJ is it possible implement this for me ?Article: 159238
rickman wrote: > On 9/5/2016 7:47 AM, Mike Perkins wrote: >> On 05/09/2016 11:57, rickman wrote: >>> On 9/4/2016 3:13 PM, Mike Perkins wrote: >>>> On 04/09/2016 19:11, John Larkin wrote: >>>>> >>>>> >>>>> I have a design that will use a DDS synthesizer to generate an >>>>> internal trigger rate for a pulse generator. The chip will be a ZYNQ >>>>> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >>>>> will have the usual, 48 bit or so, phase accumulator and sine lookup >>>>> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >>>>> turn drives an LC lowpass filter and a comparator. Standard stuff. >>>>> >>>>> But could such a clock be generated entirely inside the FPGA? >>>>> >>>>> Just using the MSB of the DDS phase accumulator works, but it will >>>>> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >>>>> MHz. I've got to look into some sort of outboard analog filtering to >>>>> clean up that single-bit clock, but I'm not optimistic. DDS is just >>>>> too weird. >>>>> >>>>> Do you suppose that one of the FPGA PLLs be used to clean up the DDS >>>>> clock, scrub the jitter somehow? That could maybe be used over a >>>>> modest range, octave maybe, followed by some dividers. >>>> >>>> That isn't how FPGA PLLs work. They add jitter rather than removing it! >>> >>> Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a >>> standard analog PLL and so *would* remove jitter. >>> >>> >>>>> Any other ideas for making a programmable-frequency clock with DDS >>>>> sort of resolution, but without all that outboard analog stuff? >>>>> >>>>> I've been playing with sorta DDS in LT Spice, using a quantizer to >>>>> approximate the DDS accumulator and DAC, but that's obviously not the >>>>> best tool for this. >>>> >>>> The jitter of a clock derived from within a FPGA would simply be related >>>> to the clock frequency used. >>>> >>>> If you use a 250MHz clock, as per the max frequency of many cheap FPGAs, >>>> then jitter will be 4ns (+ a small bit). >>> >>> Yes, you are clearly thinking of a digital PLL based on the digital >>> fabric of the FPGA. I assume John was talking about the dedicated PLLs >>> found in most FPGAS. >> >> Most of my experience is with Xilinx who I don't believe use analogue PLLs. >> >> Most FPGA PLLs are based on a variable length ring of gates which will >> have jitter as gates are switched in and out of the loop. >> >> Can you provide an example of a truly analogue PLL in a mainstream FPGA? > > Xilinx uses a DLL, but I thought they also had a PLL capability. > Everyone else uses a PLL. Lattice data sheet for the XP2 says... > > sysCLOCK™ PLLs > • Up to four analog PLLs per device > • Clock multiply, divide and phase shifting > > Altera Cyclone V says this... > > Phase-locked loops > (PLLs) > • Precision clock synthesis, clock delay compensation, and zero delay > buffering (ZDB) > • Integer mode and fractional mode > > I don't think you can do zero delay buffering if the adjustment is > digital. Later in the document they say this... > > • Jitter attenuation > > and > > PLL-based clock recovery Superior jitter tolerance > > That's pretty compelling. > The Cyclone series I at least know a thing about. There's an internal octave VCO that you spin up to somewhere in to 600-1300 MHz range, and then divide down. When I've looked at jitter performance a bit it's fairly good; below the measurement floor of cheap measurement equipment. I haven't really gone in with a spectrum analyzer to look for spurs, but I'd imagine there's not much point to it. That probably depends heavily on case-by-case power supply bypassing and exact programmed frequency (as well as whether you're using an integer or fractional divide) and is hard to talk about in any kind of general sense. The Zynq (at least according to the data sheet) does the same thing, VCO in the 800-2100 MHz range and divide down. Xilinx says nuttin' about the loop filter bandwidth, but Altera gives typs for their three switchable filters as 0.3, 1.5, and 4 MHz. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 159239
Den tirsdag den 6. september 2016 kl. 19.50.23 UTC+2 skrev Rob Gaddi: > rickman wrote: >=20 > > On 9/5/2016 7:47 AM, Mike Perkins wrote: > >> On 05/09/2016 11:57, rickman wrote: > >>> On 9/4/2016 3:13 PM, Mike Perkins wrote: > >>>> On 04/09/2016 19:11, John Larkin wrote: > >>>>> > >>>>> > >>>>> I have a design that will use a DDS synthesizer to generate an > >>>>> internal trigger rate for a pulse generator. The chip will be a ZYN= Q > >>>>> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA > >>>>> will have the usual, 48 bit or so, phase accumulator and sine looku= p > >>>>> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in > >>>>> turn drives an LC lowpass filter and a comparator. Standard stuff. > >>>>> > >>>>> But could such a clock be generated entirely inside the FPGA? > >>>>> > >>>>> Just using the MSB of the DDS phase accumulator works, but it will > >>>>> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 > >>>>> MHz. I've got to look into some sort of outboard analog filtering t= o > >>>>> clean up that single-bit clock, but I'm not optimistic. DDS is just > >>>>> too weird. > >>>>> > >>>>> Do you suppose that one of the FPGA PLLs be used to clean up the DD= S > >>>>> clock, scrub the jitter somehow? That could maybe be used over a > >>>>> modest range, octave maybe, followed by some dividers. > >>>> > >>>> That isn't how FPGA PLLs work. They add jitter rather than removing = it! > >>> > >>> Aren't you thinking of a digital PLL? The PLL in FPGAs is typically = a > >>> standard analog PLL and so *would* remove jitter. > >>> > >>> > >>>>> Any other ideas for making a programmable-frequency clock with DDS > >>>>> sort of resolution, but without all that outboard analog stuff? > >>>>> > >>>>> I've been playing with sorta DDS in LT Spice, using a quantizer to > >>>>> approximate the DDS accumulator and DAC, but that's obviously not t= he > >>>>> best tool for this. > >>>> > >>>> The jitter of a clock derived from within a FPGA would simply be rel= ated > >>>> to the clock frequency used. > >>>> > >>>> If you use a 250MHz clock, as per the max frequency of many cheap FP= GAs, > >>>> then jitter will be 4ns (+ a small bit). > >>> > >>> Yes, you are clearly thinking of a digital PLL based on the digital > >>> fabric of the FPGA. I assume John was talking about the dedicated PL= Ls > >>> found in most FPGAS. > >> > >> Most of my experience is with Xilinx who I don't believe use analogue = PLLs. > >> > >> Most FPGA PLLs are based on a variable length ring of gates which will > >> have jitter as gates are switched in and out of the loop. > >> > >> Can you provide an example of a truly analogue PLL in a mainstream FPG= A? > > > > Xilinx uses a DLL, but I thought they also had a PLL capability.=20 > > Everyone else uses a PLL. Lattice data sheet for the XP2 says... > > > > sysCLOCK=E2=84=A2 PLLs > > =E2=80=A2 Up to four analog PLLs per device > > =E2=80=A2 Clock multiply, divide and phase shifting > > > > Altera Cyclone V says this... > > > > Phase-locked loops > > (PLLs) > > =E2=80=A2 Precision clock synthesis, clock delay compensation, and zero= delay=20 > > buffering (ZDB) > > =E2=80=A2 Integer mode and fractional mode > > > > I don't think you can do zero delay buffering if the adjustment is=20 > > digital. Later in the document they say this... > > > > =E2=80=A2 Jitter attenuation > > > > and > > > > PLL-based clock recovery Superior jitter tolerance > > > > That's pretty compelling. > > >=20 > The Cyclone series I at least know a thing about. There's an internal > octave VCO that you spin up to somewhere in to 600-1300 MHz range, and > then divide down. When I've looked at jitter performance a bit it's > fairly good; below the measurement floor of cheap measurement > equipment. I haven't really gone in with a spectrum analyzer to look > for spurs, but I'd imagine there's not much point to it. That probably > depends heavily on case-by-case power supply bypassing and exact > programmed frequency (as well as whether you're using an integer or > fractional divide) and is hard to talk about in any kind of general > sense. >=20 > The Zynq (at least according to the data sheet) does the same thing, VCO > in the 800-2100 MHz range and divide down. >=20 > Xilinx says nuttin' about the loop filter bandwidth, but Altera gives > typs for their three switchable filters as 0.3, 1.5, and 4 MHz. >=20 Zynq datasheet say 1MHz and 4MHz also says max input clock jitter 20% or 1ns -LasseArticle: 159240
On Sunday, September 4, 2016 at 12:11:40 PM UTC-6, John Larkin wrote: > I have a design that will use a DDS synthesizer to generate an > internal trigger rate for a pulse generator. The chip will be a ZYNQ > 7020. The required upper frequency limit is maybe 20 MHz. The FPGA > will have the usual, 48 bit or so, phase accumulator and sine lookup > stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in > turn drives an LC lowpass filter and a comparator. Standard stuff. >=20 > But could such a clock be generated entirely inside the FPGA? You could use a single-bit DAC (like a Sigma-Delta DAC) filtered by a 1-pol= e RC filter and then run back into an LVDS input. So then you'd just have = the RC filter external. But I don't know if the oversampling rate (100MHz/= 20MHz) is enough precision. Another option is to use the lower bits of your phase accumulator to add ph= ase to the output using the ODELAY blocks. You can get a precision of 78ps= if you use 200MHz as your reference clock. However, I'm not certain how o= ften you can update the ODELAY delay value.=20Article: 159241
On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote: > > >I have a design that will use a DDS synthesizer to generate an >internal trigger rate for a pulse generator. The chip will be a ZYNQ >7020. The required upper frequency limit is maybe 20 MHz. The FPGA >will have the usual, 48 bit or so, phase accumulator and sine lookup >stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >turn drives an LC lowpass filter and a comparator. Standard stuff. > >But could such a clock be generated entirely inside the FPGA? > >Just using the MSB of the DDS phase accumulator works, but it will >have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >MHz. I've got to look into some sort of outboard analog filtering to >clean up that single-bit clock, but I'm not optimistic. DDS is just >too weird. > >Do you suppose that one of the FPGA PLLs be used to clean up the DDS >clock, scrub the jitter somehow? That could maybe be used over a >modest range, octave maybe, followed by some dividers. > >Any other ideas for making a programmable-frequency clock with DDS >sort of resolution, but without all that outboard analog stuff? > >I've been playing with sorta DDS in LT Spice, using a quantizer to >approximate the DDS accumulator and DAC, but that's obviously not the >best tool for this. Well, it's looking like I'll just use an external DDS chip, AD9835 probably, with the usual LC lowpass filter and comparator. I can clock that from a handy 50 MHz oscillator that we need for the Ethernet phy. Looks like trying to do this inside the FPGA is too risky, jitter and such. That close to Nyquist, I will need a good filter. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.comArticle: 159242
On Mon, 05 Sep 2016 22:52:33 -0400, rickman wrote: > On 9/5/2016 1:15 PM, Tim Wescott wrote: >> On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote: >> >>> On 09/04/2016 11:11 AM, John Larkin wrote: >>>> >>>> >>>> I have a design that will use a DDS synthesizer to generate an >>>> internal trigger rate for a pulse generator. The chip will be a ZYNQ >>>> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >>>> will have the usual, 48 bit or so, phase accumulator and sine lookup >>>> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >>>> turn drives an LC lowpass filter and a comparator. Standard stuff. >>>> >>>> But could such a clock be generated entirely inside the FPGA? >>>> >>>> Just using the MSB of the DDS phase accumulator works, but it will >>>> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >>>> MHz. I've got to look into some sort of outboard analog filtering to >>>> clean up that single-bit clock, but I'm not optimistic. DDS is just >>>> too weird. >>> >>> Is the analog signal from your sine generator used elsewhere in the >>> system? If not, I don't see any advantage to using an external >>> asynchronous analog comparator on an analog signal. You will pick up >>> at least one clock cycle of jitter re-syncing the incoming analog >>> signal to the digital clock. Then you have the jitter from the delays >>> out to the DAC, the filter delays and the comparator jitter to add in. >>> >>> If the digital logic for the timing generator is not in the same clock >>> domain as the system receiving it, you will pick up at least one clock >>> cycle of jitter in the clock boundary transition. >>> >>> The only way I can think of to reduce the total jitter is the use as >>> fast a clock as you can, and keep everything in one clock domain. Then >>> you only have the clock source jitter that effects the entire system. >>> >>> Good Luck, >>> BobH >> >> I can't speak to what John is doing, but if he needs a >> variable-frequency pulse train with small jitter for some external >> purpose, then he needs some sort of DDS or PLL technique. >> >> Assuming that the FPGA clock is good and steady, one could get a finer >> than one-clock resolution by playing tricks like using four or eight >> output pins to a current DAC, which then charges a cap, which then >> feeds a comparator. Then one wouldn't need to have a whole DDS inside >> -- but one would still need some external analog stuff, and one would >> still need to depend on the FPGA to have a nice consistent clock edge. > > When you say "whole DDS", it's not that much circuitry. Besides, John > said he is using a 48 bit phase accumulator with a table lookup which > will give terrible phase jitter. A table lookup is a very poor choice > given the much better ways of high resolution phase to sine conversions > possible. > > I'm not at all familiar with how you would control the current DAC if > you don't use a DDS. Are you suggesting the conversion of phase > directly to analog to create a sawtooth wave with the DAC? I don't > think you want to charge a cap. That would give a curved ramp sawtooth. > Maybe I'm not following at all. > > I don't know the Zynq parts, but nearly all other FPGAs have proper > analog PLLs which will greatly reduce jitter. I believe the input > frequency range is somewhat limited, so there may need to be some extra > circuitry with the PLL to get the proper output frequency from the > acceptable input frequencies. I was thinking along the lines of generating a programmable delay after the clock tick -- with all due respect for the fact that it won't be perfect, in a number of ways. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159243
On 9/6/2016 5:38 PM, Tim Wescott wrote: > On Mon, 05 Sep 2016 22:52:33 -0400, rickman wrote: > >> On 9/5/2016 1:15 PM, Tim Wescott wrote: >>> On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote: >>> >>>> On 09/04/2016 11:11 AM, John Larkin wrote: >>>>> >>>>> >>>>> I have a design that will use a DDS synthesizer to generate an >>>>> internal trigger rate for a pulse generator. The chip will be a ZYNQ >>>>> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >>>>> will have the usual, 48 bit or so, phase accumulator and sine lookup >>>>> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >>>>> turn drives an LC lowpass filter and a comparator. Standard stuff. >>>>> >>>>> But could such a clock be generated entirely inside the FPGA? >>>>> >>>>> Just using the MSB of the DDS phase accumulator works, but it will >>>>> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >>>>> MHz. I've got to look into some sort of outboard analog filtering to >>>>> clean up that single-bit clock, but I'm not optimistic. DDS is just >>>>> too weird. >>>> >>>> Is the analog signal from your sine generator used elsewhere in the >>>> system? If not, I don't see any advantage to using an external >>>> asynchronous analog comparator on an analog signal. You will pick up >>>> at least one clock cycle of jitter re-syncing the incoming analog >>>> signal to the digital clock. Then you have the jitter from the delays >>>> out to the DAC, the filter delays and the comparator jitter to add in. >>>> >>>> If the digital logic for the timing generator is not in the same clock >>>> domain as the system receiving it, you will pick up at least one clock >>>> cycle of jitter in the clock boundary transition. >>>> >>>> The only way I can think of to reduce the total jitter is the use as >>>> fast a clock as you can, and keep everything in one clock domain. Then >>>> you only have the clock source jitter that effects the entire system. >>>> >>>> Good Luck, >>>> BobH >>> >>> I can't speak to what John is doing, but if he needs a >>> variable-frequency pulse train with small jitter for some external >>> purpose, then he needs some sort of DDS or PLL technique. >>> >>> Assuming that the FPGA clock is good and steady, one could get a finer >>> than one-clock resolution by playing tricks like using four or eight >>> output pins to a current DAC, which then charges a cap, which then >>> feeds a comparator. Then one wouldn't need to have a whole DDS inside >>> -- but one would still need some external analog stuff, and one would >>> still need to depend on the FPGA to have a nice consistent clock edge. >> >> When you say "whole DDS", it's not that much circuitry. Besides, John >> said he is using a 48 bit phase accumulator with a table lookup which >> will give terrible phase jitter. A table lookup is a very poor choice >> given the much better ways of high resolution phase to sine conversions >> possible. >> >> I'm not at all familiar with how you would control the current DAC if >> you don't use a DDS. Are you suggesting the conversion of phase >> directly to analog to create a sawtooth wave with the DAC? I don't >> think you want to charge a cap. That would give a curved ramp sawtooth. >> Maybe I'm not following at all. >> >> I don't know the Zynq parts, but nearly all other FPGAs have proper >> analog PLLs which will greatly reduce jitter. I believe the input >> frequency range is somewhat limited, so there may need to be some extra >> circuitry with the PLL to get the proper output frequency from the >> acceptable input frequencies. > > I was thinking along the lines of generating a programmable delay after > the clock tick -- with all due respect for the fact that it won't be > perfect, in a number of ways. Ok, I got you. That's interesting. It requires the same external equipment as the traditional sine wave DDS with a DAC, analog filter and comparator except for the filter with the addition of something to zero out the integrator. The value fed to the DAC would need to be scaled to the inverse of the phase step size, a PITA in digital. That likely would be done in a look up table. This is all feasible, but I don't know how piratical to get the jitter from 10 ns down to say, 100 ps. -- Rick CArticle: 159244
On 9/6/2016 4:22 PM, John Larkin wrote: > On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin > <jjlarkin@highlandtechnology.com> wrote: > >> >> >> I have a design that will use a DDS synthesizer to generate an >> internal trigger rate for a pulse generator. The chip will be a ZYNQ >> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >> will have the usual, 48 bit or so, phase accumulator and sine lookup >> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >> turn drives an LC lowpass filter and a comparator. Standard stuff. >> >> But could such a clock be generated entirely inside the FPGA? >> >> Just using the MSB of the DDS phase accumulator works, but it will >> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >> MHz. I've got to look into some sort of outboard analog filtering to >> clean up that single-bit clock, but I'm not optimistic. DDS is just >> too weird. >> >> Do you suppose that one of the FPGA PLLs be used to clean up the DDS >> clock, scrub the jitter somehow? That could maybe be used over a >> modest range, octave maybe, followed by some dividers. >> >> Any other ideas for making a programmable-frequency clock with DDS >> sort of resolution, but without all that outboard analog stuff? >> >> I've been playing with sorta DDS in LT Spice, using a quantizer to >> approximate the DDS accumulator and DAC, but that's obviously not the >> best tool for this. > > Well, it's looking like I'll just use an external DDS chip, AD9835 > probably, with the usual LC lowpass filter and comparator. I can clock > that from a handy 50 MHz oscillator that we need for the Ethernet phy. > > Looks like trying to do this inside the FPGA is too risky, jitter and > such. That close to Nyquist, I will need a good filter. Then it might be a good idea to use the FPGA to double or quadruple the 50 MHz clock and run the external DDS with that. -- Rick CArticle: 159245
On Tuesday, September 6, 2016 at 11:22:12 PM UTC+3, John Larkin wrote: > > Well, it's looking like I'll just use an external DDS chip, AD9835 > probably, with the usual LC lowpass filter and comparator. I can clock > that from a handy 50 MHz oscillator that we need for the Ethernet phy. > AD9835 has single-ended DAC output, right? I don't see how you achieve jitter in picosecond range when you start with single-ended 20MHz signal followed by filter and comparator. Ground drift alone will put jitter into 10s of ps range, but more likely into over 100 ps. Another problem is a input clock to AD9835 which is also single-ended and also have relatively low frequency (50 MHz). Again, ground noise would be translated into relatively high jitter. Or do you say that the all jitter *before* low-pass (or band-pass) filter is of no significance? I am not sure that it is true. > > Looks like trying to do this inside the FPGA is too risky, jitter and > such. That close to Nyquist, I will need a good filter. > > > > > -- > > John Larkin Highland Technology, Inc > picosecond timing precision measurement > > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.comArticle: 159246
On Wed, 7 Sep 2016 04:10:32 -0700 (PDT), already5chosen@yahoo.com wrote: >On Tuesday, September 6, 2016 at 11:22:12 PM UTC+3, John Larkin wrote: >> >> Well, it's looking like I'll just use an external DDS chip, AD9835 >> probably, with the usual LC lowpass filter and comparator. I can clock >> that from a handy 50 MHz oscillator that we need for the Ethernet phy. >> > >AD9835 has single-ended DAC output, right? >I don't see how you achieve jitter in picosecond range when you start with single-ended 20MHz signal followed by filter and comparator. Ground drift alone will put jitter into 10s of ps range, but more likely into over 100 ps. Proper PCB layout will prevent ground loop voltages. The DDS output is a current source, which helps a lot. A passive LC filter can be terminated at one end, at the comparator. > >Another problem is a input clock to AD9835 which is also single-ended and also have relatively low frequency (50 MHz). Again, ground noise would be translated into relatively high jitter. Single-ended logic signals can have fs RMS jitter. Again, ground loops should be avoided. I can put the 50 MHz XO close to the DDS, and run a long trace to the Ethernet gadget; it doesn't care much about jitter. >Or do you say that the all jitter *before* low-pass (or band-pass) filter is of no significance? I am not sure that it is true. I don't recall saying that. But since I only need an octave clock range, a bandpass filter will reject both high and low-frequency jitter that's out of the filter's passband. At an octave bw, it's about a toss-up between an official bandpass filter and cascaded lowpass+highpass filters. A tunable narrowband filter would be cool. It could track the DDS frequency. There are a few interesting ways to do that. But that would be work, and a brute-force long elliptical filter would be as good. All of which is wandering off the FPGA topic. -- John Larkin Highland Technology, Inc lunatic fringe electronicsArticle: 159247
Den s=C3=B8ndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin: > I have a design that will use a DDS synthesizer to generate an > internal trigger rate for a pulse generator. The chip will be a ZYNQ > 7020. The required upper frequency limit is maybe 20 MHz. The FPGA > will have the usual, 48 bit or so, phase accumulator and sine lookup > stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in > turn drives an LC lowpass filter and a comparator. Standard stuff. >=20 > But could such a clock be generated entirely inside the FPGA? >=20 > Just using the MSB of the DDS phase accumulator works, but it will > have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 > MHz. I've got to look into some sort of outboard analog filtering to > clean up that single-bit clock, but I'm not optimistic. DDS is just > too weird. >=20 > Do you suppose that one of the FPGA PLLs be used to clean up the DDS > clock, scrub the jitter somehow? That could maybe be used over a > modest range, octave maybe, followed by some dividers. >=20 > Any other ideas for making a programmable-frequency clock with DDS > sort of resolution, but without all that outboard analog stuff? >=20 > I've been playing with sorta DDS in LT Spice, using a quantizer to > approximate the DDS accumulator and DAC, but that's obviously not the > best tool for this. >=20 https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get = ~20MHz ch2, through a PLL in jitter filtermode=20 with an increment that results in exactly 25MHz: =20 https://www.dropbox.com/s/9rizod2e15mxlhs/dds_pll1.jpg -LasseArticle: 159248
On Wed, 7 Sep 2016 12:55:12 -0700 (PDT), lasselangwadtchristensen@gmail.com wrote: >Den søndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin: >> I have a design that will use a DDS synthesizer to generate an >> internal trigger rate for a pulse generator. The chip will be a ZYNQ >> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA >> will have the usual, 48 bit or so, phase accumulator and sine lookup >> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in >> turn drives an LC lowpass filter and a comparator. Standard stuff. >> >> But could such a clock be generated entirely inside the FPGA? >> >> Just using the MSB of the DDS phase accumulator works, but it will >> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 >> MHz. I've got to look into some sort of outboard analog filtering to >> clean up that single-bit clock, but I'm not optimistic. DDS is just >> too weird. >> >> Do you suppose that one of the FPGA PLLs be used to clean up the DDS >> clock, scrub the jitter somehow? That could maybe be used over a >> modest range, octave maybe, followed by some dividers. >> >> Any other ideas for making a programmable-frequency clock with DDS >> sort of resolution, but without all that outboard analog stuff? >> >> I've been playing with sorta DDS in LT Spice, using a quantizer to >> approximate the DDS accumulator and DAC, but that's obviously not the >> best tool for this. >> > >https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg > >ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get ~20MHz >ch2, through a PLL in jitter filtermode Looks like classic DDS squirmies. The PLL is not filtering the jitter much. With a clock/Fout ratio of 5:1, 0.4 x Nyquist, a DDS and an LC lowpass filter usually looks pretty good. A PLL, considered as a tracking bandpass filter, could potentially be a good DDS cleanup. > >with an increment that results in exactly 25MHz: > >https://www.dropbox.com/s/9rizod2e15mxlhs/dds_pll1.jpg That's the moral equivalent of dividing 100 MHz by 4! Thanks, interesting stuff. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.comArticle: 159249
Den onsdag den 7. september 2016 kl. 23.49.29 UTC+2 skrev John Larkin: > On Wed, 7 Sep 2016 12:55:12 -0700 (PDT), > lasselangwadtchristensen@gmail.com wrote: >=20 > >Den s=C3=B8ndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Lark= in: > >> I have a design that will use a DDS synthesizer to generate an > >> internal trigger rate for a pulse generator. The chip will be a ZYNQ > >> 7020. The required upper frequency limit is maybe 20 MHz. The FPGA > >> will have the usual, 48 bit or so, phase accumulator and sine lookup > >> stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in > >> turn drives an LC lowpass filter and a comparator. Standard stuff. > >>=20 > >> But could such a clock be generated entirely inside the FPGA? > >>=20 > >> Just using the MSB of the DDS phase accumulator works, but it will > >> have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 > >> MHz. I've got to look into some sort of outboard analog filtering to > >> clean up that single-bit clock, but I'm not optimistic. DDS is just > >> too weird. > >>=20 > >> Do you suppose that one of the FPGA PLLs be used to clean up the DDS > >> clock, scrub the jitter somehow? That could maybe be used over a > >> modest range, octave maybe, followed by some dividers. > >>=20 > >> Any other ideas for making a programmable-frequency clock with DDS > >> sort of resolution, but without all that outboard analog stuff? > >>=20 > >> I've been playing with sorta DDS in LT Spice, using a quantizer to > >> approximate the DDS accumulator and DAC, but that's obviously not the > >> best tool for this. > >>=20 > > > >https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg > > > >ch1, MSB from 100MHz, 32 bit accumulator with some random increment to g= et ~20MHz > >ch2, through a PLL in jitter filtermode=20 >=20 > Looks like classic DDS squirmies. The PLL is not filtering the jitter > much. With a clock/Fout ratio of 5:1, 0.4 x Nyquist, a DDS and an LC > lowpass filter usually looks pretty good. maybe it's possible to have the filter and then run it back in to the FPGA = and through fpga PLL? though lowest BW for the PLL is 1MHz I tried upping the clock to 400MHz and it got quite a lot better, but I've = only got a TDS210 scope here so it's hard to tell how much better >=20 > A PLL, considered as a tracking bandpass filter, could potentially be > a good DDS cleanup. put the DDS inside the loop ? >=20 > > > >with an increment that results in exactly 25MHz: > >=20 > >https://www.dropbox.com/s/9rizod2e15mxlhs/dds_pll1.jpg >=20 >=20 > That's the moral equivalent of dividing 100 MHz by 4! I know, it was a sanity check ;) -Lasse
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