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Hello i am new in vhdl, but try it, I want to make pipe between OV7670 and monitor, best thing is to use code o= f Hamsterwork's with Lauri's edition http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670 and=20 http://lauri.v=F5sandi.com/hdl/zynq/zybo-ov7670-to-vga.html and want to ado= pt it to ML402 for Virtex-4 XC4VSX35, it requires 8 bit for each color in R= GB,and bram address can be only 18bit wide, i made edition but cannot get a= ny picture, link to this video on youtube=20 https://youtu.be/Tr-9UzEL-D8 code i modified, top_level, capture, vga, memory, clocking http://download.files.namba.kg/files/147527022 pass :'123' could someone help to check for video and code , what problem with which si= gnal ?Article: 158576
On 1/5/2016 6:44 AM, abirov@gmail.com wrote: > Hello i am new in vhdl, but try it, > I want to make pipe between OV7670 and monitor, best thing is to use code of Hamsterwork's with Lauri's edition > http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670 and > http://lauri.võsandi.com/hdl/zynq/zybo-ov7670-to-vga.html and want to adopt it to ML402 for Virtex-4 XC4VSX35, it requires 8 bit for each color in RGB,and bram address can be only 18bit wide, i made edition but cannot get any picture, link to this video on youtube > https://youtu.be/Tr-9UzEL-D8 > code i modified, top_level, capture, vga, memory, clocking > > http://download.files.namba.kg/files/147527022 pass :'123' > > could someone help to check for video and code , what problem with which signal ? Have you tried running this in a simulator? Did you create timing constraints and use the timing analysis tool? -- RickArticle: 158577
On January 5th, 2016, David Wade sent: |--------------------------------------------------------------------| |"[. . .] | | | |For this project 14.1 on Windows/10 (there is a minor hack to get it| |owrking).... | | | |Dave | |G4UGM" | |--------------------------------------------------------------------| Is Windows 10 better or worse than other operating systems for FPGA work? Regards, Paul Colin GlosterArticle: 158578
> Have you tried running this in a simulator? Did you create timing > constraints and use the timing analysis tool? I do not know how to do it, I will route it and use oscilloscopeArticle: 158579
On 1/6/2016 1:35 AM, abirov@gmail.com wrote: >> Have you tried running this in a simulator? Did you create timing >> constraints and use the timing analysis tool? > > I do not know how to do it, I will route it and use oscilloscope You need to learn how to design FPGAs properly. A simulator is not hard to use. Most of the work is in writing a VHDL test bench to properly exercise your design. The timing analysis tool lets you specify the timing required in your design such as clock cycle times, time from signal input to the clock and from the clock to signal outputs. Trying to do this with an oscilloscope is nearly impossible for any internal signals. The timing analysis tool lets you do this as part of your design process without loading the design onto your board. -- RickArticle: 158580
On 06/01/16 06:35, abirov@gmail.com wrote: >> Have you tried running this in a simulator? Did you create timing >> constraints and use the timing analysis tool? > > I do not know how to do it, I will route it and use oscilloscope If you haven't tested the design before routing then there is no reason to believe your circuit does what you would like it to do. If you haven't tested the design after place and route then there is no reason to believe you specified your system requirements correctly, nor that the tool satisfied the unstated requirements (naturally!), nor even that it was able to satisfy the stated requirements.Article: 158581
--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
D:\xilinx_core\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3
-s 12 -n 3 -fastpaths -xml ov7670_top_preroute.twx ov7670_top_map.ncd -o
ov7670_top_preroute.twr ov7670_top.pcf -ucf constraint.ucf
Design file: ov7670_top_map.ncd
Physical constraint file: ov7670_top.pcf
Device,package,speed: xc4vsx35,ff668,-12 (PRODUCTION 1.71 2013-10-13, STEPPING level 1)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock OV7670_PCLK
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
OV7670_D<0> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<1> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<2> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<3> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<4> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<5> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<6> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<7> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_HREF | -0.353(R)| 0.912(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_VSYNC| 0.259(R)| 0.852(R)|OV7670_PCLK_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock clk100
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
btn | 2.830(R)| -2.133(R)|clk50 | 0.000|
------------+------------+------------+------------------+--------+
Clock clk100 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
Nblank | 2.358(R)|clk25 | 0.000|
OV7670_SIOC | 2.066(R)|clk50 | 0.000|
OV7670_SIOD | 2.358(R)|clk50 | 0.000|
OV7670_XCLK | 2.066(R)|clk50 | 0.000|
led | 2.358(R)|clk50 | 0.000|
vga_blue<0> | 2.066(R)|clk25 | 0.000|
vga_blue<1> | 2.066(R)|clk25 | 0.000|
vga_blue<2> | 2.066(R)|clk25 | 0.000|
vga_blue<3> | 2.066(R)|clk25 | 0.000|
vga_blue<4> | 2.066(R)|clk25 | 0.000|
vga_blue<5> | 2.066(R)|clk25 | 0.000|
vga_blue<6> | 2.066(R)|clk25 | 0.000|
vga_blue<7> | 2.066(R)|clk25 | 0.000|
vga_green<0>| 2.066(R)|clk25 | 0.000|
vga_green<1>| 2.066(R)|clk25 | 0.000|
vga_green<2>| 2.066(R)|clk25 | 0.000|
vga_green<3>| 2.066(R)|clk25 | 0.000|
vga_green<4>| 2.066(R)|clk25 | 0.000|
vga_green<5>| 2.066(R)|clk25 | 0.000|
vga_green<6>| 2.066(R)|clk25 | 0.000|
vga_green<7>| 2.066(R)|clk25 | 0.000|
vga_hsync | 2.066(R)|clk25 | 0.000|
vga_red<0> | 2.066(R)|clk25 | 0.000|
vga_red<1> | 2.066(R)|clk25 | 0.000|
vga_red<2> | 2.066(R)|clk25 | 0.000|
vga_red<3> | 2.066(R)|clk25 | 0.000|
vga_red<4> | 2.066(R)|clk25 | 0.000|
vga_red<5> | 2.066(R)|clk25 | 0.000|
vga_red<6> | 2.066(R)|clk25 | 0.000|
vga_red<7> | 2.066(R)|clk25 | 0.000|
vga_vsync | 2.066(R)|clk25 | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock OV7670_PCLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
OV7670_PCLK | 1.543| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk100
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk100 | 3.571| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
clk100 |clkout | 1.808|
---------------+---------------+---------+
Analysis completed Wed Jan 06 16:51:22 2016
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 330 MB
Article: 158582On 05/01/2016 17:18, Nicholas Collin Paul de Gloucester wrote: > On January 5th, 2016, David Wade sent: > |--------------------------------------------------------------------| > |"[. . .] | > | | > |For this project 14.1 on Windows/10 (there is a minor hack to get it| > |owrking).... | > | | > |Dave | > |G4UGM" | > |--------------------------------------------------------------------| > > Is Windows 10 better or worse than other operating systems for FPGA > work? I think Windows/7 is pobably still better. I use 10 because I need it for other reasons. I have XP in a VMWARE VM for A parrallel printer port programmer... > > Regards, > Paul Colin GlosterArticle: 158583
I just ran across this: http://www.eetimes.com/author.asp? section_id=36&doc_id=1328618&_mc=sm_eet_editor_maxmaxfield&hootPostID=09e55671236236acbe4121d86cb78c72 http://tinyurl.com/zhdcerx It looks like it could be a nifty thing to use in certain circumstances, particularly where one needs a complicated analog block in little space with fairly high bandwidth (yes, I know -- it's digital inside, but I don't care about that if it's analog outside). Anyone have any mileage with the company or any predecessor products? Do you know of any competing products out there? It looks like a good arrow to have in my quiver, if it can meet the expectations they're trying to set. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 158584
On 07/01/16 19:14, Tim Wescott wrote: > I just ran across this: > > http://www.eetimes.com/author.asp? > section_id=36&doc_id=1328618&_mc=sm_eet_editor_maxmaxfield&hootPostID=09e55671236236acbe4121d86cb78c72 > (If you put < > around your pasted urls, they will work fine in newsreaders without wrapping issues - there is no need for tinyurl's.) <http://www.eetimes.com/author.asp?section_id=36&doc_id=1328618> > http://tinyurl.com/zhdcerx > > It looks like it could be a nifty thing to use in certain circumstances, > particularly where one needs a complicated analog block in little space > with fairly high bandwidth (yes, I know -- it's digital inside, but I > don't care about that if it's analog outside). > > Anyone have any mileage with the company or any predecessor products? Do > you know of any competing products out there? It looks like a good arrow > to have in my quiver, if it can meet the expectations they're trying to > set. > I have been trying to find an excuse to use one of these things in a product - they look so fun! This new device, with in-system programmability by I²C (I'm guessing that you can burn the NVM via the I²C, as well as just change the current RAM-based configuration) opens up new possibilities. For the previous generations, you had to either order a gazillion factory-programmed devices or program them by hand using the development kit. That's great for people making hundreds of thousands of boards, and for people making tens of boards, but not for those making hundreds and thousands. The I²C programmability and reconfigurability makes them interesting for a wider range of uses.Article: 158585
On Fri, 08 Jan 2016 10:10:52 +0100, David Brown wrote: > On 07/01/16 19:14, Tim Wescott wrote: >> I just ran across this: >> http://tinyurl.com/zhdcerx >> It looks like it could be a nifty thing to use in certain >> circumstances, >> particularly where one needs a complicated analog block in little space >> with fairly high bandwidth (yes, I know -- it's digital inside, but I >> don't care about that if it's analog outside). > I have been trying to find an excuse to use one of these things in a > product - they look so fun! This new device, with in-system > programmability by I²C (I'm guessing that you can burn the NVM via the > I²C, as well as just change the current RAM-based configuration) opens > up new possibilities. All of this sounds like sex, but what would I use it for? Maybe I need to do more analog (or at least asynchronous) to be able to think of something.Article: 158586
On Fri, 08 Jan 2016 15:38:26 +0000, Aleksandar Kuktin wrote: > On Fri, 08 Jan 2016 10:10:52 +0100, David Brown wrote: > >> On 07/01/16 19:14, Tim Wescott wrote: >>> I just ran across this: > >>> http://tinyurl.com/zhdcerx > >>> It looks like it could be a nifty thing to use in certain >>> circumstances, >>> particularly where one needs a complicated analog block in little >>> space with fairly high bandwidth (yes, I know -- it's digital inside, >>> but I don't care about that if it's analog outside). > >> I have been trying to find an excuse to use one of these things in a >> product - they look so fun! This new device, with in-system >> programmability by I²C (I'm guessing that you can burn the NVM via the >> I²C, as well as just change the current RAM-based configuration) opens >> up new possibilities. > > All of this sounds like sex, but what would I use it for? Maybe I need > to do more analog (or at least asynchronous) to be able to think of > something. I tend to close a lot of control loops in software; there's a definite ceiling in what you can use a microcontroller with because of code execution speed. Something that I can think of off the top of my head for a chip like this would be as a controller in a snazzy switching supply, assuming that there's enough resources on board to implement a controller as well as a proper PWM generator. At today's switching speeds one can't really do cycle-by-cycle control with a microcontroller -- one should be able to with an FPGA or CPLD. -- www.wescottdesign.comArticle: 158587
On 08/01/16 20:52, Tim Wescott wrote: > I tend to close a lot of control loops in software; there's a definite > ceiling in what you can use a microcontroller with because of code > execution speed. Have a look at the XMOS processors and boards. Cheap, many cores (i.e. >10) and execution time for each code block is /guaranteed/ by the compiler. Low jitter and guaranteed timing helps in control loops! Many of the architectural concepts are by Prof David May, who had a large hand in inventing the Transputer and Occam.Article: 158588
On Wednesday, January 6, 2016 at 4:09:15 PM UTC+6, Tom Gardner wrote:
> On 06/01/16 06:35, abirov@gmail.com wrote:
> >> Have you tried running this in a simulator? Did you create timing
> >> constraints and use the timing analysis tool?
> >
> > I do not know how to do it, I will route it and use oscilloscope
>
> If you haven't tested the design before routing then there
> is no reason to believe your circuit does what you would
> like it to do.
>
> If you haven't tested the design after place and route then
> there is no reason to believe you specified your system
> requirements correctly, nor that the tool satisfied the
> unstated requirements (naturally!), nor even that it was
> able to satisfy the stated requirements.
All values displayed in nanoseconds (ns)
Setup/Hold to clock OV7670_PCLK
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
OV7670_D<0> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<1> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<2> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<3> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<4> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<5> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<6> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_D<7> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_HREF | -0.353(R)| 0.912(R)|OV7670_PCLK_BUFGP | 0.000|
OV7670_VSYNC| 0.259(R)| 0.852(R)|OV7670_PCLK_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock clk100
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
btn | 2.830(R)| -2.133(R)|clk50 | 0.000|
------------+------------+------------+------------------+--------+
Clock clk100 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
Nblank | 2.358(R)|clk25 | 0.000|
OV7670_SIOC | 2.066(R)|clk50 | 0.000|
OV7670_SIOD | 2.358(R)|clk50 | 0.000|
OV7670_XCLK | 2.066(R)|clk50 | 0.000|
led | 2.358(R)|clk50 | 0.000|
vga_blue<0> | 2.066(R)|clk25 | 0.000|
vga_blue<1> | 2.066(R)|clk25 | 0.000|
vga_blue<2> | 2.066(R)|clk25 | 0.000|
vga_blue<3> | 2.066(R)|clk25 | 0.000|
vga_blue<4> | 2.066(R)|clk25 | 0.000|
vga_blue<5> | 2.066(R)|clk25 | 0.000|
vga_blue<6> | 2.066(R)|clk25 | 0.000|
vga_blue<7> | 2.066(R)|clk25 | 0.000|
vga_green<0>| 2.066(R)|clk25 | 0.000|
vga_green<1>| 2.066(R)|clk25 | 0.000|
vga_green<2>| 2.066(R)|clk25 | 0.000|
vga_green<3>| 2.066(R)|clk25 | 0.000|
vga_green<4>| 2.066(R)|clk25 | 0.000|
vga_green<5>| 2.066(R)|clk25 | 0.000|
vga_green<6>| 2.066(R)|clk25 | 0.000|
vga_green<7>| 2.066(R)|clk25 | 0.000|
vga_hsync | 2.066(R)|clk25 | 0.000|
vga_red<0> | 2.066(R)|clk25 | 0.000|
vga_red<1> | 2.066(R)|clk25 | 0.000|
vga_red<2> | 2.066(R)|clk25 | 0.000|
vga_red<3> | 2.066(R)|clk25 | 0.000|
vga_red<4> | 2.066(R)|clk25 | 0.000|
vga_red<5> | 2.066(R)|clk25 | 0.000|
vga_red<6> | 2.066(R)|clk25 | 0.000|
vga_red<7> | 2.066(R)|clk25 | 0.000|
vga_vsync | 2.066(R)|clk25 | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock OV7670_PCLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
OV7670_PCLK | 1.543| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk100
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk100 | 3.571| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
clk100 |clkout | 1.808|
---------------+---------------+---------+
Analysis completed Wed Jan 06 16:51:22 2016
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 330 MB
Could someone help to me ??????????? Guys???
Article: 158589On Fri, 08 Jan 2016 19:50:49 -0800, abirov wrote: > On Wednesday, January 6, 2016 at 4:09:15 PM UTC+6, Tom Gardner wrote: >> On 06/01/16 06:35, abirov@gmail.com wrote: >> >> Have you tried running this in a simulator? Did you create timing >> >> constraints and use the timing analysis tool? >> > >> > I do not know how to do it, I will route it and use oscilloscope >> >> If you haven't tested the design before routing then there is no reason >> to believe your circuit does what you would like it to do. > > Could someone help to me ??????????? Guys??? You have already been given helpful advice. Simulate, get it working in simulation. It's your choice to use or ignore that advice, that's not our problem. -- BrianArticle: 158590
On 1/8/2016 3:52 PM, Tim Wescott wrote: > On Fri, 08 Jan 2016 15:38:26 +0000, Aleksandar Kuktin wrote: > >> On Fri, 08 Jan 2016 10:10:52 +0100, David Brown wrote: >> >>> On 07/01/16 19:14, Tim Wescott wrote: >>>> I just ran across this: >> >>>> http://tinyurl.com/zhdcerx >> >>>> It looks like it could be a nifty thing to use in certain >>>> circumstances, >>>> particularly where one needs a complicated analog block in little >>>> space with fairly high bandwidth (yes, I know -- it's digital inside, >>>> but I don't care about that if it's analog outside). >> >>> I have been trying to find an excuse to use one of these things in a >>> product - they look so fun! This new device, with in-system >>> programmability by I²C (I'm guessing that you can burn the NVM via the >>> I²C, as well as just change the current RAM-based configuration) opens >>> up new possibilities. >> >> All of this sounds like sex, but what would I use it for? Maybe I need >> to do more analog (or at least asynchronous) to be able to think of >> something. > > I tend to close a lot of control loops in software; there's a definite > ceiling in what you can use a microcontroller with because of code > execution speed. > > Something that I can think of off the top of my head for a chip like this > would be as a controller in a snazzy switching supply, assuming that > there's enough resources on board to implement a controller as well as a > proper PWM generator. At today's switching speeds one can't really do > cycle-by-cycle control with a microcontroller -- one should be able to > with an FPGA or CPLD. Microsemi bought Actel some time back and their mixed signal FPGA. I have never done anything with it because the price is a bit too high for some apps I've had and the analog performance was too low for others. Mixed signal can be hard to do well. Two companies who could do it well are Analog devices and Silicon Labs. They both have produced mixed signal MCUs with great analog. They just need to branch out into FPGAs, lol. -- RickArticle: 158591
On 1/8/2016 10:50 PM, abirov@gmail.com wrote: > On Wednesday, January 6, 2016 at 4:09:15 PM UTC+6, Tom Gardner wrote: >> On 06/01/16 06:35, abirov@gmail.com wrote: >>>> Have you tried running this in a simulator? Did you create timing >>>> constraints and use the timing analysis tool? >>> >>> I do not know how to do it, I will route it and use oscilloscope >> >> If you haven't tested the design before routing then there >> is no reason to believe your circuit does what you would >> like it to do. >> >> If you haven't tested the design after place and route then >> there is no reason to believe you specified your system >> requirements correctly, nor that the tool satisfied the >> unstated requirements (naturally!), nor even that it was >> able to satisfy the stated requirements. > > All values displayed in nanoseconds (ns) > > Setup/Hold to clock OV7670_PCLK > ------------+------------+------------+------------------+--------+ > |Max Setup to|Max Hold to | | Clock | > Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | > ------------+------------+------------+------------------+--------+ > OV7670_D<0> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<1> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<2> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<3> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<4> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<5> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<6> | -0.375(R)| 0.760(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_D<7> | -0.277(R)| 0.670(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_HREF | -0.353(R)| 0.912(R)|OV7670_PCLK_BUFGP | 0.000| > OV7670_VSYNC| 0.259(R)| 0.852(R)|OV7670_PCLK_BUFGP | 0.000| > ------------+------------+------------+------------------+--------+ > > Setup/Hold to clock clk100 > ------------+------------+------------+------------------+--------+ > |Max Setup to|Max Hold to | | Clock | > Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | > ------------+------------+------------+------------------+--------+ > btn | 2.830(R)| -2.133(R)|clk50 | 0.000| > ------------+------------+------------+------------------+--------+ > > Clock clk100 to Pad > ------------+------------+------------------+--------+ > | clk (edge) | | Clock | > Destination | to PAD |Internal Clock(s) | Phase | > ------------+------------+------------------+--------+ > Nblank | 2.358(R)|clk25 | 0.000| > OV7670_SIOC | 2.066(R)|clk50 | 0.000| > OV7670_SIOD | 2.358(R)|clk50 | 0.000| > OV7670_XCLK | 2.066(R)|clk50 | 0.000| > led | 2.358(R)|clk50 | 0.000| > vga_blue<0> | 2.066(R)|clk25 | 0.000| > vga_blue<1> | 2.066(R)|clk25 | 0.000| > vga_blue<2> | 2.066(R)|clk25 | 0.000| > vga_blue<3> | 2.066(R)|clk25 | 0.000| > vga_blue<4> | 2.066(R)|clk25 | 0.000| > vga_blue<5> | 2.066(R)|clk25 | 0.000| > vga_blue<6> | 2.066(R)|clk25 | 0.000| > vga_blue<7> | 2.066(R)|clk25 | 0.000| > vga_green<0>| 2.066(R)|clk25 | 0.000| > vga_green<1>| 2.066(R)|clk25 | 0.000| > vga_green<2>| 2.066(R)|clk25 | 0.000| > vga_green<3>| 2.066(R)|clk25 | 0.000| > vga_green<4>| 2.066(R)|clk25 | 0.000| > vga_green<5>| 2.066(R)|clk25 | 0.000| > vga_green<6>| 2.066(R)|clk25 | 0.000| > vga_green<7>| 2.066(R)|clk25 | 0.000| > vga_hsync | 2.066(R)|clk25 | 0.000| > vga_red<0> | 2.066(R)|clk25 | 0.000| > vga_red<1> | 2.066(R)|clk25 | 0.000| > vga_red<2> | 2.066(R)|clk25 | 0.000| > vga_red<3> | 2.066(R)|clk25 | 0.000| > vga_red<4> | 2.066(R)|clk25 | 0.000| > vga_red<5> | 2.066(R)|clk25 | 0.000| > vga_red<6> | 2.066(R)|clk25 | 0.000| > vga_red<7> | 2.066(R)|clk25 | 0.000| > vga_vsync | 2.066(R)|clk25 | 0.000| > ------------+------------+------------------+--------+ > > Clock to Setup on destination clock OV7670_PCLK > ---------------+---------+---------+---------+---------+ > | Src:Rise| Src:Fall| Src:Rise| Src:Fall| > Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| > ---------------+---------+---------+---------+---------+ > OV7670_PCLK | 1.543| | | | > ---------------+---------+---------+---------+---------+ > > Clock to Setup on destination clock clk100 > ---------------+---------+---------+---------+---------+ > | Src:Rise| Src:Fall| Src:Rise| Src:Fall| > Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| > ---------------+---------+---------+---------+---------+ > clk100 | 3.571| | | | > ---------------+---------+---------+---------+---------+ > > Pad to Pad > ---------------+---------------+---------+ > Source Pad |Destination Pad| Delay | > ---------------+---------------+---------+ > clk100 |clkout | 1.808| > ---------------+---------------+---------+ > > > Analysis completed Wed Jan 06 16:51:22 2016 > -------------------------------------------------------------------------------- > > Trace Settings: > ------------------------- > Trace Settings > > Peak Memory Usage: 330 MB > > Could someone help to me ??????????? Guys??? Others have explained that you will debug the logic of your design much more easily in a simulation than on the bench. Debugging in the chip is hard because you need to bring signals out to see what his happening. The simulator allows you to view any signal at any time. You can get waveform displays, or probe signals in a list showing the current value. You can even walk through the code with breakpoints if that is how you like to do it (I never use this but others do). Then, once you have the logic working correctly you can deal with timing issues. To use the timing analysis you need to create timing constraints. These constraints consist of clock period (or frequency), input clock setup times and output delay times. If you don't understand what these timing constraints mean then you need to ask questions. Just posting part of a timing report and saying "help" isn't the way to get useful help. Here is a pointer. In your previous post the tool gives you one very important error message.... INFO:Timing:2698 - No timing constraints found, doing default enumeration. -- RickArticle: 158592
On Fri, 08 Jan 2016 14:52:13 -0600, Tim Wescott wrote: > On Fri, 08 Jan 2016 15:38:26 +0000, Aleksandar Kuktin wrote: >> All of this sounds like sex, but what would I use it for? Maybe I need >> to do more analog (or at least asynchronous) to be able to think of >> something. > > I tend to close a lot of control loops in software; there's a definite > ceiling in what you can use a microcontroller with because of code > execution speed. > > Something that I can think of off the top of my head for a chip like > this would be as a controller in a snazzy switching supply, assuming > that there's enough resources on board to implement a controller as well > as a proper PWM generator. At today's switching speeds one can't really > do cycle-by-cycle control with a microcontroller -- one should be able > to with an FPGA or CPLD. Hmm... an idea. :) Yesterday, I also thought of a thread, but I think it was on sci.electronics.design, where it was asked if such-and-such circuit exists, and one of the answers being to implement the required device in digital.Article: 158593
On January 6th, 2016, David Wade sent: |-------------------------------------------------------------------------| |"On 05/01/2016 17:18, Nicholas Collin Paul de Gloucester wrote: | |> On January 5th, 2016, David Wade sent: | |> |--------------------------------------------------------------------| | |> |"[. . .] | | |> | | | |> |For this project 14.1 on Windows/10 (there is a minor hack to get it| | |> |owrking).... | | |> | | | |> |Dave | | |> |G4UGM" | | |> |--------------------------------------------------------------------| | |> | |> Is Windows 10 better or worse than other operating systems for FPGA | |> work? | | | |I think Windows/7 is pobably still better. I use 10 because I need it for| |other reasons. I have XP in a VMWARE VM for A parrallel printer port | |programmer..." | |-------------------------------------------------------------------------| Thanks for this feedback. Regards, Paul Colin de GloucesterArticle: 158594
wireshark showed that webchat uses curl to access "www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?topic=webtalkupload HTTP/1.1\r\n". For some reason I can't turn off webchat even though I have a full licenses. Setting http_proxy, https_proxy and ftp_proxy at least blocked Xilinx's bigbrother-ware.Article: 158595
webtalk uses curl under the covers, so setting http_proxy, https_proxy and ftp_proxy will at least block Xilinx's bigbrother-ware.Article: 158596
Is there synthesis software out there that'll take Verilog or other HDL and generate a netlist of 7400-series logic? To carry things one step further, if you were seriously contemplating such a thing, of course you'd want the software to understand that chips and boards are of finite sizes, that propagation delays between chips and boards exist, and that board-board connections have finite numbers of pins. So -- has it been done, perhaps by someone with way too much time on their hands? How big is an ARM M1 core when it's implemented in discrete logic chips that are currently available in the DigiKey catalog? And how fast? -- www.wescottdesign.comArticle: 158597
Solved, problem was in ov7670, camera board was broken or smth else, when i change it, it starts to work.Article: 158598
We are interested in finding someone to help develop an FPGA image capture = application. We are using Altera's MAX10 FPGA and Arrow's BeMicro MAX10 dev= elopment board. The image sensor is the MT9V034. It will transfer captured = images to a Raspberry Pi over a SPI interface.Article: 158599
On 01/18/2016 07:37 PM, Tim Wescott wrote: > Is there synthesis software out there that'll take Verilog or other HDL > and generate a netlist of 7400-series logic? Interesting idea, but moving in the opposite direction of progress (grin). You could probably make a technology library for a standard synthesis package, but handling the multiple gates/package might be a problem. > > So -- has it been done, perhaps by someone with way too much time on > their hands? How big is an ARM M1 core when it's implemented in discrete > logic chips that are currently available in the DigiKey catalog? And how > fast? > It would probably be about the size of a PDP11-34 and run at 10MHz instead of 50MHz, but this is very much a WAG. BobH
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