Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
http://c64upgra.de/c-one/JRISCDoc020704.pdf antti altera.openchip.orgArticle: 65851
Rene Tschaggelar wrote: > > Rick Collins wrote: > > That part is true, but I think most of the expense is by the maker, the > > disti only has one support person for any given manufacturer. It is not > > that much of a cost burden for them. And they will very much limit the > > amount of support they give you if you are not a large customer. > > > > Unfortunately this as wrong, as you can get wrong. > This may have been this way years ago and it proved wrong. The > distributors realized that luckily. The business works a bit > different. There are companies who want a new product and pay for the > development. There are those who do a development and there are others > who actually manufacture the parts. The first mentioned company sells > the final products then. Now who needs the support, and who buys the > most parts ? > As developper, I seldom buy more than 10 pieces. But also I introduce > the new technologies into many other companies, be they my costomers > or may they become my customers. Meaning there is no sense in flooding > those who buy the most parts with PR materials. The decisions are done > long befoe they buy the parts. I think we may have a bit of a language barrier, so your points are not completely clear. I am sure the salesmen know the difference between a small company building a small volume product and a small company building a large volume product for another company. On the other hand, I have been told point blank that it can be very hard for the FAEs and salesmen to track a project between companies in this way and as a result, they do not get the credit (or the profit) from the ultimate sale. So they are very reluctant to devote much time to such projects. I got this straight from the horses mouth (so to speak). They are much more inclined to assist the companies who design the products they sell in large numbers and as a result you can count on both support and a good parts price. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 65852
rickman wrote: > Rene Tschaggelar wrote: > >>Rick Collins wrote: >> >>>That part is true, but I think most of the expense is by the maker, the >>>disti only has one support person for any given manufacturer. It is not >>>that much of a cost burden for them. And they will very much limit the >>>amount of support they give you if you are not a large customer. >>> >> >>Unfortunately this as wrong, as you can get wrong. >>This may have been this way years ago and it proved wrong. The >>distributors realized that luckily. The business works a bit >>different. There are companies who want a new product and pay for the >>development. There are those who do a development and there are others >>who actually manufacture the parts. The first mentioned company sells >>the final products then. Now who needs the support, and who buys the >>most parts ? >>As developper, I seldom buy more than 10 pieces. But also I introduce >>the new technologies into many other companies, be they my costomers >>or may they become my customers. Meaning there is no sense in flooding >>those who buy the most parts with PR materials. The decisions are done >>long befoe they buy the parts. > > > I think we may have a bit of a language barrier, so your points are not > completely clear. I am sure the salesmen know the difference between a > small company building a small volume product and a small company > building a large volume product for another company. On the other hand, > I have been told point blank that it can be very hard for the FAEs and > salesmen to track a project between companies in this way and as a > result, they do not get the credit (or the profit) from the ultimate > sale. So they are very reluctant to devote much time to such projects. > I got this straight from the horses mouth (so to speak). > > They are much more inclined to assist the companies who design the > products they sell in large numbers and as a result you can count on > both support and a good parts price. > Ok. My points. It may work the way you described where there are plenty of big companies doing big projects. Over here, many big companies are a mere shaddow of themselves after the new economy took over and they were rationalized to death or near death. Many new small businesses took over the lead in applying technology. I'm lucky that my distributor, selling Altera parts (amongst others), takes the time to provide me with, compared with my sales volume, excessive support. Yes, we may talk about who the project is for. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 65853
I've recently written a Java command-line application called BlockGen that generates a memory module in VHDL using Xilinx Block RAM given a set of parameters and an input file in Altera MIF (.mif) format or be a text file containing hex data. Although you can do the similar types of things with Xilinx's CoreGen utility, this is useful in situations where you want to share files with people using the free WebPack version of ISE which doesn't come with CoreGen, besides which converting hex data in .mif and other text files is a cumbersome process. Hope you find this useful: http://www.anuff.com/ed/projects/BlockGen.zip Feedback welcome. Thanks EdArticle: 65854
If you want an idea of what it might have go search the patent office..... Steve "Peter Alfke" <peter@xilinx.com> wrote in message news:40241030.DC005E6B@xilinx.com... > Manfred, be assured that Xilinx will announce a new Virtex family this > year, and be also assured that the family will include MGTs and PPC > microprocessors. Don't worry about the exact family names, that's a > marketing issue. > The best stuff is still to come ! > > Peter Alfke > =================== > Manfred Kraus wrote: > > > > I heard rumours XILINX will announce Virtex-3 later this year, > > but a VIRTEX-3 PRO is not planned. > > Will FPGAs with integrated Processors share the destiny of the X6200 series > > ?Article: 65855
That link does not work for me... Steve "Peter Foord" <pfoord@iee.org.uk> wrote in message news:72dbb0dd.0402060853.78020386@posting.google.com... > The IEE (a UK-based professional engineering society) has organised an > online technology debate on the relative merits of programmable logic, > ASICs and gate arrays, with a panel of industry speakers. The event > takes place on 24 February from 16.00 GMT - registration (free of > charge) is required. Full details can be found at > http://www.iee.tv/techdebateArticle: 65856
Steve Casselman wrote: > That link does not work for me... >>The IEE (a UK-based professional engineering society) has organised an >>online technology debate on the relative merits of programmable logic, >>ASICs and gate arrays, with a panel of industry speakers. The event >>takes place on 24 February from 16.00 GMT - registration (free of >>charge) is required. Full details can be found at >>http://www.iee.tv/techdebate It seems to be at http://www.iee.org/techdebate/ I don't know why they would be at iee.tv. -- glenArticle: 65857
Hello, I have a newbie problem that is probably easy to solve. I have 4 data streams entering Virtex II FPGA through LVDS standard (each stream is 4 wires, 2 clock and 2 data). This is fine as I am able to receive the signals each individually i.e. data from each stream is clock by only their respective clock and the data does not interact with each other. What I want to do is to treat each stream as a bit of a word i.e. have them all clocked by a single clock. Because these streams are independent clock phases and probably clock jitter is not equal, though frequency should nominally be equal. Is there a way to generate a single clock and/or correct for phase differences on the data streams so that can can treat the data as a single "word"? How should I look at this problem? HerwinArticle: 65858
On Fri, 06 Feb 2004 14:07:44 -0800, Peter Alfke <peter@xilinx.com> wrote: >Manfred, be assured that Xilinx will announce a new Virtex family this >year, and be also assured that the family will include MGTs and PPC >microprocessors. Don't worry about the exact family names, that's a >marketing issue. They should skip Virtex-3 and go straight to Virtex-4, which would allow them to align the Spartan and Virtex numbers. Allan.Article: 65859
Hi, "Invisible One" <Invisible_1@sympatico.ca> wrote: > 1 - What software and hardware tools are available that operate well under > Windows (compilation, etc...)? You can do the whole design flow for Fpgas under Windows (mostly NT). Normaly you get the tools from the Fpga vendor. > 2 - Has anyone had any experience with programming AI's on FPGAa? Are there > tools available for FPGA development? Don't know any tools, but there are different people doing AI on VLSI. Feed google with Linear-Integrate-and-Fire for a start in the topic. > 3 - Are there any programmable logic devices out there that have a ADC built > in? You can build an ADC using digital logic an an external RC cirquit. The result is ok for 3-5 bits resolution. The more bits, the more effort you will have to do in the external cirquit (e.g doing an active lowpass with higher order instead of an passive). bye ThomasArticle: 65860
Hi, I am looking for a reasonably priced front-end toolset for VHDL multi-vendor FPGA design. This should as a minimum provide: * VHDL design entry (text based and high level graphical) * Functional simulation (testbenches with file I/O) * Post-synthesis and timing (post-PAR) simulation. For this I am considering ActiveHDL, but since we also do a lot of hardware design using the Protel schematic and PCB tools, the new nVisage DXP version with integrated VHDL front-end tools looks interesting. As anybody used these tools in nVisage or DXP and has any opinion on their maturity, features and quality? Thanks! NikiArticle: 65861
We have two CPLDs on a board (Altera EPM7256A and Xilinx XCR3064XL) and would like to program them with a single tool. To complicate things further, the tool should work in Linux. The download cable we use is Xilinx Parallel Cable III, but if this is a real problem, it can be replaced by something else. It seems there are no tools which would do this without some patching. I have been thinking of taking the Altera JAM player and patching it for the Xilinx cable. This should be quite straightforward, as only a few things need to be changed in the jamstub.c. (BTW, has anybody any experience on compiling the JAM player with gcc?) Then the workflow would be: - Altera: Quartus II Web Edition -> .jam -> JAM player - Xilinx: ISE WebPack iMpact -> .jam -> JAM player The big question, however, is: does it work? I have no doubt about the Altera path, as JAM is invented by Altera. But what about the Xilinx JAM compatibility. iMpact seems to be able to produce either .svf or .jam files, but does either of these work reliably (svf throuth svf2jam) with the JAM player? On the Xilinx site I found something on the need of patching the JAM player. Is this enough, or is there still something else? TIA, - Ville -- Ville Voipio, Dr.Tech., M.Sc. (EE)Article: 65862
On Sun, 8 Feb 2004 22:02:43 -0800, "Herwin" <herwinc@ucla.edu> wrote: >Hello, > >I have a newbie problem that is probably easy to solve. > >I have 4 data streams entering Virtex II FPGA through LVDS standard (each >stream is 4 wires, 2 clock and 2 data). This is fine as I am able to >receive the >signals each individually i.e. data from each stream is clock by only their >respective >clock and the data does not interact with each other. > >What I want to do is to treat each stream as a bit of a word i.e. have them >all >clocked by a single clock. Because these streams are independent clock >phases >and probably clock jitter is not equal, though frequency should nominally be >equal. > >Is there a way to generate a single clock and/or correct for phase >differences on the >data streams so that can can treat the data as a single "word"? How should >I look >at this problem? Does your system meet the following requirements? 1. The average frequency is exactly the same on all four channels. (You said "nominally equal" but that could mean anything.) 2. You can put an upper limit on the instantaneous phase difference between channels. 3. Each channel contains a unique data pattern (frame marker, etc.) that would allow you to work out the phase difference between the channels. If so, then I recommend the following: Have four independent FIFOs. Each FIFO takes its input from one of the channels. The output of all FIFOs are clocked from the same source, which would be the input clock on *one* of the FIFOs, or any other clock with the same frequency (e.g. one of the input clocks that has been filtered by a PLL). The FIFO size is determined by the maximum phase difference from #2 (above). Have a control input on the FIFO that allows you to adjust the depth (by fiddling the pointers - it doesn't matter if this trashes the data briefly during the adjustment), and control this such that the frame markers (from #3, above) line up on the outputs of all four FIFOs. BTW, this is very common technique. It is done in some variants of 10G Ethernet (that recombine four 3.125Gbps 8B10B streams into one 10Gbps stream). Regards, Allan.Article: 65863
"Rick Collins" <spamgoeshere4@yahoo.com> wrote in message news:40255850.62EF5633@yahoo.com... > Steve wrote:> > So why are your small quantity prices so inflated? > > Perhaps you should take an econ class, all kidding aside. I had a very > brief one in high school and the most basic concept (next to guns vs. > butter) is that of fixed costs vs. marginal costs. Even though they > don't *make* the parts in 100 unit lots, there are fixed costs > associated with selling them in 100 unit lots. This mainly has to do > with support, I would expect. > > But there is also the issue of motivation. If you are running a company > that has customers buying literally millions of parts a year and > customers buying 100's of parts a year, are you going to give the small > customer anywhere near the same prices as the big customer? No, you are > going to shave every possible penny on the price you must to keep the > big customer from buying the competitor's parts. The 100 unit customer > is not even a consideration. But _every_ big customer started as a small customer, and if you can get people trained up and familiar with your P&R software and design process it's a big risk for them to change to a competitor. The problem is that if X does this A will _have_ to follow suit. It's an oligopoly, it's in both their interests to keep low volume prices up. > Besides, if you are buying only 100 of a part, is it a big issue if you > pay 2x for the part? If you are building a product, you are likely > selling the product for 3, 5 or even 10x your parts cost. Otherwise you > will be losing a little on each one you sell, and will be out of > business soon. It depends what the product it. If it's a custom product for someone the BOM cost is probably insignificant in the overall product development cost. If you're a small company trying to get a novel product out it can be a very big issue, FPGA pricing is likely to dominate your overall product cost, making the product viable or not. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 65864
Rick Collins <spamgoeshere4@yahoo.com> wrote in message news:<402559B3.AFBBB736@yahoo.com>... > Rene Tschaggelar wrote: > > The cost is at the FPGA representative, distributing the stuff. > > They get the questions asked. > > No, the distis only have as much markup as the maker allows. I have > been though the quotation cycle and nothing gets done without Xilinx > authorizing it. So Xilinx /do/ fix their prices. Surely this is against competition laws?? -- SteveArticle: 65865
"Antti Lukats" <antti@case2000.com> writes: > there is JAM for linux version at sourceforge > compiling JAM is pretty easy, modifying for new hardware also I tried finding the sourceforge version, but could not. Do you have a more precise pointer? I think I forgot to mention that the software should work in Cygwin, as well. So, the PPI requires some thinking. My first idea is to take the PPI driver from avrdude, where it is able to handle both Cygwin and Linux. > patching: we had big big big problems programming Xilinx devices with JAM > player > anyway we tried the output files from iMpact just didnt work, not directly > not > via SVF2JAM This is exactly what I was afraid of. > I got some patch to fix some issues in JAM player, Xilinx site does carry a patch, so maybe I'll try it first. > this info may be outdated I have not checked it with latest iMpact version > maybe the compatibilty is better now I'll need to check. Thanks! - Ville -- Ville Voipio, Dr.Tech., M.Sc. (EE)Article: 65866
As there are no responces I'm wondering if there is anyone who has used the plugs-library and/or c++ on the nios softcore?Article: 65867
Hello, I wanted the relationship between the number of iteration vs LUT table entry. Because i wanted to estimate the arc tan to a accuracy of 1 microradians. In my simulation i found that even if the iteration is around 25 iteration i could not achieve the 1 microradian accuracy. My LUT i have represented using 32 bit and the two number whos atan is to be obtained is also 32 bit(all fixed point). Please suggest a solution with regards praveenArticle: 65868
steve41@totalise.co.uk (Steve) wrote in message news:<4d3ee211.0402070631.4ee1b54@posting.google.com>... > Rene Tschaggelar <none@none.net> wrote in message news:<402405f0$0$714$5402220f@news.sunrise.ch>... > > > > I can understand that attitude for people buying ten thousand chips; > > > but where do you expect people to get the experience with FPGAs that > > > they have with microprocessors, when state-of-the-art FPGAs are two > > > orders of magnitude more expensive and an order of magnitude less > > > convenient to acquire? > > > > The cost is at the FPGA representative, distributing the stuff. > > They get the questions asked. > > > Xilinx have a revenue of $1.2bn according to this: > > http://finance.yahoo.com/q/is?s=xlnx > > Are you seriously trying to say that the cost of an FPGA > representative being asked questions has anything other than a > negligible effect on the prices of FPGAs? In-state factory FAEs, Disty FAEs. Sales teams that must be incentivized to drum up demand for new parts. Then customers who go out and convert their FPGA to CGAs as soon as production ramps up. FPGAs are not like CPUs. They are often prototype platforms. Low volume, abandoned by the customer as soon as the design is stable and can be converted to a CGA or ASIC. FPGAs are inexpensive in my view, and the software tools are amazing. It's a good time to be an engineer. But if you know a way to bring the equivalent of a Xilinx offering for 25% of the price, join the marketplace, please.Article: 65869
On Mon, 09 Feb 2004 17:11:31 +1100, Allan Herriman wrote: > On Fri, 06 Feb 2004 14:07:44 -0800, Peter Alfke <peter@xilinx.com> > wrote: > >>Manfred, be assured that Xilinx will announce a new Virtex family this >>year, and be also assured that the family will include MGTs and PPC >>microprocessors. Don't worry about the exact family names, that's a >>marketing issue. > > They should skip Virtex-3 and go straight to Virtex-4, which would > allow them to align the Spartan and Virtex numbers. > > Allan. The local Xilinx guys told me that they are donig exactly that, calling the next family Virtex4 instead of 3 so that it will match the Spartan numbers.Article: 65870
Hi,
Has anyone here taken VHDL training classes from Xilinx?
http://www.xilinx.com/support/training/abstracts/adv-vhdl.htm
Are they any good?/worth the money?
Any review/feedback on those classes would be appreciated
Jakub
Article: 65871
Re: your title...."Challenges" are for managers and manger wanna-bes
who have been taught that "problem" is a four letter word. Problems
are solved by engineers.
Does the Virtex E have a DCM?
Anyway, as somebody else pointed out, use enables (which end up in the
combinatorial logic of your D inputs).
if(clk'event and clk='1') then
if(slow_en='1') then
q<=d;
end if;
end if;
Geir Botterli <geirb@fokk.org> wrote in message news:<308520dbkbv5fm4m3h0ap35n21rrgbqn8e@4ax.com>...
> Greetings, this is my first posting to this group, but I've been
> following the discussions for some time.
>
> I have a small problem which I'm trying to solve:
>
> My design has a Virtex E, and I need to generate a 1MHz clock and a
> 4MHz clock from a single clock source. The are to be used internally
> and they need to be synchronized. My problem is that the CLKDLLE
> primitive needs a CLKIN of at least 25MHz. I can supply that, I have
> an external oscillator tunable from 0 (or very low at least) to 40MHz.
> But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to
> create the 1MHz clock.
>
> Do I have any options? Are there any other techniques I may apply to
> perform division and get a minimal clock skew between the two clocks?
>
> What would happen if I tried to use a CLKIN of 16MHz? No DLL lock?
>
> Thank you,
> -Geir Botterli
Article: 65872Most classes are given through distributers (Avnet, Insight etc) and are introductory level. You learn basic language constructs, how to create a project and compile, debug simple errors. The emphasis being on around the product being hawked. Oh yea, you get the business card of the teacher and FAE for any questions. I never saw many engineers get a whole hell of a lot from this in and of itself. I did take these courses, after I had learned the subject - my "boss" wanted everyone in our group to take them. I learned more from books and working with others in my group. There are lots of good books and resources on the internet. [Some] University courses are good as well. They tend to concentrate on the language set - many courses offer an EDA appendix' to the course as well - unfortuantely most schools can't afford the Mentor or Synopsis platforms. Check this out. "Jakub Dudek" <jaouque@yahoo.com> wrote in message news:c0889o$2mj$1@home.itg.ti.com... > Hi, > > Has anyone here taken VHDL training classes from Xilinx? > http://www.xilinx.com/support/training/abstracts/adv-vhdl.htm > > Are they any good?/worth the money? > > Any review/feedback on those classes would be appreciated > > Jakub > >Article: 65873
Steve wrote: > Austin Lesea <austin@xilinx.com> wrote in message news:<c00e21$77m1@cliff.xsj.xilinx.com>... > >>Steve, >> >>Quite frankly, I am amazed at how folks think about this. You have >>obviously never thought about that computer on your desk, and how it can >>be sold for $499! > > > > I don't know about the US PC prices, but in the UK you can make your > own PC for not that much more than you buy a new ready-built PC from a > shop. Compare that to Xilinx where small quantities are a few hundred > percent more expensive than in large quantities. > Oh really? You can layout the motherboard, buy all of the components, fab the motherboard, get all the eproms programmed, etc etc etc. Sure. AustinArticle: 65874
Hi there, I use Quartus II v3.0 to work on my Altera designs and I have a problem. Recently I reorganized my hardrive and moved some folder locations... My old projects open fine from new locations and all components are found correctly when I double-click in the schematics window. When I try to locate the component in the messages window (by double clicking on the error line) the program cannot locate my files, telling me that file does not exists. This file truly does not exists because it is looked for in the *old* locations, somehow preserved in the project file... Is there a way to fix the project files without redo all my projects? I do not want the program to look in the old locations on my non-existing e: drive. I moved everything to bigger c: drive but it does not work! I have changed the location for my "User Libraries" in Settings, but it did not help... Any other ideas?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z