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"John_H" <johnhandwork@mail.com> wrote in message <dcyUb.24$uo1.18709@news-west.eli.net> : Hi, John, thanks for your reply. >Use a single clock for the FPGA. >Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth (or >4*n-th) edge. I'm afraid I don't get how I should use clock enables to achieve this. The only "solution" i have come up with is like this: always @ (posedge clk_4MHz) clk_2MHz <= ~clk_2MHz; always @ (posedge clk_2MHz) clk_1MHz <= ~clk_1MHz; +BUFGs But this will result in a skew between the edges of the 4 and 1 MHz clocks. I could run the 4 MHz clock through some logic to delay it, but I don't like that option very much. Could you give an example on how to do this with clock enables? >One simple clock. >No DLL. >All flops synchronous with no skew. >Apply the multi-cycle constraint through the enables to get your timing at 4 >MHz or 1 MHz. >A thing of beauty. Sounds wonderful :) Regards, -Geir BotterliArticle: 65826
Hi, we tried to reconfigure a VirtexII using the Xilinx Multimedia Demoboard. The configuration can be done using CF-Card and System-ACE (bye the way, how do you pronounce ACE, A-C-E ? ) or via JTAG. The MPU port of the System-ACE is connected to the Virtex device. We want to initiate a reconfiguration from the FPGA itself. In order to do that, we send a byte to the CONTROLREG register of the System-ACE using the MPU port. In this way we set the FORCECFGMODE bit and the CFGSTART bit to 1 at the same time. Unfortunately the reconfiguration doesn't start. Any ideas? Thanks JoergArticle: 65827
Austin Lesea <austin@xilinx.com> wrote in message news:<c00e21$77m1@cliff.xsj.xilinx.com>... > Steve, > > Quite frankly, I am amazed at how folks think about this. You have > obviously never thought about that computer on your desk, and how it can > be sold for $499! I don't know about the US PC prices, but in the UK you can make your own PC for not that much more than you buy a new ready-built PC from a shop. Compare that to Xilinx where small quantities are a few hundred percent more expensive than in large quantities. > Or even your car, just go price the parts > individually some time. It's called mass production. I thought someone who works at Xilinx would have heard of mass production? > Steve wrote: > > > Austin Lesea <austin@xilinx.com> wrote in message news:<bvu1ml$7s71@cliff.xsj.xilinx.com>... > > > >>Steve, > >> > >>As for older parts, they do not get any less expensive to make. So the > >>price drops until the yields are stable, and then stops dropping. > >>Happens to everyone. At some point, they get more expensive to make as > >>their quantities go down, and the fab line equipment gets more expensive > >>to run (obsolete processes). > > > > > > > > So why are the prices *identical* to the cent, at different suppliers, > > in different countries, 4 years apart? > > They use the "manufacturer's suggested retail price." As mentioned, > these were very old parts, and the pricing was now stable. You use the example of car prices above, and it's interesting to note that in the UK some of the big car companies were found guilty of price-fixing because they were applying pressure to their dealerships to sell at the price the car manufacturer wanted them to sell at, and if the dealership disobeyed the manufacturer then they faced losing the ability to sell their cars. This sounds awfully similar to the Xilinx pricing policy... > > When we did accounts at uni we were taught that the larger the batch > > size the cheaper the product is because you spread the manufacturing > > setup charges across more units, but Xilinx aren't going to do a batch > > size of 100 for an order or 100 units. > > You learned the right stuff. Still applies. If a disti orders 100 > parts (and they do) we have to process just that many parts for that one > order. Disti's don't want to stock anything anymore, so that makes > costs go. Take the other end of the scale; what about your highest volume chips? Unless your production managers are extremely bad at planning then you're never going to do make 100 parts when that part sells X million per annum. But all your, say, Spartan IIE chips seem to follow a nice monotonically increasing price vs size graph for a single package type. Why? Because there seems to be very few distributors, so there's little competition, and no true competition if Xilinx order the distributors to sell the products at set prices. > Imagine Xilinx' dilemma: what do we build? and when do we build it? > If we have an order for 100K parts spread out over a year, everything is > trivial, and less costly. But if we have seemingly random orders > popping in all of the time, we have to build ahead (risk) and sometimes > scrap parts that are not moving. Yes, but the fastest selling chips are still expensive in small quantities. > If you have any optimism about your business at all, it would be best to > enter into a agreement and let the disti (and us) know where you think > you are going, and how many you will need. What about companies that are starting off? It just seems that if you're a big company that can place vast orders then you're alright; if you're small then you're not interested. > Distribution costs can't be > > much either because it only costs ~$9 to get a book sent to teh UK > > from amazon.com. The cost of wages for sales people is a fixed cost > > anyway, and the cost of the silicon itself is a variable cost which is > > independent of the batch size if you take the manufacturing setup > > costs separately. > > We can't seem to convince disti's to work for free, however, so they > charge what they feel they need to in order to make a profit. Do they though? Or do Xilinx have a say in the prices? > Disti's > also have 200+ FAEs of their own on their payrolls to support their > products, as well as order entry systems, stocking(?), unsold inventory, > stocking losses, uncollectable accounts (deadbeats), etc. > > As for the book business, I was an author, and if an author gets 1 cent > on their book, they are lucky. Ruthless business, with all of the money > going to the publisher and retailers. Like perfume, or music CDs, cost > of book: $3, price of book $75...... the $9 shipping is a complete > rip-off, they already made their profit, now they are icing their cake. Books are a good example of mass production though because bestsellers sell at £5 or less, whereas slow selling books like niche engineering books sell at very high prices. You don't see this kind of thing with Xilinx's prices though because despite some of your fastest selling chips selling hundreds or thousands of times faster than your slower selling chips the price vs size curve of the chips is monotonic. > > So why are your small quantity prices so inflated? > > > > Because they are a fair representation of the costs associated with > small numbers of parts ordered through distribution to allow for a > profitable business by the distis and reps. Compare that with bestselling books, which are cheap wherever you go, from the biggest to the smallest booksellers. This seems to be the biggest problem, because there seems to be so few places that you can buy Xilinx parts from in small quantities that they can effectively charge whatever they want. And from some of the posts to this and the other thread it seems that the distributors aren't interested at all in small quantities, so they price them at levels that discourage people to buy in small quantities. You have to wonder whether Xilinx limits the number of suppliers in order to keep prices artificially high? > They also represent the > unwillingness of a customer to enter into a contract which would allow a > scheduled delivery of parts over the long term, which is where the real > savings start to kick in. When do the "real savings start to kick in"? When you order 50,000 per annum? How can start-up companies do this? -- SteveArticle: 65828
Rene Tschaggelar <none@none.net> wrote in message news:<402405f0$0$714$5402220f@news.sunrise.ch>... > > I can understand that attitude for people buying ten thousand chips; > > but where do you expect people to get the experience with FPGAs that > > they have with microprocessors, when state-of-the-art FPGAs are two > > orders of magnitude more expensive and an order of magnitude less > > convenient to acquire? > > The cost is at the FPGA representative, distributing the stuff. > They get the questions asked. Xilinx have a revenue of $1.2bn according to this: http://finance.yahoo.com/q/is?s=xlnx Are you seriously trying to say that the cost of an FPGA representative being asked questions has anything other than a negligible effect on the prices of FPGAs? > > But, again, why doesn't the same argument apply to CPUs, for which > > there are half a dozen distributors in most towns, fairly happily > > distributing the things for a couple of percent profit margin. > > You say it. There are half a dozend shop selling cpus per town. > You go there, get a cpu, no questions asked, no questions answered. > They wouldn't be able to answer anyway. You don't expect such shops to be able to answer your questions, but the problem is that there just aren't any shops that you can buy FPGAs from. > There may be one FPGA representaive per state. And you ask a lot of > questions. Not because you're more stupid than a cpu buyer, but > because placing a cpu and applying an FPGA are completely different. See above. -- SteveArticle: 65829
Here is an example of how to use "clock enables". The example uses one of the count states as the "emable" Variable a will be updated every 4th 4Mhz clock (at a 1Mhz interval). always @ (posedge 4Mhz) begin cnt[1:0] <= cnt[1:0] + 1; if (cnt == 3) a <= b; else a <= b; end "Geir Botterli" <geirb@fokk.org> wrote in message news:16o920li0tfoia1qq0hpm4bbl9sj6krha1@4ax.com... > "John_H" <johnhandwork@mail.com> wrote in message > <dcyUb.24$uo1.18709@news-west.eli.net> : > > Hi, John, thanks for your reply. > > >Use a single clock for the FPGA. > >Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth (or > >4*n-th) edge. > > I'm afraid I don't get how I should use clock enables to achieve this. > The only "solution" i have come up with is like this: > > always @ (posedge clk_4MHz) > clk_2MHz <= ~clk_2MHz; > > always @ (posedge clk_2MHz) > clk_1MHz <= ~clk_1MHz; > > +BUFGs > > But this will result in a skew between the edges of the 4 and 1 MHz > clocks. > > I could run the 4 MHz clock through some logic to delay it, but I > don't like that option very much. > > Could you give an example on how to do this with clock enables? > > >One simple clock. > >No DLL. > >All flops synchronous with no skew. > >Apply the multi-cycle constraint through the enables to get your timing at 4 > >MHz or 1 MHz. > >A thing of beauty. > > Sounds wonderful :) > > Regards, > -Geir Botterli > >Article: 65830
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qhvfmjde2i.fsf@ruckus.brouhaha.com>... > Austin wrote: > > Quite frankly, I am amazed at how folks think about this. You have > > obviously never thought about that computer on your desk, and how it can > > be sold for $499! Or even your car, just go price the parts > > individually some time. > > Thomas Womack <twomack@chiark.greenend.org.uk> writes: > > I've often priced the parts for building a computer, and they add up > > to something within 15% of the price of buying the computer from Dell. > > You may have priced the subassemblies such as the motherboard, CD-ROM > drive, etc. Try pricing the actual components (chips, passives, etc.) in > small quantity. You'll be lucky if you can get a total BOM cost less > than five times Dell's price. The total BOM cost in small quantities is irrelevant because you can buy motherboards from as little as £40 (~$60) in the shops. The issue is that if you buy Xilinx parts in large quantities then you're alright, if you don't buy in large quantities then you have to put up with high unit prices so those that want to buy high volume chips in small quantities don't benefit from the economies of scale for these parts. -- SteveArticle: 65831
Steve wrote: > Rene Tschaggelar <none@none.net> wrote in message news: > <402405f0$0$714$5402220f@news.sunrise.ch>... > >>>I can understand that attitude for people buying ten thousand chips; >>>but where do you expect people to get the experience with FPGAs that >>>they have with microprocessors, when state-of-the-art FPGAs are two >>>orders of magnitude more expensive and an order of magnitude less >>>convenient to acquire? >> >>The cost is at the FPGA representative, distributing the stuff. >>They get the questions asked. > > Xilinx have a revenue of $1.2bn according to this: > > http://finance.yahoo.com/q/is?s=xlnx > > Are you seriously trying to say that the cost of an FPGA > representative being asked questions has anything other than a > negligible effect on the prices of FPGAs? I buy my FPGAs through a distributor. Not Altera direct. Somehow it took me longer to grasp certain ideas. I was talking on the phone with a FAE several times for half an hour or so. This FAE is likely getting a bit more than $5.95/hour. And this service somehow has to be paid. The fewer chips a customer purchases the more expensive he is, assuming the setup-cost per customer to be constant. So obviously the lower the chip count the higher the prices. ReneArticle: 65832
"Subroto Datta" <sdatta@altera.com> wrote in message news:<jIsUb.19024$ZW5.17022@newssvr16.news.prodigy.com>... > Ted, > If you can do send me the two archives of the design. The one which > compiles in the 7-8 minute range and the other one which has the addiitonal > logic added, and causes increased compilation time. We would like to analyze > the design. > Thanks for the offer and for the interest. I found that when I deleted all the files except the source ones, compilation time went down to 4 minutes. I shall keep copies of all precompilations, and if I see the problem again, I shall send the query as a service request in the Altera website. ThanksArticle: 65833
damn typo ... that should be "else a <= a" "Mike Lewis" <someone@microsoft.com> wrote in message news:8oadnQrloLlHarndRVn-sA@magma.ca... > Here is an example of how to use "clock enables". > > The example uses one of the count states as the "emable" > Variable a will be updated every 4th 4Mhz clock (at a 1Mhz > interval). > > always @ (posedge 4Mhz) > begin > cnt[1:0] <= cnt[1:0] + 1; > > if (cnt == 3) a <= b; > else a <= b; > end > > "Geir Botterli" <geirb@fokk.org> wrote in message > news:16o920li0tfoia1qq0hpm4bbl9sj6krha1@4ax.com... > > "John_H" <johnhandwork@mail.com> wrote in message > > <dcyUb.24$uo1.18709@news-west.eli.net> : > > > > Hi, John, thanks for your reply. > > > > >Use a single clock for the FPGA. > > >Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth > (or > > >4*n-th) edge. > > > > I'm afraid I don't get how I should use clock enables to achieve this. > > The only "solution" i have come up with is like this: > > > > always @ (posedge clk_4MHz) > > clk_2MHz <= ~clk_2MHz; > > > > always @ (posedge clk_2MHz) > > clk_1MHz <= ~clk_1MHz; > > > > +BUFGs > > > > But this will result in a skew between the edges of the 4 and 1 MHz > > clocks. > > > > I could run the 4 MHz clock through some logic to delay it, but I > > don't like that option very much. > > > > Could you give an example on how to do this with clock enables? > > > > >One simple clock. > > >No DLL. > > >All flops synchronous with no skew. > > >Apply the multi-cycle constraint through the enables to get your timing > at 4 > > >MHz or 1 MHz. > > >A thing of beauty. > > > > Sounds wonderful :) > > > > Regards, > > -Geir Botterli > > > > > >Article: 65834
Hi, I was just wondering if anyone has experienced problems with the installation of the xilinx webpack on windows 98SE? I get the installation started but at the end it reports that virtex support files are being un-installed.And if you do try to use MAP or PAR they report missing virtex personality modules. Thanks Jez -- Using M2, Opera's revolutionary e-mail client: http://www.opera.com/m2/Article: 65835
Windows versions prior to 2000 are not supported. From http://www.xilinx.com/ise/products/webpack_faq.htm "What platforms support ISE WebPACK? "ISE WebPACK is based on the main ISE Foundation software. It supports the same Windows based platforms as ISE Foundation. For the 6.1 release the supported platforms are: Windows XP, Windows 2000 w/SP2 (Chinese, Korean, US, Japanese). At the current time ISE WebPACK is not supported under Linux." Jez Smith wrote: > > Hi, > I was just wondering if anyone has experienced problems with the > installation of the xilinx webpack on windows 98SE? > I get the installation started but at the end it reports that virtex > support files are being un-installed.And if you do try to use MAP or PAR > they report missing virtex personality modules. > Thanks > JezArticle: 65836
Andy Peters wrote:
> It's great if you have
> a relationship with a distributor, but once they find out that you
> only want to build a handful of prototypes or whatever, they're not
> interested. There has to be a way for the small garage shop guys to
> get parts.
try this: http://www.arrow.com/
(o) Part Description
enter "acex" in the box
click (Search)
On page two there are qty=1 parts for under $20 you can order Online.
Ground shipping is $8
I have never used acex or online ordering,
but it looks like a viable option not requiring
any relationship with a distributor.
-- Mike Treseler
Article: 65837Steve wrote: > > Austin Lesea <austin@xilinx.com> wrote in message news:<bvu1ml$7s71@cliff.xsj.xilinx.com>... > > Steve, > > > > As for older parts, they do not get any less expensive to make. So the > > price drops until the yields are stable, and then stops dropping. > > Happens to everyone. At some point, they get more expensive to make as > > their quantities go down, and the fab line equipment gets more expensive > > to run (obsolete processes). > > So why are the prices *identical* to the cent, at different suppliers, > in different countries, 4 years apart? > > > That is also why we then go to a new and less expensive technology as > > soon as we can! If we can make an FPGA for less, our business increases > > as the number of applications that can afford FPGAs increases. > > > > As for why things cost less in quantity, that is Econ 101 (for non majors). > > I must have missed Econ 101, so could you explain why there's such an > enormous difference in price between the following?: > > From: > > http://www.ebnonline.com/showArticle.jhtml?articleID=4400089&_loopback=1 > > XC2S400E & XC2S600E for $27 and $45, respectively, in 250,000-unit > quantities, end 2002, and from: > > http://www.plis.ru/price.html?ID=124 > > the cheapest you can get them for is $55.45 and $170.00 respectively, > for <100 units. > > When we did accounts at uni we were taught that the larger the batch > size the cheaper the product is because you spread the manufacturing > setup charges across more units, but Xilinx aren't going to do a batch > size of 100 for an order or 100 units. Distribution costs can't be > much either because it only costs ~$9 to get a book sent to teh UK > from amazon.com. The cost of wages for sales people is a fixed cost > anyway, and the cost of the silicon itself is a variable cost which is > independent of the batch size if you take the manufacturing setup > costs separately. > > So why are your small quantity prices so inflated? Perhaps you should take an econ class, all kidding aside. I had a very brief one in high school and the most basic concept (next to guns vs. butter) is that of fixed costs vs. marginal costs. Even though they don't *make* the parts in 100 unit lots, there are fixed costs associated with selling them in 100 unit lots. This mainly has to do with support, I would expect. But there is also the issue of motivation. If you are running a company that has customers buying literally millions of parts a year and customers buying 100's of parts a year, are you going to give the small customer anywhere near the same prices as the big customer? No, you are going to shave every possible penny on the price you must to keep the big customer from buying the competitor's parts. The 100 unit customer is not even a consideration. Besides, if you are buying only 100 of a part, is it a big issue if you pay 2x for the part? If you are building a product, you are likely selling the product for 3, 5 or even 10x your parts cost. Otherwise you will be losing a little on each one you sell, and will be out of business soon. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 65838
Rene Tschaggelar wrote: > > Thomas Womack wrote: > > In article <c00e21$77m1@cliff.xsj.xilinx.com>, > > Austin Lesea <austin@xilinx.com> wrote: > > > >>Steve, > >> > >>Quite frankly, I am amazed at how folks think about this. You have > >>obviously never thought about that computer on your desk, and how it can > >>be sold for $499! Or even your car, just go price the parts > >>individually some time. > > > > > > I've often priced the parts for building a computer, and they add up > > to something within 15% of the price of buying the computer from Dell. > > Moreover, the price for Intel CPUs in the shop is the same to within > > about 15% as the price stated for thousand-unit quantities in their > > press releases. > > > > I believe FPGAs are comparably complicated to Intel CPUs, and I don't > > think there's as much as an order of magnitude difference in production > > quantity. > > > > Is the market volatility for FPGAs that much greater? > > An Intel cpu doesn't cost 4.70$ on whatever quantity. > And the margin on intel cpus is sufficient on all levels. That is not the relevant point. FPGAs (which mostly cost much more than $4.70) have a very different business model which requires significant costs for each customer of the product. Support on FPGAs is very high. There is also the cost of tool development which is nearly zero for the CPU and very high recurring cost for FPGAs. > >>If you have any optimism about your business at all, it would be > >>best to enter into a agreement and let the disti (and us) know where > >>you think you are going, and how many you will need. > > > > > > I can understand that attitude for people buying ten thousand chips; > > but where do you expect people to get the experience with FPGAs that > > they have with microprocessors, when state-of-the-art FPGAs are two > > orders of magnitude more expensive and an order of magnitude less > > convenient to acquire? > > The cost is at the FPGA representative, distributing the stuff. > They get the questions asked. No, the distis only have as much markup as the maker allows. I have been though the quotation cycle and nothing gets done without Xilinx authorizing it. > >>Because they are a fair representation of the costs associated with > >>small numbers of parts ordered through distribution to allow for a > >>profitable business by the distis and reps. > > > > > > But, again, why doesn't the same argument apply to CPUs, for which > > there are half a dozen distributors in most towns, fairly happily > > distributing the things for a couple of percent profit margin. > > You say it. There are half a dozend shop selling cpus per town. > You go there, get a cpu, no questions asked, no questions answered. > They wouldn't be able to answer anyway. > > There may be one FPGA representaive per state. And you ask a lot of > questions. Not because you're more stupid than a cpu buyer, but > because placing a cpu and applying an FPGA are completely different. That part is true, but I think most of the expense is by the maker, the disti only has one support person for any given manufacturer. It is not that much of a cost burden for them. And they will very much limit the amount of support they give you if you are not a large customer. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 65839
Steve wrote: > > Rene Tschaggelar <none@none.net> wrote in message news:<402405f0$0$714$5402220f@news.sunrise.ch>... > > > > I can understand that attitude for people buying ten thousand chips; > > > but where do you expect people to get the experience with FPGAs that > > > they have with microprocessors, when state-of-the-art FPGAs are two > > > orders of magnitude more expensive and an order of magnitude less > > > convenient to acquire? > > > > The cost is at the FPGA representative, distributing the stuff. > > They get the questions asked. > > Xilinx have a revenue of $1.2bn according to this: > > http://finance.yahoo.com/q/is?s=xlnx > > Are you seriously trying to say that the cost of an FPGA > representative being asked questions has anything other than a > negligible effect on the prices of FPGAs? There are a large number of costs associated with a customer. Mainly it is in the support, but there is also the cost of the tools which must be spread over all customers. They learned a long time ago that it is better to make each customer pay equally for the tools and keep that cost out of the chip price as much as they can. Otherwise they favor the small customers over the large ones. It is the large customers that make money for them. > > > But, again, why doesn't the same argument apply to CPUs, for which > > > there are half a dozen distributors in most towns, fairly happily > > > distributing the things for a couple of percent profit margin. > > > > You say it. There are half a dozend shop selling cpus per town. > > You go there, get a cpu, no questions asked, no questions answered. > > They wouldn't be able to answer anyway. > > You don't expect such shops to be able to answer your questions, but > the problem is that there just aren't any shops that you can buy FPGAs > from. Maybe not brick and mortar, but you can buy FPGAs from Digikey which is not much different from any other online retailer. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 65840
On a sunny day (6 Feb 2004 22:12:21 -0800) it happened Bassman59a@yahoo.com (Andy Peters) wrote in <9a2c3a75.0402062212.527c53a0@posting.google.com>: > There has to be a way for the small garage shop guys to >get parts. I agree with an other poster that Xilinx needs to improve on this, and make a website where yiou can order any quantity of anything they make. That would bring prices down, as distributors are taken out of the chain. More and more companies sell directly via the internet. I do not see how this would reduce sales for Xilinx, unless all there sales are stocking the distributors.Article: 65841
"Mike Lewis" <someone@microsoft.com> wrote in message <LZWdndi5gp-qYrnd4p2dnA@magma.ca> : >damn typo ... that should be "else a <= a" > >"Mike Lewis" <someone@microsoft.com> wrote in message >news:8oadnQrloLlHarndRVn-sA@magma.ca... >> Here is an example of how to use "clock enables". >> >> The example uses one of the count states as the "emable" >> Variable a will be updated every 4th 4Mhz clock (at a 1Mhz >> interval). >> >> always @ (posedge 4Mhz) >> begin >> cnt[1:0] <= cnt[1:0] + 1; >> >> if (cnt == 3) a <= b; >> else a <= b; >> end Thanks, but wouldn't this approach also create a couple of gate delays worth of skew between the clocks? -GeirArticle: 65842
Rick Collins wrote: > Rene Tschaggelar wrote: > >>>>Because they are a fair representation of the costs associated with >>>>small numbers of parts ordered through distribution to allow for a >>>>profitable business by the distis and reps. >>> >>> >>>But, again, why doesn't the same argument apply to CPUs, for which >>>there are half a dozen distributors in most towns, fairly happily >>>distributing the things for a couple of percent profit margin. >> >>You say it. There are half a dozend shop selling cpus per town. >>You go there, get a cpu, no questions asked, no questions answered. >>They wouldn't be able to answer anyway. >> >>There may be one FPGA representaive per state. And you ask a lot of >>questions. Not because you're more stupid than a cpu buyer, but >>because placing a cpu and applying an FPGA are completely different. > > > That part is true, but I think most of the expense is by the maker, the > disti only has one support person for any given manufacturer. It is not > that much of a cost burden for them. And they will very much limit the > amount of support they give you if you are not a large customer. > Unfortunately this as wrong, as you can get wrong. This may have been this way years ago and it proved wrong. The distributors realized that luckily. The business works a bit different. There are companies who want a new product and pay for the development. There are those who do a development and there are others who actually manufacture the parts. The first mentioned company sells the final products then. Now who needs the support, and who buys the most parts ? As developper, I seldom buy more than 10 pieces. But also I introduce the new technologies into many other companies, be they my costomers or may they become my customers. Meaning there is no sense in flooding those who buy the most parts with PR materials. The decisions are done long befoe they buy the parts. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 65843
I made a lot of changes:
- split IO_control in two modules : an io buffer (iobuf) and the
contoller (IO_Async)
- now it's totally asynchronous
- no more extra reg
- tried to split the big always in many little ones
but now it doesn't work neither with modelsim, post place & route sim
results aren't nice.
The problem seems to be somewhere between iobuf and IO_Async because
when i try to write an address in ADDR it never arrives ?
The funny thing is that both modules work fine alone..
here's the code:
------------------------------------------------------------------------------
module IO_Async(ALE,NWR,NRD,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,rst,ibuf,obuf);
input ALE;
input NWR;
input NRD;
input [7:0] MIN;
input [7:0] MAX;
input [7:0] ibuf;
output [7:0] obuf;
output [7:0] SEL;
output [7:0] TYPEFIL;
output [7:0] AMPLIF;
output [7:0] DIVFRQ;
output rst;
reg [7:0] ADDR;
reg [7:0] obuf;
reg [7:0] SEL;
reg [7:0] TYPEFIL;
reg [7:0] AMPLIF;
reg [7:0] DIVFRQ;
reg rst;
// ciclo scrittura ADDR
always @(posedge ALE)
ADDR <= ibuf;
//ciclo scrittura rst
always @(negedge NWR)
if (ADDR == 8'b0000_0000)rst <= (ibuf[0]);
else rst <= rst;
// ciclo scrittura SEL
always @(negedge NWR)
if (ADDR == 8'b0000_0001)SEL <= ibuf;
else SEL <= SEL;
// ciclo scrittura TYPEFIL
always @(negedge NWR)
if (ADDR == 8'b0000_0010)TYPEFIL <= ibuf;
else TYPEFIL <= TYPEFIL;
// ciclo scrittura AMPLIF
always @(negedge NWR)
if (ADDR == 8'b0000_0100)AMPLIF <= ibuf;
else AMPLIF <= AMPLIF;
// ciclo scrittura DIVFRQ
always @(negedge NWR)
if (ADDR == 8'b0000_1000)DIVFRQ <= ibuf;
else DIVFRQ <= DIVFRQ;
// ciclo letture
always @(negedge NRD)
if (ADDR == 8'b0000_0000)obuf <= {7'b0,rst};
else if (ADDR == 8'b0000_0001)obuf <= SEL;
else if (ADDR == 8'b0000_0010)obuf <= TYPEFIL;
else if (ADDR == 8'b0000_0100)obuf <= AMPLIF;
else if (ADDR == 8'b0000_1000)obuf <= DIVFRQ;
else if (ADDR == 8'b0001_0000)obuf <= MIN;
else if (ADDR == 8'b0010_0000)obuf <= MAX;
else obuf <= obuf;
endmodule
_______________________________________________________________________________
-------------------------------------------------------------------------------
module iobuff(da,obuf,ibuf,dir);
input dir;
inout [7:0] da;
input [7:0] obuf;
output [7:0] ibuf;
assign da = (dir) ? 8'bzzzz_zzzz : obuf;
assign ibuf = (dir) ? da : 8'bzzzz_zzzz;
endmodule
_______________________________________________________________________________
Article: 65844On Sat, 07 Feb 2004 09:36:09 -0500, Mike Lewis wrote: > Here is an example of how to use "clock enables". > > The example uses one of the count states as the "emable" > Variable a will be updated every 4th 4Mhz clock (at a 1Mhz > interval). > > always @ (posedge 4Mhz) > begin > cnt[1:0] <= cnt[1:0] + 1; > > if (cnt == 3) a <= b; > else a <= b; > end > You don't use an else for clock enables, here is cleaner version of the above. reg [1:0] cnt; reg ce; always@(posedge 4mhz) begin cnt <= cnt + 1; ce <= cnt == 2; if(ce) begin foo <= bar; end end There isn't any skew problem, the clock is always the 4Mhz clock. The ce controls a mux which either selects the new value or the current value, i.e. the above example is equivalent to the previous posters example. However the way that I wrote it is what synthesizers expect to see. Also all FPGAs, both Xilnx and Altera incorporate the clock enable logic into the flip flops so it's effectively free. As for DLLs, at 1MHz you don't need them. Also you won't have to worry about multi-cycle clock constraints, just put a constraint on the 4Mhz clock. 4Mhz is so slow that it's practically impossible to write any code that can't meet 4Mhz timing.Article: 65845
Is "MTI starter" ModelSim? in that case, isn't that coved in the testbench simulation section? JeanArticle: 65846
Added in http://www.fpga4fun.com/simulation.htmlArticle: 65847
Tim wrote: > Austin Lesea wrote: > > >>We can't seem to convince disti's to work for free > > > So why don't you sell off your web pages for people > who don't want FAE support and the rest? The price curves are all political/Marketing decisions. Sometimes IC makers promote ICs through disti's at (say) the 10K price for ALL lower volumes. Why ? - It's a great marketing ramp tool, and gets their device onto designers radar. For those design-ins that hit 10K, it has real benefit, and for the others that did not, what did it REALLY cost them ? - In silicon terms very little, and maybe a couple of lunches for the Distis to convince them this will actually seed sales, and maybe some coverage/support payments. Another sales-seed path is web sales. Microchip do this very well - Xilix could learn there... Now, all that activity occurs mainly in devices looking to push growth. I've seen it with Motorola and their newest FLASH uC, and also IIRC with the Coolrunner made by - oh yes, Xilinx. Now, of course they CAN do the same with FPGA's, but as they don't NEED to, until Altera does, not much will change.... -jgArticle: 65848
Jesse Kempa wrote: > Jim Granville <no.spam@designtools.co.nz> wrote in message news:<14XTb.20607$ws.2742532@news02.tsnz.net>... > >> One thing that was not obvious in a quick trawl thru their info, >>was the relative NIOS sizes (Stratix / Stratix II). >> You'd think that would make a good benchmark, but maybe it's still a >>'work in progress' as they tune the SW. >> >> Anyone seen actual numbers or NIOS or NIOS II ? >> >>-jg > > > Jim, > > Nios v3.2 is the final release of "classic" Nios. It is slated to be > released very soon, and will offer a couple of tweaks for Stratix II > support. For another data point: I ran the "minimal_32" example > through QII 4.0 for both device families and got 2011LEs (Stratix) vs. > 1393ALUTs (Stratix II). > > Again, Nios 3.2 will officially support Stratix II. > > As for Nios II... I cannot comment on that yet, but stay tuned, its > worth waiting for. Jesse, Thanks for that. We would expect NIOS II to be more 'tuned' for Stratix II... Here's a question, (for when you can comment :) Will NIOS II have a variant that fits/runs on MAX II devices ? -jgArticle: 65849
Jim Granville wrote: > Tim wrote: >> Austin Lesea wrote: >> >> >>> We can't seem to convince disti's to work for free >> >> >> So why don't you sell off your web pages for people >> who don't want FAE support and the rest? > > The price curves are all political/Marketing decisions. > > Sometimes IC makers promote ICs through disti's at (say) the 10K > price for ALL lower volumes. Sometimes I feel that X would get a better result by using distributors whose primary business was distributing computer cases or bananas or other low-tech stuff. Ego-free distribution. And the low-tech/web/... distribution should sell only the fastest speed grade, cutting the parts count by two or three.
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