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Austin Franklin a écrit : > If the PCI Ethernet card supports master, then you probably can do > what you want with your PCI interface supporting target only. I'm afraid this won't be enough. An Ethernet card is not supposed to be a system controller: it will need to be configured at startup (the PCI Configuration Space needs to be written in order to activate the target and the master functionnalities) and only a PCI master can issue configuration cycles. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.IPricot.com/Article: 26426
Yeah ... mine works if I don't use the Quartus fitter ... but unfortunately my design won't fit without it. I got it working briefly a few days ago ... I think by messing with unused inputs ... then it stopped again ... this time I've got it working again by removing an lpm_compare and replacing it with (a<b) in verilog ... so far so hoopy! Gary Leonid Shvarzberg wrote: > I also had some weird system error during the compiles of 10K30, something > to do with > "fitme.C". Forgot the details, but I was able to get rid of this error by > removing Quartus compile options in MaxPlus. > Good Luck. > LS > > Gary Cook <gary_cook@ntlworld.com> wrote in message > news:39DCFE2C.82E5AF94@ntlworld.com... > > Running Maxplus 9.64 and am having problems getting > > internal errors during fitting ... sometimes during > > partitioner and even 1% through netlist compiler. It's > > not consistant at all ... I can run fine for a while and > > then bang! all of a sudden I can't compile a thing. > > Altera support aren't much help and the web-site mentions > > a similar error but doesn't give much help either ... > > just wondering if anyone here's got any info that could > > help... > > > > not sure if it's an os thing ... running it on nt and get no > > problems, running on win98 and get problems ... ??? > > > > Cheers, > > > > Gary Cook. > >Article: 26427
Hi, My question is about safely generating an asynchronous pulse to reset a single D latch in a Spartan FPGA, (and I know this is frowned upon, with good reasons). More specifically, I need to duplicate the main function offered with the discrete 74F552 chip : http://www-us6.semiconductors.com/acrobat/datasheets/74F552_2.pdf This chip is a bidirectional registered transceiver with "Data Ready" flag and parity. It's all very easy, except for the OEBR & OEAS input that clear the flag on it's rising edge by internally generating a short asynchronous reset pulse for the flag latch. The "ugly" trick they show in the schematic (bottom of page 5) diagram is a NAND gate whose 2 inputs are driven by both a true and a (heavily loaded) inverted signal, thus creating the transient condition during the time between when the uninverted input goes high and when the inverted input goes low (propagation delay in the inverter). Such a trick would obviously not work with a Spartan FPGA that would directly create a nand gate with both an inverting and not inverting input (if optimisation does not simply eliminte it and reduce the NAND's output to a constant "1" value). So I tried to figure out another way, and here's the schematic drawing of the trick I thought to solve the problem : http://www3.sympatico.ca/erv/pulse.gif - OBUF is in slew rate limited mode, - ILD is "with delay" (most important part) - UPAD is preferably used, but unused IOPAD can be used for that purpose, if there are no UPAD in the selected package. The reason I think this should work is in the published timing for the Spartan serie, namely : - [CLB Latch] Set/reset direct Width (high) (T rpw) XCS05-3 : Minimum 4 ns XCS05-4 : Minimum 3 ns - Delay adder for input with delay option XCS05-3 : Minimum 4 ns XCS05-4 : Minimum 3.6 ns (XCS10 and up have higher (thus better) values) Other delays in the loop (even if a lower bound delay is not part of the specs) include: - Slew rate limited OBUF delay - PAD capacitance (even for UPAD) - Input buffer - Delay element - ILD D to Q delay - FDC CLR input High to Q low delay According to the published timing, even if all the propagation + routing delays are 0, the minimum pulse (-4 grade) should be 3.6 ns, and the maximum length with TTL input levels selected should be 7.2 (O to pad)+3.6 (Delay element, no max value specified)+2.8 (pad to I1,I2 via ILD)+ 3 (CLR to Q (T rio)) = 16.6 ns ---------------------------------------------------------------------------- What do you think about it ? is it safe or did I miss something ? Is there a better way to do it (when no high speed clock is availiable) ? Do you have experience (good or bad) with such design ? Can it be trusted both in the lab and *in real applications* ? Thanks for your help.Article: 26428
Hi, My question is about safely generating an asynchronous pulse to reset a single D latch in a Spartan FPGA, (and I know this is frowned upon, with good reasons). More specifically, I need to duplicate the main function offered with the discrete 74F552 chip : http://www-us6.semiconductors.com/acrobat/datasheets/74F552_2.pdf This chip is a bidirectional registered transceiver with "Data Ready" flag and parity. It's all very easy, except for the OEBR & OEAS input that clear the flag on it's rising edge by internally generating a short asynchronous reset pulse for the flag latch. The "ugly" trick they show in the schematic (bottom of page 5) diagram is a NAND gate whose 2 inputs are driven by both a true and a (heavily loaded) inverted signal, thus creating the transient condition during the time between when the uninverted input goes high and when the inverted input goes low (propagation delay in the inverter). Such a trick would obviously not work with a Spartan FPGA that would directly create a nand gate with both an inverting and not inverting input (if optimisation does not simply eliminte it and reduce the NAND's output to a constant "1" value). So I tried to figure out another way, and here's the schematic drawing of the trick I thought to solve the problem : http://www3.sympatico.ca/erv/pulse.gif - OBUF is in slew rate limited mode, - ILD is "with delay" (most important part) - UPAD is preferably used, but unused IOPAD can be used for that purpose, if there are no UPAD in the selected package. The reason I think this should work is in the published timing for the Spartan serie, namely : - [CLB Latch] Set/reset direct Width (high) (T rpw) XCS05-3 : Minimum 4 ns XCS05-4 : Minimum 3 ns - Delay adder for input with delay option XCS05-3 : Minimum 4 ns XCS05-4 : Minimum 3.6 ns (XCS10 and up have higher (thus better) values) Other delays in the loop (even if a lower bound delay is not part of the specs) include: - Slew rate limited OBUF delay - PAD capacitance (even for UPAD) - Input buffer - Delay element - ILD D to Q delay - FDC CLR input High to Q low delay According to the published timing, even if all the propagation + routing delays are 0, the minimum pulse (-4 grade) should be 3.6 ns, and the maximum length with TTL input levels selected should be 7.2 (O to pad)+3.6 (Delay element, no max value specified)+2.8 (pad to I1,I2 via ILD)+ 3 (CLR to Q (T rio)) = 16.6 ns ---------------------------------------------------------------------------- What do you think about it ? is it safe or did I miss something ? Is there a better way to do it (when no high speed clock is availiable) ? Do you have experience (good or bad) with such design ? Can it be trusted both in the lab and *in real applications* ? Thanks for your help.Article: 26429
Hi I use a XC9536 CPLD device. I want to change this device to an low power cpld -fpga device for a batterie cricute. I don't want this low power device to use prom like XC9536. Where do I find an device to fitt my problem? Thankful for help Björn Lindegren Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26430
Hey, Rick. Do you mind forwarding me the graph you got from Austin, if you can? Thanks, Kent.Article: 26431
Hi Guys/Girls I'm at the beginning of yet another Xilinx design. Just about to use the Virtex-E, but then, no 5V tolerance (I need to be driving more current than the 100R series resistor will allow). I have decided to use the Spartan-II part. The question: From the data sheets I have for the XCV50E and the XC2S50 (both in FG256 package), I can see that the pin-out is 99% the same (Virtex has a temp sensor diode). Have I got completely the wrong data sheets, because Xilinx told me that Spartan-II and Virtex-E were different families and that the pin-outs would not be the same!? Thanks for any info. Graeme Keith R. Williams <krw@attglobal.net> wrote in message news:pLMYl5dhX7hK-pn2-ZCy9Mdkk5t4o@localhost... > On Fri, 13 Oct 2000 16:53:39, jean-francois hasson > <jfhasson@club-internet.fr> wrote: > > > Hi, > > > > I am working on a design involving an FPGA which could be either a > > Xilinx or an Altera. I know Altera is about to propose a 5V compatible > > APEX without any glue outside and I was wondering if Xilinx has a > > similar part in the Virtex family. > > Virtex (and I suppose Spartan-II ?) is 5V tollerant. However, it > won't drive 5V CMOS reliably without help on the up level. Any > version of TTL (or HCT) is fine though. > > Virtex-E is *not* 5V tollerant. Ooops! It's a good thing I had > time to put in a quick-switch on the one 5V CMOS input before I > turned the board for the Virtex-E spin. ;-) > > ---- > Keith > >Article: 26432
Try the Low Power Coolrunner CPLDs from Xilinx ... Larry e97bjli@thn.htu.se a écrit : > Hi > > I use a XC9536 CPLD device. I want to change this device to an low power > cpld -fpga device for a batterie cricute. > > I don't want this low power device to use prom like XC9536. > > Where do I find an device to fitt my problem? > > Thankful for help > > Björn Lindegren > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 26433
Put each clock in a separate process. The synthesis will have trouble with multiple clocks within one process. "James S." wrote: > > Hi, > > I'm having trouble using this clk'event in VHDL. I'm using it for a rising > edge condition, i.e. > > if (clk'event and clk='1') then ... etc. > > In my code, I have several different clocks, i.e. > > if (clk1'event and clk1='1') then ... etc. > if (clk2'event and clk2='1') then ... etc. > if (clk3'event and clk3='1') then ... etc. > > and so on. The syntax checks OK, but when I synthesize, I get this error: > > Error: This use of clock edge specification not supported > > It synthesizes fine with less than 3 'events statments like those, but any > more and I get the error. Is this a device limit? Is there a way around > it? > > I'm using Xilinx Foundation 3.1i software and coding for an XC95108 CPLD. > > Thanks for any help, > James -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26434
Hi Everybody, My parallel jtag programmer has suddenly decided to give me problems. For some unknown reason it suddenly desided that there was a syntax error in my BSDL files. > Loading Boundary-Scan Description Language (BSDL) file > 'D:/Xilinx_CPLD/data/xc18v02_pc44.bsd'.....ERROR:JTag - Illegal character ? > (/37777777637) at line 473 in BSDL description.% > ERROR:JTag - Error of type 'Improper Entity declaration' encountered while > parsing BSDL file at or near '3, 0, Z),'. > ERROR:JTag - Error of type 'Check if source file is BSDL' encountered while > parsing BSDL file at or near '3, 0, Z),'. > terminated due to errors. It has been working fine for weeks, suddenly after a recompile it decided not to play along any longer. I found a "Answer" on xilinx support page where they state: > This error occurs sporadically, and seems to happen when 2.1i and 3.1i software > is run on Windows platforms. And under the solution they write: > This error message is currently under investigation. Sporadic error under windows - where have we heard that one before ? Anyway, has anyone out there had the same problem and found a work-around ? I would appreciate a hint.Article: 26435
Nope, they are indeed the same with the exception that spartan replaces the temp diode with a power down function. The main difference is the limited selection of packages...spartan only comes in the cheap packages, which means you'll probably want to use the FG256 package to get pin compatibility. Also, be aware there are differences in the speedfiles. Grumps wrote: > > Hi Guys/Girls > > I'm at the beginning of yet another Xilinx design. Just about to use the > Virtex-E, but then, no 5V tolerance (I need to be driving more current than > the 100R series resistor will allow). I have decided to use the Spartan-II > part. > > The question: > From the data sheets I have for the XCV50E and the XC2S50 (both in FG256 > package), I can see that the pin-out is 99% the same (Virtex has a temp > sensor diode). Have I got completely the wrong data sheets, because Xilinx > told me that Spartan-II and Virtex-E were different families and that the > pin-outs would not be the same!? > > Thanks for any info. > > Graeme > > Keith R. Williams <krw@attglobal.net> wrote in message > news:pLMYl5dhX7hK-pn2-ZCy9Mdkk5t4o@localhost... > > On Fri, 13 Oct 2000 16:53:39, jean-francois hasson > > <jfhasson@club-internet.fr> wrote: > > > > > Hi, > > > > > > I am working on a design involving an FPGA which could be either a > > > Xilinx or an Altera. I know Altera is about to propose a 5V compatible > > > APEX without any glue outside and I was wondering if Xilinx has a > > > similar part in the Virtex family. > > > > Virtex (and I suppose Spartan-II ?) is 5V tollerant. However, it > > won't drive 5V CMOS reliably without help on the up level. Any > > version of TTL (or HCT) is fine though. > > > > Virtex-E is *not* 5V tollerant. Ooops! It's a good thing I had > > time to put in a quick-switch on the one 5V CMOS input before I > > turned the board for the Virtex-E spin. ;-) > > > > ---- > > Keith > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26436
Hi, Grumps. "Grumps" <grumps@here.com> writes: > The question: > From the data sheets I have for the XCV50E and the XC2S50 (both in FG256 > package), I can see that the pin-out is 99% the same (Virtex has a temp > sensor diode). Have I got completely the wrong data sheets, because Xilinx > told me that Spartan-II and Virtex-E were different families and that the > pin-outs would not be the same!? You missed the biggest difference, I beleive. The Virtex-E family has a core voltage of 1.8v, while the Spartan-II has 2.5v. That will be one big difference. Other than that, the Virtex Families and the Spartan-II Families do have the exact same pin-out, save for the Temp pins or the STATUS & PWRDOWN pins on the Spartan-II. Hope this helps. -KentArticle: 26437
If you didn't have to update the coefficients, you could just use the Coregen. HOwever, to update the coefficients with that incarnation, you need to do partial reconfiguration, which means knowing where the LUTs are as well as knowing how the LUT pins got assigned so that you can order the partial products correctly...a PITA at best. A better method, IMHO is to replace the LUTs with SRL16E shift register elements. For very little additional logic, you can reload the luts by shifting new data in. The SRL16E uses the LUT as a 16 bit shift register. THe output is selected from one of the 16 bits using the input address, so when it is not shifting, the function is just like a LUT. For the structure of the multiplier, look at my website for the section on multipliers. In particular, you'll want to look at the KCMs. BTW, the KCM does not stand for constant coefficient multiplier as many believe, it stands for Ken Chapman multiplier. Ken was the one who introduced them to the Xilinx library. Lars wrote: > > Hi everybody! > > In my design I have to implement a couple of 8x8 bit multipier. One coefficient is constant. > Since I have to change this constant coefficient in runtime (partial reconfig. of the Virtex chip) the easiest way would be a implementation just with LUTs (so I know the exact location of the LUTs and can change them). Has somebody an idea how I can handle this?? > > Thank you! > > Lars -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26438
For the NCO, use a phase accumulator so that the frequency can be adjusted. The phase accumulator output is essentially a sawtooth which you need to convert to a sinewave. The conversion can be done in a number of ways, the best of which depends on your particular requirements for phase resolution, magnitude accuracy, sample rate, available real estate, and resources available. In FPGAs, anything less than 5-6 bits phase resolution is generally best handled by a look up table an logic to take advnatage of symmetry. Over 9 bits of phase resolution is generally best handled by an on-the-fly computation using a CORDIC rotator. The in-between resolutions depend on what you have available. There are a few slides on waveform generation in the Designcon "Modulation and Demodulation for FPGAs" presentation available on my website. andrew_f66@my-deja.com wrote: > > I'm a final year undergraduate doing a project on implementing a PWM > circuit on a Xilinx FPGA for driving an induction motor. Somehow I need > to be able to generate a digital sine wave to compare with a triangular > carrier wave to generate the PWM. Someone suggested programming an > EEPROM with a look-up table of Sine values, but this doesn't seem a > very flexible way of doing it. > > Can anyone help, with a reference or anything else? Any suggestions on > any other part of the project? > > Thanks, > > Andrew F. > Bristol Uni. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26439
You can either assign a location (or relative location--RLOC) inside the source, in a constraints file or with the grpahical floorplanner. THe constraints file and floorplanner are not hierarchical, so they only assign LOCs, which are absolute placements. Evan Shattuck has some info on his website regarding putting RLOCs in your VHDL for exemplar. RLOCs can only be placed on instantiated primitives, so you'll have to use instantiation. If you are specifying LUTs, that is easy: attribute RLOC:string; attribute RLOC of my_lut: label is "R0C1.S0"; begin my_lut:LUT port map( ... you'll also need an INIT attribute on the LUT to describe the logic. If instead you want to specify the logic in the LUT as an equation, then you'll need to create component with just the logic for that LUT. In synplicity, put the xc_map attribute on the component, which is essentially like the old FMAPs, but is not passed through. For example: --FMAP'd or2 library IEEE; use IEEE.std_logic_1164.all; entity fmap_or2 is port ( a, b : in std_logic; z : out std_logic); end fmap_or2; architecture rtl of fmap_or2 is attribute xc_map : STRING; attribute xc_map of rtl : architecture is "fmap"; begin z <= a or b; end rtl; ---------------------------------------------------------------------------------------- THen in your next level up: attribute RLOC:string; attribute RLOC of my_lut: label is "R0C1.S0"; begin my_lut:fmap_or2 port map( ... Lars wrote: > > Hi folks! > > I want to assign my LUTs to certain CLBs in the Virtex chip in my VHDL code, e.g. LUT1 to CLBR1C3.S0. > How can I do that? > > Thank you in advance!!! > > Lars -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26440
giuseppe ha scritto nel messaggio <8s7anh$lr4$1@fe2.cs.interbusiness.it>... :Does anyone know a source of an 8 pins DIP 17512 5V serial EEPROM - PROM?. : : What do you mean with "a source of" ?Article: 26441
Thanks Ray & Kent. It'll be the XC2S50FG256 then. I know about the core voltage issues, but thanks for the reminder. Grumps <grumps@here.com> wrote in message news:8servj$jce$1@supernews.com... > Hi Guys/Girls > > I'm at the beginning of yet another Xilinx design. Just about to use the > Virtex-E, but then, no 5V tolerance (I need to be driving more current than > the 100R series resistor will allow). I have decided to use the Spartan-II > part. > > The question: > From the data sheets I have for the XCV50E and the XC2S50 (both in FG256 > package), I can see that the pin-out is 99% the same (Virtex has a temp > sensor diode). Have I got completely the wrong data sheets, because Xilinx > told me that Spartan-II and Virtex-E were different families and that the > pin-outs would not be the same!? > > Thanks for any info. > > Graeme > > Keith R. Williams <krw@attglobal.net> wrote in message > news:pLMYl5dhX7hK-pn2-ZCy9Mdkk5t4o@localhost... > > On Fri, 13 Oct 2000 16:53:39, jean-francois hasson > > <jfhasson@club-internet.fr> wrote: > > > > > Hi, > > > > > > I am working on a design involving an FPGA which could be either a > > > Xilinx or an Altera. I know Altera is about to propose a 5V compatible > > > APEX without any glue outside and I was wondering if Xilinx has a > > > similar part in the Virtex family. > > > > Virtex (and I suppose Spartan-II ?) is 5V tollerant. However, it > > won't drive 5V CMOS reliably without help on the up level. Any > > version of TTL (or HCT) is fine though. > > > > Virtex-E is *not* 5V tollerant. Ooops! It's a good thing I had > > time to put in a quick-switch on the one 5V CMOS input before I > > turned the board for the Virtex-E spin. ;-) > > > > ---- > > Keith > > > > > >Article: 26442
I would rather that you asked Austin directly for it. I don't want to possibly ruffle any feathers. I actually don't think the graph is very clear and it could easily be misinterpreted. Perhaps Austin has one that is labeled a little more clearly. Kent Orthner wrote: > > Hey, Rick. > > Do you mind forwarding me the graph you got from Austin, if you can? > > Thanks, > Kent. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26443
This will likely work. But it all depends on how you are using the part. This circuit depends as much (or more) on how you will be using it as it does on the internal construction of the circuit. So beware of async resets, even it they work the way they are intended! Eric Montreal wrote: > > Hi, > > My question is about safely generating an asynchronous pulse to reset > a single D latch in a Spartan FPGA, (and I know this is frowned upon, > with good reasons). > > More specifically, I need to duplicate the main function offered with > the discrete 74F552 chip : > http://www-us6.semiconductors.com/acrobat/datasheets/74F552_2.pdf > > This chip is a bidirectional registered transceiver with "Data Ready" > flag and parity. > > It's all very easy, except for the OEBR & OEAS input that clear the flag on > it's rising edge by internally generating a short asynchronous reset pulse > for the flag latch. > > The "ugly" trick they show in the schematic (bottom of page 5) diagram is a NAND > gate whose 2 inputs are driven by both a true and a (heavily loaded) inverted > signal, thus creating the transient condition during the time between when the > uninverted input goes high and when the inverted input goes low (propagation > delay in the inverter). > > Such a trick would obviously not work with a Spartan FPGA that would directly > create a nand gate with both an inverting and not inverting input (if optimisation > does not simply eliminte it and reduce the NAND's output to a constant "1" value). > > So I tried to figure out another way, and here's the schematic drawing of the trick > I thought to solve the problem : > http://www3.sympatico.ca/erv/pulse.gif > > - OBUF is in slew rate limited mode, > - ILD is "with delay" (most important part) > - UPAD is preferably used, but unused IOPAD can be used for that purpose, if there > are no UPAD in the selected package. > > The reason I think this should work is in the published timing for the Spartan > serie, namely : > > - [CLB Latch] Set/reset direct Width (high) (T rpw) > XCS05-3 : Minimum 4 ns > XCS05-4 : Minimum 3 ns > > - Delay adder for input with delay option > XCS05-3 : Minimum 4 ns > XCS05-4 : Minimum 3.6 ns > (XCS10 and up have higher (thus better) values) > > Other delays in the loop (even if a lower bound delay is not part of the specs) include: > - Slew rate limited OBUF delay > - PAD capacitance (even for UPAD) > - Input buffer > - Delay element > - ILD D to Q delay > - FDC CLR input High to Q low delay > > According to the published timing, even if all the propagation + routing delays > are 0, the minimum pulse (-4 grade) should be 3.6 ns, and the maximum length > with TTL input levels selected should be 7.2 (O to pad)+3.6 (Delay element, no > max value specified)+2.8 (pad to I1,I2 via ILD)+ 3 (CLR to Q (T rio)) = 16.6 ns > > ---------------------------------------------------------------------------- > > What do you think about it ? is it safe or did I miss something ? > > Is there a better way to do it (when no high speed clock is availiable) ? > > Do you have experience (good or bad) with such design ? > > Can it be trusted both in the lab and *in real applications* ? > > Thanks for your help. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26444
Hi,
how would you implement an ordered list with
i) 8bit-integers as elements
ii) operations a)append, b)delete element i and c) foreach i { ... }
in an Fpga (XC4000) ?
Foreach list a maximal length is given.
Any idea ?
Something like a shift register ?
Thanks a lot
ciao
J=F6rg
Article: 26445"S. Ramirez" wrote: > > Then try using VHDL to program your 22V10s! Simon, The 16V8 was overkill! I just needed to gate a couple of signals. Turns out the 16V8 was cheaper and took up less board space than the equivalent discrete parts. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26446
Neil Franklin wrote: > Since > then I instinctively believe Assimov, that any sufficiently advanced > technology is indistinguishable from magic. Wasn't it Arthur C. Clarke who said that? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26447
Right you are. I missed the 'E' after the 'XCV50'. The SpartanII has the same core voltage as the straight Virtex, which is 2.5v. Virtex E is 1.8v and not 5v tolerant on the I/O Kent Orthner wrote: > > Hi, Grumps. > > "Grumps" <grumps@here.com> writes: > > The question: > > From the data sheets I have for the XCV50E and the XC2S50 (both in FG256 > > package), I can see that the pin-out is 99% the same (Virtex has a temp > > sensor diode). Have I got completely the wrong data sheets, because Xilinx > > told me that Spartan-II and Virtex-E were different families and that the > > pin-outs would not be the same!? > > You missed the biggest difference, I beleive. The Virtex-E family has a core voltage > of 1.8v, while the Spartan-II has 2.5v. That will be one big difference. > > Other than that, the Virtex Families and the Spartan-II Families do have the > exact same pin-out, save for the Temp pins or the STATUS & PWRDOWN pins on the > Spartan-II. > > Hope this helps. > > -Kent -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26448
Tom St Denis wrote: > > Would a paper on a block cipher geared towards low end microcontrollers > be suited for this conference? > Probably, but the number of papers accepted is very small. Unless you're working for a professor or corporation that's part of the "in" group, you might as well not waste your effort. I'm missing a lot of conferences this year 'cause I can't afford the trip to Europe. At least the people on the other side of the pond are finally getting a lower cost conference! Patience, persistence, truth, Dr. mikeArticle: 26449
In article <39EB352F.CC9D154F@physiology.wisc.edu>, Mike Rosing <rosing@physiology.wisc.edu> wrote: > Tom St Denis wrote: > > > > Would a paper on a block cipher geared towards low end microcontrollers > > be suited for this conference? > > > > Probably, but the number of papers accepted is very small. Unless you're > working for a professor or corporation that's part of the "in" group, you > might as well not waste your effort. I'm missing a lot of conferences > this year 'cause I can't afford the trip to Europe. At least the people > on the other side of the pond are finally getting a lower cost conference! Well I want to submit my paper on TC8, I have a hardware design team (some really nice people from opencores.org), I have a embedded software design team (myself and a friend) and I am writting the technical paper. The TC8 *draft* paper (http://www.geocities.com/tomstdenis/tc8_draft.zip) is available. It's one of my "better" papers as I tried to include more background and technical information. I am working on the cryptanalysis right now, I found a related key theoretical attack and I have to work out the probability of it working... Tom Sent via Deja.com http://www.deja.com/ Before you buy.
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