Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi
I am working with and ACTEL 54sx series device and I'd like to make a
traditional xor gate clock doubler. I am using the Viewlogic schematic
capture tool.
------- ---
---| Delay |--------| |
| ------- |xor|-------------
clk -----------------------| |
---
What i'm looking for is an attribute setting that will prevent the
logic compiler from optimizing away a series connected gate string...
Thanks in advance
John Parker
Article: 38026john wrote: >Hi, a better circuit ( more reliable ) is the one I published in the Xilinx data book many years ago: Feed clk into XOR gate. XOR output clocks a flipflop. Q is inverted and feeds its own D (typical toggle design). Inverted Q also feeds second input of the aforementioned XOR. XOR output is double-frequency clock. This circuit is reliable ( the pulse must first toggle the flip-flop! ) and should survive any over-eager simplification attempts by the synthesizer... Peter Alfke ( on vacation near Seattle ) ============================================ > Hi > > I am working with and ACTEL 54sx series device and I'd like to make a > traditional xor gate clock doubler. I am using the Viewlogic schematic > capture tool. > > ------- --- > ---| Delay |--------| | > | ------- |xor|------------- > clk -----------------------| | > --- > > What i'm looking for is an attribute setting that will prevent the > logic compiler from optimizing away a series connected gate string... > > Thanks in advance > > John ParkerArticle: 38027
I am implementing Forward according IEEE802.3 It works Basic and Tag mode.When there is a packet from MAC,i need Forward it according to DA By Checking Hash Table .Can anyone adivse me about verilog source code reference to implement it?Article: 38028
I am novice in asic design . Can anybody recommend where to begin ?
I have solid background in digital design , FPGAs and synopsys dc_shell ...
What I would like is to know more about following issues :
1) How asic design is different from FPGA ?
2) Design flow ?
3) Which tools other than synthesis tools are used in asic design ?
Which are the most common ones ???
3) Analog issues in asic design .
4) Packaging and how it can affect digital design ???
5) Clocks in asic , DLLs , PLLs .
5) Number of iterations in modern asic design ????
6) Physical synthesis , is it usefull ???
7) IBM 0.18 micron libraries ....
If anybody can give pointers onto up-to-date books , websites it will be
great ...!!
I am interested in all this information from the point of view of digital
designer ....
Thank you ...
Article: 38029Hi All, WISH YOU ALL HAPPY NEW YEAR. Can Anybody please provide me the information on the availability of different Virtex-II FPGA chips.(inculding approx cost of the chip). Thanks and Regards - satyaArticle: 38030
gajju <gsr_1976@yahoo.com> wrote: > I am using synplicity for synthesizing my code and targetting the edif > to xilinx par. In par i am giving area constraint to for hierarchical > design. > INST "U1/U2/U3" AREA_GROUP=g0; > AREA_GROUP g0 ..... > I have found that some of my hierarchical block nets are not > synthesized with name U1/U2/U3 etc. Instead they are named as G_900.. > Bcas of this par tool is not able to place them in specified area. > These nets are some combo logic which has been synthesized and given > some interim name by synplicity. Is there any way i can tell > synplicity tool to prepand all of them with hierarchy name?? I found that using syn_hier=hard on the hierarchical blocks helps to keep all of the logic named properly. Of course it has other effects too (especially on optimization and fanout control) which you may not like. This is a fairly annoying Synplify problem.. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38031
I would suggest you go to Xilinx's Web site and find a local rep to call directly. Prices for Xilinx parts can vary widely. If you call a rep you can work out a good price even on low quantities. They can also tell you what's shipping and when. If you just want to see published prices, try out www.partminer.com. They will list many Xilinx parts, just keep in mind that you can get better pricing if you develop a relationship with the local rep. Colin Cook Cook Technologies Embedded System Design Services. satya <satya@iwavesystems.net> wrote in message news:82741d43.0201010115.6515f3f2@posting.google.com... > Hi All, > WISH YOU ALL HAPPY NEW YEAR. > Can Anybody please provide me the information on the availability of > different Virtex-II FPGA chips.(inculding approx cost of the chip). > > Thanks and Regards > - satyaArticle: 38032
i am learning verilog Language,and i want refer some good style verilog sample.where is it?Article: 38033
HI, WISH U A VERY HAPPY NEW YEAR. I WANTED TO KNOW THE DIFFERENCES BETWEEN COOLRUNNER CPLD , XC4000 ,VIRTEX AND SPARTAN FPGA WITH RESPECT TO THE ARCHITECTURE. DIVYAArticle: 38034
HI, I WANT TO KNOW WHERE I CAN GET INFORMATION ON HOW TO DO FLOORPLANNING IF POSSIBLE WITH EXAMPLES. DIVYAArticle: 38035
Hi i want some information on xilinx floorplanning .i will be glad if u could get me some information on this renjini.kArticle: 38036
hi, i am searching for a link, book, university lessons explaining the architecture of asic and fpga and their differences. thanks, matthiasArticle: 38037
Hi Viktor, It available now and has been since October. www.xilinx.com/microblaze G=F6ran Bilski Victor Schutte wrote: > Yesterday I got my small NIOS board functional. When I started out I wa= nted > to achieve a few things: > -Replace my 8051 (big board,large RAM/ROM) designs. > -Have something that can be upgraded. > -Have some useable tools. > > I am not trying to plug an ad. for Altera but I am impressed. My entire= PCB > is 120mm by 90mm, 32 bit NIOS, 64 I/Os, 6 serial ports (if I simplify t= he > UARTs), RTC , 256K RAM, 1Meg FLASH. I can configure from a single EPC1 = or 2 > or from flash, although I think the EPC1 is eventually cheaper/cost > effective and safer (if you consider that you might wipe your CPU desig= n > configuration from flash). You still need to apply external power and > MAX232. > > I wrote a small program to test memory copy to a port (at clk=3D20MHz).= At > this speed, with a serializer, I will be able to transmit about 73megab= its > per second. This small PCB is magnitudes faster than the 8051 (at whate= ver > speed you can buy .e.g. Dallas has produced a 50MIPS device). If Altera= > discontinues the 20K100 (device that I am using at the moment) I can ea= sily > migrate to other packages(The drawback is that you can only use it with= > Altera devices (legally)). The tools are easy to use and free (GNU C/C+= +). > Plus, looking at NIOS ver2 more features can be packed into the FPGA. > Plus,plus... you don't need a killer heatsink and fan, everything runs > pretty cool. > > Cost and effort wise it might not be an option for many people to devel= op > your own PCB. The development kit is $995. The components are hard to f= ind > in small quantities and believe me it takes a bit more effort to get it= > going than a simple 8051 design. I think Altera can supply more of the = kit's > populated PCBs but these cost about $600 to $700 (correct me if I am wr= ong). > > Now a plug for my business. I am using NIOS for my access control syste= ms > and vehicle management systems. I am also situated in South Africa and = for > those who watch the money markets you will notice that the South Africa= Rand > is about 11 to 1 to the US dollar, which means we are dirt cheap. I can= > supply small quantity populated PCBs, tested with all the software you = need > for less than $300. I am also planning an ACEX1k100 NIOS which in large= > quantities will be lots cheaper. My PCB is not production ready yet bu= t > email me (zerksus@mweb.co.za) is you have any questions. > > Question: Does anybody know if MicroBlaze is a reality or not. For the = last > year I have been reading specs of how much better and cheaper it is tha= n > NIOS but nobody wants to sell anything to me. I always get responses th= at it > will be available later this year (Ray, any response ?) > > Victor > Zerksus Engineering > > "Stuart Moses" <mostuus@yahoo.com> wrote in message > news:99d0603.0112271625.5b56fdd1@posting.google.com... > > The biggest criteria is performance. What performance do you need? > > A soft-core processor implemented in programmable logic will be slowe= r > > than a hard-core processor. There are several soft-cores available o= n > > the market, some of these are synthesizable Verilog and VHDL verions > > of 6502, 8051, etc. or architecture-specific soft-cores such as > > Altera's Nios. If you are replacing a 68000 micro in you system, a > > Nios will have more horsepower than you would need. > > > > Hard-Core processors in FPGAs include Altera's ARM9 implementation > > (@200MHz) and Triscend's ARM7 (@50MHz.) In this case, the Altera and= > > Triscend implementations have hard-wired processor bus interfaces, > > guaranteeing fast external memory bus speeds & allowing the processor= > > to power-up and operate before the FPGA is configured (this allows th= e > > processor to configure the device.) Xilinx had announced something i= n > > a hard-core processor, but I don't believe they're shipping these > > parts. > > > > Another important criteria is the S/W development tools and OS suppor= t > > (if you require an OS.) Make certain that there are compilers and > > debug tools available. On an ARM or MIPs, OS and tools support will > > not be a problem at all. The Nios includes S/W tools and a debugger > > and has two RTOSes and a Linux port. > > > > Hope this helps.Article: 38038
Carl, I agree that proper careful placement will outdo the tool any day. I would say that the gap gets narrower all of the time. I would also suggest that lately the gap is narrow enough that most customers do not go in and tweak their designs, other than to find a problem. The FPGA editor is not the real view of the chip (obviously). I do agree that it is all you need to construct a really high performance working design (we use it all of the time to verify features functions and specifications). Austin Carl Brannen wrote: > Austin, with regard to "A really good engineer who knows the structure may > (only may) get a better > result. That is because the engineer does not really know the structure. A > good example is the FPGA editor view which is a simplistic representation of > the chip -- not at all how it is really implemented. The synthesis tools > now know all of the tricks and truly know the structures, and their costs." > > I disagree. > > (1) The tools have very little idea what the silicon is capable of. > (2) The FPGA editor provides an engineer full knowledge of what the silicon > is capable of. The delays are there, as are all the bits that can be > manipulated. If the synthesis tools can make it, it is observable with FPGA > Editor. > (3) If you want some examples, I'll publish my arithmetic templates. They > allow all kinds of stuff to be put in a slice that the tools simply can't do. > > Maybe someday the tools will be able to match a "really good engineer", but it > hasn't happened yet. Even if the tools had full knowledge of what can be put > into a Virtex slice, they don't know how to do a global optimization for > the design. > > Carl > > -- > Posted from firewall.terabeam.com [216.137.15.2] > via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 38039
divya wrote: > HI, > WISH U A VERY HAPPY NEW YEAR. > I WANTED TO KNOW THE DIFFERENCES BETWEEN COOLRUNNER CPLD , XC4000 > ,VIRTEX AND SPARTAN FPGA WITH RESPECT TO THE ARCHITECTURE. > DIVYA RTFDS. Go to: http://www.xilinx.com/ and read. --=aArticle: 38040
Austin Lesea wrote: > > The FPGA editor is not the real view of the chip (obviously). I do agree that it > is all you need to construct a really high performance working design (we use it > all of the time to verify features functions and specifications). > > Austin > Austin, If that's so - and I agree - then why isn't FPGA Editor part of the WebPACK tool set ? One thing you missed out - AFAIK FPGA Editor is the only way of constructing hard marcos ?Article: 38041
Dear Kevin, We are glad that our suggestions helped you to improve your design. Your assumptions are generally correct and you are on the right way to solve your problem. To your questions regarding our PCI core. - we are using our own PCI development board containing XCV100PQ208 - 4 the reason for -4 part was the budget restriction (it was university project ...) - it is also true that -4 Virtex FPGA was ordered for different purpose than PCI Core development. It is also a reason we have to deal with slower part. - we are using MG FPGA Advantage flow - Leonardo Spectrum for synthesis. - the result is PCI Core capable of Target/Initiator mode (most challenging is the Initiator Burst Write implementation) That is all I can reveal. Best regards Milos BecvarArticle: 38042
Orlls <sf@ikre.oiret> wrote in message news:<ee73fd4.-1@WebX.sUN8CHnE>... > i am learning verilog Language,and i want refer some good style verilog sample.where is it? Try the projects section of http://www.opencores.orgArticle: 38043
Thanks all. I can't believe I was so brain damaged that I needed to ask that. Ah well. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 38044
The difference is simple. Development time and cost. Look up the various FPGA manufacturers, altera, xilinx, and so on, they explain that in detail. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com Matthias Weber wrote: > > hi, > > i am searching for a link, book, university lessons explaining the architecture of asic and fpga and their differences. > > thanks, > > matthiasArticle: 38045
Hello all, I have coded a standard 32 bit counter in VHDL for a project, this counter is used to count 100MHz clock pulses within a certain time interval. I have simulated it and it works beautifully, now I have gone through the synthesis, etc and targeted the design (of which this counter is a small part) to a Spartan II XC2S100 FPGA. The tools report that the maximum frequency is about 67 MHz. Does this mean that this counter will not work correctly, if so how do I implement a faster counter in VHDL, the VHDL code doesn't specify speed or how to make a counter faster. I'm assuming the 67MHz reported is the maximum speed of the entire circuit, and since this part is a very small part and the rest operates at much lower frequencies that this may not be a problem but I'm unsure. I am fairly new to Xilinx products and VHDL. Do I need to get into floorplanning, etc to enable the counter to be able to accurately count these pulses? Any help would be greatly appreciated. Thanks Jason BerringerArticle: 38046
Dear All,
I have a problem or question about the timing report on the Xilinx
ISE 4.1.
In my design, I used synplify pro for synthesis and design manager of
Xilinx ISE 4.1 for implemenation. In the design, I built a clock
generator which uses 2 DCMs to generator 3 different clock signals
for the operation. The details are
Primary input : 50MHz clock signal
DCM0 input : primary 50MHz clock signal
output : use 2X output to get the 100MHz output
DCM1 input : 2X output of the DCM0 (100MHz)
output : use 2X_180 output (200MHz) to get a 180-degree
shifted 200MHz output(named as clk_4x)
Within the design, it is supposed the the timing constraint for
the logic using the clk_4x should be 5ns. However, from the
timing report it showed a strange result. It shows that the
requirement is 2.5ns rather than the 5ns, and the timing of
the rising edge of the clk_4x signal is very strange too.
Do anyone have idea about this problem? Thanks in advance.
Regards,
Kenneth
--------------------------------------------------------------------------------
Slack: -6.541ns (requirement - (data path - negative
clock skew))
Source: SYN/fs_syn_5ns_case_2_4
Destination: SYN/clk_change_buf[0]
Requirement: -2.500ns
Data Path Delay: 4.029ns (Levels of Logic = 2)
Negative Clock Skew: -0.012ns
Source Clock: clk_4x rising at 7.500ns
Destination Clock: clk_4x rising at 10.000ns
Data Path: SYN/fs_syn_5ns_case_2_4 to SYN/clk_change_buf[0]
Location Delay type Delay(ns) Physical Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
SLICE_X27Y34.YQ Tcko 0.568
SYN/fs_syn_5ns_case_2_4
SYN/fs_syn_5ns_case_2_4
SLICE_X34Y8.CE net (fanout=9) 3.221
SYN/fs_syn_5ns_case_2_4
SLICE_X34Y8.CLK Tceck 0.240
SYN/clk_change_buf[1]
SYN/clk_change_buf[0]
-------------------------------------------------
---------------------------
Total 4.029ns (0.808ns logic,
3.221ns route)
(20.1% logic,
79.9% route)
Article: 38047"Jason Berringer" <jberringer@trace-logic.com> wrote in message news:x4QY7.34453$AS4.2680281@news20.bellglobal.com... > Hello all, > > I have coded a standard 32 bit counter in VHDL for a project, this counter > is used to count 100MHz clock pulses within a certain time interval. I have > simulated it and it works beautifully, now I have gone through the > synthesis, etc and targeted the design (of which this counter is a small > part) to a Spartan II XC2S100 FPGA. The tools report that the maximum > frequency is about 67 MHz. Does this mean that this counter will not work > correctly, if so how do I implement a faster counter in VHDL, the VHDL code > doesn't specify speed or how to make a counter faster. I'm assuming the > 67MHz reported is the maximum speed of the entire circuit, and since this > part is a very small part and the rest operates at much lower frequencies > that this may not be a problem but I'm unsure. I am fairly new to Xilinx > products and VHDL. Do I need to get into floorplanning, etc to enable the > counter to be able to accurately count these pulses? > > Any help would be greatly appreciated. > > Thanks > > Jason Berringer Jason, Why don't you post your code so that we can all take a look at it. It will help us diagnose your problem. Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 38048
Jason Berringer wrote: > The tools report that the maximum > frequency is about 67 MHz. Does this mean that this counter will not work > correctly, Some tools (like the Altera MAX Plus) can provide a list of "critical paths" and the blocks/processes involved. I am not sure if Xilinx also provides such a feature, but with this you could check whether your counter is affected or not. > if so how do I implement a faster counter in VHDL, the VHDL code > doesn't specify speed or how to make a counter faster. A 32-bit counter is quite long, so you should consider implementing it in severals stages as look-ahead counters. > I'm assuming the > 67MHz reported is the maximum speed of the entire circuit, and since this > part is a very small part and the rest operates at much lower frequencies > that this may not be a problem but I'm unsure. I had the same problem a couple of weeks ago, and it was the counter that slowed down the whole design. Breaking it up as described above really worked for me and doubled my maximum frequency - so give it a try! Happy New Year, Andreas If you need more information, don't hesitate to contact me by email, since I don't read the groups regularly, and might miss a reply from you.Article: 38049
What kind of cable can be used to pass multiple LVDS signals at 300MHZ from
one VIRTEX-E/SPARTAN2E chip to other?
Who manufactures appropriate cable?
Is it possible to use CAT6?
Is there something like flat cable for such purposes?
Thanks,
Alex Sherstuk
sherstuk@iname.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z