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Dear Sir or Madam, I want to perform a timing simulation for a static SRAM using MODELSIM 5.7e (Altera OEM). But things do go wrong. If you have some time please look at http://mitglied.lycos.de/vazquez78/ to see more details. I would appreciate any helpful hint. Kind regards André V. G&D System DevelopmentArticle: 67201
Mike Treseler wrote: > > Hal Murray wrote: > > > But that's only one of the screwup patterns. The other one is > > that it starts in state 0000... > > Is there any simple way out of that? (I can't see one.) > > I don't know a *simple* one. > The *stress-less* one is > binary encoding. Binary encoding does nothing to help this problem. If your FSM does not fully utilize all of possible encodings, not only can you make an invalid state transition, you can get into an unrecoverable state, just like the one-hot encoding. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67202
> You have no code between > > >if Reset= '1' then > > elsif Rising_Edge(Data_flag) then This "elsif" needs to be changed to an "if" This is an asyncronous reset, thats no good either.Article: 67203
Jim Granville wrote: > > Hal Murray wrote: > >> You can make 0000 a valid state, if it is important that > >>reset recovery delays are minimised. > >>(It is then not strictly one-hot any more...) > > > > > > I can make 0000 be a valid state with a couple of inverters > > before and after some FF and maybe using a reset rather than > > preset on the initial FF. > > > > But if you ignore complications like that, and think > > in terms of a "one" hot state machine that has only one > > bit on, there are two failure modes - 2 bits on and > > 0 bits on. > > > > The anync reset mess can easily make two bits on. They > > are adjacent to eachother, so it's easy to filter them > > out with only local logic. > > > > I'm looking for a similar neat/simple way to catch the > > no bits on case. Or a way to convince myself that it > > won't happen. > > Seems to be equally likely as 'double ones' ? > The effect that can cause the upstream Q to miss loading a '0', > ( so gives two 1's adjacent) > can equally load a '0', but have the downstream reg miss > 'passing on' the '1' ( so gives all 0's ) > > > > >>Gray code and twisted ring/johnson counters are also > >>usefull for state engines. > >> I think some SW allows you to specify what form the > >>underlying HW takes. > > > > > > But they give up the simple decoding which is usually > > the reason I'm using one-hot state machines. > > Agreed. > I don't think there is any 'silver bullet', but you can > design a state engine that has differing start and spin paths. > If it's built using D registers, then any illegal states will > likely trend to 0000H, even with minimal gating. > > Covering all illegal states in a One-hot is more a challenge > - I can see the potential to use more layers of logic doing this, > than decoding a Gray Code design. It is not that hard if you are willing to wait more than one clock cycle to get back into a valid state. To detect a one-hot illegal state you just need to count the FFs set to 1. If it is other than 1, then you have an illegal state. The counting circuit is just a bunch of adders followed by more adders until you get a single result. This result can be compared to the number ...0001, no match is an illegal state. Since this can be a deep circuit, it can be pipelined to run at whatever speed you need. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67204
http://biz.yahoo.com/prnews/040308/sfm094_1.html I wonder what this means for Triscend. Does this mean they will have funding for improving their product line? Or is this another assimilation by the BORG and these devices will go the same way as some others that were bought and are no longer available? Is supporting three hard CPUs by one FPGA company practical (8051, ARM, PPC)? Something tells me the 8051 will be the first to go... (nobody likes a 5 volt tolerant part ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67205
Hi - Here's a second vote for "what does hang mean?" Many of the questions posted in this group aren't too tough to answer; they're too *vague* to answer. For folks who may be posting questions for the first time, here's something you may want to look at: http://www.catb.org/~esr/faqs/smart-questions.html While the tone is a bit too snarky for my taste, the article makes some good points. Bob Perlman Cambrian Design Works On Mon, 8 Mar 2004 08:13:20 -0500, "Mike Lewis" <someone@microsoft.com> wrote: >Everybody else has provides ideas to check with regard to board level >hardware problems. What if the problem is a functional problem or a >timing problem in the fpga. You have two identical boards but the "stimulus" >could very well be different or the order of events could be different. > >One thing I really hate is when someone says ... I have a problem, >the thing "hangs". What does that mean? Maybe if you dig >deeper to find out why it "hangs" you can solve your problem. >What is happening when it "hangs"? What is it that "hangs"? >The thing that "hangs" ... what things could make it "hang"? > >Mike > >"Masoud Naderi" <naderimisc@yahoo.com> wrote in message >news:2ba3bbea.0403051417.5f36d35f@posting.google.com... >> Hi all, >> I have two boards with the exactly same fpga (spartanIIE) and same >> code inside them. One of the boards hangs 2~10 minute after power on. >> I want to find out the reason. Is it due to power problem on one of >> the boards? grouding or ...? >> please let me know your ideas. >> regards. >Article: 67206
Rick, Gee, I thought you would be happy that they would be saved at all, and now have access the the number 1 embedded CPU, the IBM PPC (based on latest shipments of V2 Pro and Pro X family). We are certainly delighted to have their expertise and knowledge in embedded processor solutions. To us, and our 200,000 seats of software, it seems almost insignificant if 10% have started to use the PPC. Pop that up to 40%, and you now have the largest group of PPC users on the planet. Exactly what parts are you referring to that are no longer available? Austin rickman wrote: > http://biz.yahoo.com/prnews/040308/sfm094_1.html > > I wonder what this means for Triscend. Does this mean they will have > funding for improving their product line? Or is this another > assimilation by the BORG and these devices will go the same way as some > others that were bought and are no longer available? > > Is supporting three hard CPUs by one FPGA company practical (8051, ARM, > PPC)? Something tells me the 8051 will be the first to go... (nobody > likes a 5 volt tolerant part ;) >Article: 67207
In article <404CA972.57DFE9A2@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >http://biz.yahoo.com/prnews/040308/sfm094_1.html > >I wonder what this means for Triscend. Does this mean they will have >funding for improving their product line? Or is this another >assimilation by the BORG and these devices will go the same way as some >others that were bought and are no longer available? I have a feeling it was a bit of a bidding war betweteen Xilinx and Altera, and that M&A in both companies wanted to buy Triscend, so somebody blinked and bought it, as much to keep any patents and other IP out of the hands of suehappy, third party lawyers. I doubt anything else will really carry forward. AFter all, what does an A7V really buy you over a V2 Pro 4? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 67208
Nick, Remember it was ARM that bid to buy Triscend. Just do a Google news lookup on Triscend....... Austin Nicholas C. Weaver wrote: > In article <404CA972.57DFE9A2@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >>http://biz.yahoo.com/prnews/040308/sfm094_1.html >> >>I wonder what this means for Triscend. Does this mean they will have >>funding for improving their product line? Or is this another >>assimilation by the BORG and these devices will go the same way as some >>others that were bought and are no longer available? > > > I have a feeling it was a bit of a bidding war betweteen Xilinx and > Altera, and that M&A in both companies wanted to buy Triscend, so > somebody blinked and bought it, as much to keep any patents and other > IP out of the hands of suehappy, third party lawyers. > > I doubt anything else will really carry forward. AFter all, what does > an A7V really buy you over a V2 Pro 4?Article: 67209
Gilbert, In the first part of the process, you are giving data_out register based semantics with Data_Flag being the clock: > if Reset= '1' then > elsif Rising_Edge(Data_flag) then > if We='1' then > case data_in(3 downto 0) is > when "1000" => > data_out <= "1111"; > when others=> > data_out <= "1111"; > end case; > end if; > end if; In the second part of the process, you are giving data_out latch based semantics with we=0 being the latch is enabled condition: > if We='0' then > case Addr(3 downto 0) is > when "0001" => > data_out <= "ZZZZ"; > when others => > data_out <= "1111"; > end case; > end if; What hardware are you trying to create? If data_out is a register clocked by data_flag, then perhaps you have an "end if;" out of place. If the end if that is associated with the rising edge of data_flag came at the end of the process, the synthesis tool would see data_out as a register. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ gilbert wrote: > Hi, > > i have wrote a VHDL code as below. > i use Xilinx foundation platform. > The situation is: > > syntax check --> Check Successful > Synthesis --> Error: HDL translation aborted. > (HDL-105) > > Is there anybody can help me ? > > The problem confuse me for long time. > > Thanks, Gilbert > > > > -- begin my code > library IEEE; > use IEEE.std_logic_1164.all; > entity Buff is > port ( > Data_in: in STD_LOGIC_VECTOR (3 downto 0 ); > Data_flag: in STD_LOGIC; > Reset: in STD_LOGIC; > Addr: in STD_LOGIC_VECTOR(7 downto 0); > We: in STD_LOGIC; > data_out: out STD_LOGIC_VECTOR(3 downto 0) > ); > end Buff; > > architecture Buff_arch of Buff is > begin > process (Data_flag ) > begin > if Reset= '1' then > elsif Rising_Edge(Data_flag) then > if We='1' then > case data_in(3 downto 0) is > when "1000" => > data_out <= "1111"; > when others=> > data_out <= "1111"; > end case; > end if; > end if; > if We='0' then > case Addr(3 downto 0) is > when "0001" => > data_out <= "ZZZZ"; > when others => > data_out <= "1111"; > end case; > end if; > > end process; > end Buff_arch; > > -- end my code >Article: 67210
"Magnus Danielson" <magda@netinsight.net> wrote in message news:404c4a28$1@fnewsa.telia.net... > Hi, > When bypassing both the 8B/10B and 64B/66B encoder and decoders, while > otherwise configuring the Rocket I/O similar to the 64B/66B setup (i.e. > use 64B/66B scrambler), where do my additional 2 data bits show up in RX > and TX direction. The 64B/66B encoder/decoder does not fit my needs, and > the 8B/10B is too much waste of the baudrate. I naturally assume that > the use of scrambler is sufficient for line-code properties and I view > the 64B/66B stuff as specific application encoding stuff which just > happends to not be usefull to me for my intended application. > PS. Yes, I have been reading the latest UG. > Cheers, Magnus The 8B/10B (or any other xB/yB) encoding is there so that you transmit an equal number of ones and zeros. This keeps the transceivers from saturating one way or the other. SteveArticle: 67211
Hello Ppl
I have actually already asked this question before but I need help again.
I'm using a Nios Development Board (50MHz Oscillator, FPGA = Cyclone
EP1C20F400C7). I'm using Quartus II v4.0 Build 190
I need to generate a clock speed of 12.5MHz. While I have my own vhdl code
that can do this, I can't use the ALTPLL to do this for me.
How can i do this? When I try to generate a speed of 12.5MHz using
MegaFunction Wizard in Quartus it complains ('Post divider max count
exceeded')
Does this mean there is a lower limit? Is there a way to achieve this speed
using ALTPLL and the above specs?
Thanks
Article: 67212rickman wrote: > http://biz.yahoo.com/prnews/040308/sfm094_1.html > > I wonder what this means for Triscend. Does this mean they will have > funding for improving their product line? Or is this another > assimilation by the BORG and these devices will go the same way as some > others that were bought and are no longer available? > > Is supporting three hard CPUs by one FPGA company practical (8051, ARM, > PPC)? Something tells me the 8051 will be the first to go... (nobody > likes a 5 volt tolerant part ;) Yep, 5V tolerant I/O would lead users to ask why OTHER Xilinx devices did not have it - clearly, it would have to go ;)Article: 67213
Nicholas C. Weaver wrote: > In article <404CA972.57DFE9A2@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >>http://biz.yahoo.com/prnews/040308/sfm094_1.html >> >>I wonder what this means for Triscend. Does this mean they will have >>funding for improving their product line? Or is this another >>assimilation by the BORG and these devices will go the same way as some >>others that were bought and are no longer available? > > > I have a feeling it was a bit of a bidding war betweteen Xilinx and > Altera, and that M&A in both companies wanted to buy Triscend, so > somebody blinked and bought it, as much to keep any patents and other > IP out of the hands of suehappy, third party lawyers. > > I doubt anything else will really carry forward. AFter all, what does > an A7V really buy you over a V2 Pro 4? Original offer was from ARM, which was interestimng in itself, as clearly they did not need to buy an ARM license ;) - and it also put them into conflict with their own customers, so what they REALLY wanted was the FPGA-adjacent-to-ARM IP, to on-sell. Likely Xilinx spotted that, and thought 'we can get 40 employees, and snuff a FPGA license stream, all with some loose change'... What (if anything) gets killed is more a question of foundry process flows. If they hit a snag like with Coolrunner, then some devices will go, but I think Triscend used a mainstream foundry so on-going prodn is quite low risk. Next generation development is another story entirely... -jgArticle: 67214
> john wrote: > >> Hi, >> >> Is somebody know how to increase the jitter in a PLL integrated in a >> FPGA ?? >> >> Thanks in advance... Now _there's_ a request you don't see often.... :)Article: 67215
Rather than a one hot machine, you might consider a shift register machine that
starts off with all zeros and shifts a 1 in for each state transition. The
terminal state(s) then apply reset to the whole shift register. Branches are a
little bit uglier, but it does provide recovery from an illegal state.
Hal Murray wrote:
> > You can make 0000 a valid state, if it is important that
> >reset recovery delays are minimised.
> >(It is then not strictly one-hot any more...)
>
> I can make 0000 be a valid state with a couple of inverters
> before and after some FF and maybe using a reset rather than
> preset on the initial FF.
>
> But if you ignore complications like that, and think
> in terms of a "one" hot state machine that has only one
> bit on, there are two failure modes - 2 bits on and
> 0 bits on.
>
> The anync reset mess can easily make two bits on. They
> are adjacent to eachother, so it's easy to filter them
> out with only local logic.
>
> I'm looking for a similar neat/simple way to catch the
> no bits on case. Or a way to convince myself that it
> won't happen.
>
> >Gray code and twisted ring/johnson counters are also
> >usefull for state engines.
> > I think some SW allows you to specify what form the
> >underlying HW takes.
>
> But they give up the simple decoding which is usually
> the reason I'm using one-hot state machines.
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67216rickman wrote: > Mike Treseler wrote: > >>Hal Murray wrote: >> >> >>>But that's only one of the screwup patterns. The other one is >>>that it starts in state 0000... >>>Is there any simple way out of that? (I can't see one.) >> >>I don't know a *simple* one. >>The *stress-less* one is >>binary encoding. > > > Binary encoding does nothing to help this problem. If your FSM does not > fully utilize all of possible encodings, not only can you make an > invalid state transition, you can get into an unrecoverable state, just > like the one-hot encoding. This depends on the low level HW. Toggle FF's can stick in illegal states, but D registers in binary state engines tend to illegal -> Zero. We often use that 'hidden' feature in state engine design. One-hot state engines are typically a primed shift register, so illegal state preservation is more of a problem. -jgArticle: 67217
"Nicholas C. Weaver" wrote: > > In article <404CA972.57DFE9A2@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >http://biz.yahoo.com/prnews/040308/sfm094_1.html > > > >I wonder what this means for Triscend. Does this mean they will have > >funding for improving their product line? Or is this another > >assimilation by the BORG and these devices will go the same way as some > >others that were bought and are no longer available? > > I have a feeling it was a bit of a bidding war betweteen Xilinx and > Altera, and that M&A in both companies wanted to buy Triscend, so > somebody blinked and bought it, as much to keep any patents and other > IP out of the hands of suehappy, third party lawyers. > > I doubt anything else will really carry forward. AFter all, what does > an A7V really buy you over a V2 Pro 4? If your code is writen for an ARM, then you may not want to port to a PPC. Having an ARM hard core in a part (although the fact that it is not a Xilinx compatible part) is a way to lure a bit more business from Altera. But your point I think is that the ARM 7 CPU is not a speed demon. That is true and the Triscend parts don't seem to add much to the Xilinx portfolio in my opinion. So that is why I was asking the question of what is Xilinx going to do with this company and these devices. Personally, I don't think the parts will survive as a family. I would think the first goal of Xilinx will be to bring the programmable logic of these devices into line with their existing tools. This probably means replacing the PL with sections of the VII or S3 (or V3). Then there is a good chance they will upgrade the ARM with an ARM9 since that is where the speed is and that seems to be the focus of the Xilinx marketing. I would love to see a decent line of Xilinx FPGA cores tied to an ARM7 core in a 5 volt tolerant technology. I almost went with the Atmel FPSLIC parts at one point, but was scared off by the limited product range and the possibility that they will be obsoleted at any time. The ideal marrage might be an ARM7 (like the LPC from Philips) with a low power CPLD (like the coolrunner which was also from Philips). The internal RAM and Flash will complement the MCU and PLD so that you can have the best of all worlds in one part. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67218
Actually, this is not too much different from a one-hot machine. Just like in a Johnson ring counter, JRC, it is the edge of the row of 1's that tells you the state. So you need two inputs to test for a given state. Two adjacent states can be checked with three inputs and any number of consecutively encoded states can be detected with just four inputs. Jumps are not really an issue other than with your async reset condition. The number of inputs to a given state element are a function of the number of state transitions that terminate in this state, the same as with one-hot encoding. With a JRC the number of state elements is reduced by a factor of 2 and the number of state inputs to a state element function are at most doubled, but often less than doubled and sometimes less than the one-hot case. Ray Andraka wrote: > > Rather than a one hot machine, you might consider a shift register machine that > starts off with all zeros and shifts a 1 in for each state transition. The > terminal state(s) then apply reset to the whole shift register. Branches are a > little bit uglier, but it does provide recovery from an illegal state. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67219
LUTs are very efficient "illegal state" detectors. Let's say you have a 16-state one-hot machine. Four LUTs can each detect "exactly one of my inputs is High", and a fifth LUT does the same with the four LUT outputs. So 5 LUTs can detect any illegitimate 16-bit code. Take it from there... Peter Alfke ====================================== > From: Jim Granville <no.spam@designtools.co.nz> > Organization: TelstraClear > Newsgroups: comp.arch.fpga > Date: Tue, 09 Mar 2004 09:38:34 +1300 > Subject: Re: Release asynchrounous resets synchronously > > rickman wrote: >> Mike Treseler wrote: >> >>> Hal Murray wrote: >>> >>> >>>> But that's only one of the screwup patterns. The other one is >>>> that it starts in state 0000... >>>> Is there any simple way out of that? (I can't see one.) >>> >>> I don't know a *simple* one. >>> The *stress-less* one is >>> binary encoding. >> >> >> Binary encoding does nothing to help this problem. If your FSM does not >> fully utilize all of possible encodings, not only can you make an >> invalid state transition, you can get into an unrecoverable state, just >> like the one-hot encoding. > > This depends on the low level HW. > Toggle FF's can stick in illegal states, but D registers in binary > state engines tend to illegal -> Zero. > We often use that 'hidden' feature in state engine design. > One-hot state engines are typically a primed shift register, so > illegal state preservation is more of a problem. > -jg >Article: 67220
Ngd2vhdl inserts the ROC model. This model asserts the global reset signal GSR 100 ns after the start simulation. You should always accomodate GSR in timing/structural simulation ... You can do a search of ROC on the xilinx support site. You can change roc pulse width some ngd2vhdl option. Sudhir Singh wrote: > Hello, > I have been simulating a simple 1-bit register using Xilinx XST tools > and ModelSim. The VHDL code implements a register with asynchronous > reset (clear). The register gets mapped on to the Virtex-II IOB input > FF. When I run the Post-Place and Route simulation, for some reason > the FF output remains cleared for more than 100 ns before it starts to > work properly. I am clocking the FF at 25 MHz. Changing the clock > speed does not change this behaviour. The reset line is only asserted > for one clock cycle during start up. > Also, changing the implementation to synchronous reset makes no > difference. > Does anybody have any explanation for this behaviour?Article: 67221
Peter Alfke wrote: > LUTs are very efficient "illegal state" detectors. > Let's say you have a 16-state one-hot machine. Four LUTs can each detect > "exactly one of my inputs is High", and a fifth LUT does the same with the > four LUT outputs. So 5 LUTs can detect any illegitimate 16-bit code. Take it > from there... Agreed. Q: Does current software implement this automatically, or if the user is smart enough to add an ELSE clause, will it find this optimal case ?Article: 67222
Are u refering to the `protect and `endprotect compiler directives? Looking at the IEEE spec there's no definition of these compiler directives. It's use I have only seen associated with simulation models targeted toward a specific simulator.. As the encryption/decryption I would assume is proprietary. Thus, you cannot compile in XST. I found this text in the ModelSim user guide: Though other simulators have a `protect directive, the algorithm ModelSim uses to encrypt source files is different. Hence, even though an uncompiled source file with `protect is compatible with another simulator, once the source is compiled in ModelSim, you could not simulate it elsewhere. Kelvin @ SG wrote: >Hi, there: > >Can Xilinx XST synthesize encrypted verilog source codes? For example the >following style... >What is the software to do this encryption? > >Best Regards, >Kelvin > > > > >Article: 67223
obviously 8051 has to go...before dumping the donkey you had better pick a nice horse... "rickman" <spamgoeshere4@yahoo.com> wrote in message news:404CA972.57DFE9A2@yahoo.com... > http://biz.yahoo.com/prnews/040308/sfm094_1.html > > I wonder what this means for Triscend. Does this mean they will have > funding for improving their product line? Or is this another > assimilation by the BORG and these devices will go the same way as some > others that were bought and are no longer available? > > Is supporting three hard CPUs by one FPGA company practical (8051, ARM, > PPC)? Something tells me the 8051 will be the first to go... (nobody > likes a 5 volt tolerant part ;) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 67224
Hi, there: Can Xilinx XST synthesize encrypted verilog source codes? For example those encrypted codes in Samsung RAM model...Assume the original code is synthesizable and encrypted... What is the software to do this encryption? Best Regards, Kelvin
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