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Hi I have two devices communicating via an Aurora link (single lane, full duplex) over SFP + optical cables. I need to replace one of them with a PC (testing, emulation etc etc) I see several (HITEC for example) offering PCIe cards featuring Kintex FPGA that look like they would do the job but I don't have a resource to do any HDL work. Can anyone recommend an off the shelf card?Article: 159601
karl.robinsod@gmail.com wrote: > Hi > > I have two devices communicating via an Aurora link (single lane, full duplex) over SFP + optical cables. I need to replace one of them with a PC (testing, emulation etc etc) > > I see several (HITEC for example) offering PCIe cards featuring Kintex FPGA that look like they would do the job but I don't have a resource to do any HDL work. > > Can anyone recommend an off the shelf card? My understanding of Aurora is that it's a very low level protocol and therefore it doesn't make a lot of sense to have a standard product that would connect your PC to a "generic" Aurora device. It's a bit like saying you want a board to run Cat6 cable into your PC without specifying what protocol it needs to talk. There must be some protocol running on top of Aurora between your two devices. If you didn't design the devices yourself, I would suspect that whoever made them would be a better place to start looking for a PC connection. -- GaborArticle: 159602
Sure, it's low level frames - just like Ethernet frames. I want to be able to receive and transmit raw frames. We developed the devices at both ends. We could do the work but why spend (scarce) resources recreating something that maybe already exists?Article: 159603
karl.robinsod@gmail.com wrote: > We developed the devices at both ends. We could do the work but why spend > (scarce) resources recreating something that maybe already exists? That seems pretty niche. In particular it's an FPGA protocol, so it's expected that you're going to be adding hardware to it. It isn't a something you would buy off the shelf. However I'd suggest looking around demo projects for Aurora that might be available - maybe there's something there that you can take as-is, or lightly customise? If the issue is getting the data from fPGA to the PC, something like Xillybus might be worth a look. Depends whether their licensing suits your model. TheoArticle: 159604
Tim Wescott <tim@seemywebsite.com> wrote: > If he's doing what I think he's doing he wants to produce RF directly > from a DAC that is connected to the FPGA. I think the first step here is to select the right DAC, that is able to be be driven from the FPGA and has the necessary properties on the analogue end. For instance, a randomly selected example might be: https://www.maximintegrated.com/en/products/analog/data-converters/digital-to-analog-converters/MAX5891.html which looks to have generous output bandwidth. That takes 16 bits of LVDS plus an LVDS clock. An FPGA should be able to generate that. However the next question is: can your selected FPGA manage it, or do you need a more fancy FPGA? That's basically a case of pin-counting and looking at the specs for LVDS drivers. Though it's worth doing a dummy run before you commit (before designing your board, write some code to generate maximum-frequency square wave samples and drive them out the correct pins), because the tool will tell you if you overlooked something or misunderstood. Or, if you already have an eval board, what DAC do you have? TheoArticle: 159605
Hi Tim, I am sorry but I am a bit short on time today. (to much fun things to do, to little time), so I will just reply to your message. However, I do also like to thank everybody who replied (you, Gabor, Jon, Rickman). I'll try to answers to all the remarks at once. First, an answer to your other message, and to explain my setup. Yes, indeed, the goal is to create the RF-signal directly from the FPGA. As said, this is at this point just an exercise, by trying to make something that is more-or-less "usefull" and -at the same time- a way for me to learn more about FPGAs. At the same time, it's also my first project in verilog. So, I know, you can do a lot by adding analog circuits after the DAC, but I am at this point trying to learn what exactly a FPGA is capable of doing. It started after a fellow-ham in our radio-club have a talk on "digital modes" a couple of weeks ago, mentioning PSK31. (yes, "rickman", you are correct, it is PSK31, not FSK. My error). As the talk also mentioned building your own beacon for CW, QRSS (very slow CW) or WSPR, mainly based on AD9850, I thought "it should be possible to do this for PSK31 too. The problem is that PSK31 is not just phase-shift keying. To reduce splatter, it reduces the amplitute of the signal to zero just before change is phase-shift is done. (in fact, the signal is multiplied with a cosine signal) (see here: https://upload.wikimedia.org/wikipedia/commons/7/78/Bpsk31bits.png) So it was not possible to use a AD9850 for that and -I think- a FPGA would be ideal for this. My idea was to port the design of (I think) a 2011 "elektor" project for a DDS from using a microcontroller (ATtiny) to using a FPGA. The design is very basic, using a R/2R ladder as DAC. The DDS is based on a 256-value sinewave table with 8 bits of resolution. This drives 8 output-ports connected to the R/2R ladder. So, for the best "quality" (stepping 1 value per clock-cycle in a 256 value table) the frequency of the resulting sinewave is fclock/256. Or, going the other way, for a 137 Khz sinewave, you need a 35.072 Mhz clock. (which should of course not be a problem for a FPGA). But, as said, this does mean that if you have a 8 bit R/2R ladder, you risk have the port of the lowest bit switch at 35.072 Mhz (hum ... come to think of it, probably only half of that). And this got me thinking about how fast you can actually switch a I/O pin of a FPGA. I know that FPGAs are used for "very high speed" devices, .. so I guess that the pins are able to switch very fast, ... but how fast. And, ... how do you actually interface it? I noticed that the pinplanner in the Altera software allows you to select a number of different modes for I/O pins: different voltages, HSTL class I and II, LVCMOS, LVTTL, LVDS/PPDS/RSDS (in different variants), SSTL. So I started reading documentation about all these different modes, what speed they offer, how to interface them, etc. but the information was -at least to me- quite daunting. (hence my question). BTW. My apologies to everybody for not making my original question more clear. But then, the result was that I got some information that was not planned, but not less interesting never-the-less :-) On 16-01-17 18:20, Tim Wescott wrote: >> The problem to create a digital signal for even the lowest ham-bands >> (137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at >> 35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is >> even worse, or I need to reduce the resolution of the DDS > > How are you arriving at that number? In a world where perfect > reconstruction filters exist, you can run the output frequency all the > way up to half of the clock frequency. If you want to make the > reconstruction filtering much easier you'd limit the output to something > like Fs/4 -- and 548kHz is a hell of a lot less than 35.6MHz. > > This article should help to clarify your thinking: > http://wescottdesign.com/articles/Sampling/sampling.pdf Thanks for the link. (actually quite an interesting read) :-) > As for your question about I/O rates: probably up to hundreds of MHz, but > it somewhat depends on your abilities. If you don't want to spread your > output spectrum from the DDS you may want to make a stable clock source > external of the FPGA and use that both to drive the DAC's sample clock > and the FPGA. At least the last time I checked (which, granted, was 20 > years ago), internal FPGA circuitry was too noisy to use as sampling > clocks in communications applications. That is interesting information. Thanks. :-) Again thanks to you and to all who replied. As said, currently this is just an exercise for myself, but the goal does is to actually build this thing: get the analog backend of the this done correctly and use it -as a portable FSK31-enabled beacon-, perhaps for SOTA-operations. Cheerio! Kr. Bonne.Article: 159606
On Tue, 17 Jan 2017 00:59:11 +0100, kristoff wrote: > Hi Tim, > > > > I am sorry but I am a bit short on time today. (to much fun things to > do, to little time), so I will just reply to your message. > > However, I do also like to thank everybody who replied (you, Gabor, Jon, > Rickman). I'll try to answers to all the remarks at once. > > > > > First, an answer to your other message, and to explain my setup. > > Yes, indeed, the goal is to create the RF-signal directly from the FPGA. > > As said, this is at this point just an exercise, by trying to make > something that is more-or-less "usefull" and -at the same time- a way > for me to learn more about FPGAs. At the same time, it's also my first > project in verilog. > > > So, I know, you can do a lot by adding analog circuits after the DAC, > but I am at this point trying to learn what exactly a FPGA is capable of > doing. > > It started after a fellow-ham in our radio-club have a talk on "digital > modes" a couple of weeks ago, mentioning PSK31. > (yes, "rickman", you are correct, it is PSK31, not FSK. My error). > > As the talk also mentioned building your own beacon for CW, QRSS (very > slow CW) or WSPR, mainly based on AD9850, I thought "it should be > possible to do this for PSK31 too. > > The problem is that PSK31 is not just phase-shift keying. To reduce > splatter, it reduces the amplitute of the signal to zero just before > change is phase-shift is done. (in fact, the signal is multiplied with a > cosine signal) > (see here: > https://upload.wikimedia.org/wikipedia/commons/7/78/Bpsk31bits.png) > So it was not possible to use a AD9850 for that and -I think- a FPGA > would be ideal for this. > > > My idea was to port the design of (I think) a 2011 "elektor" project for > a DDS from using a microcontroller (ATtiny) to using a FPGA. The design > is very basic, using a R/2R ladder as DAC. > > The DDS is based on a 256-value sinewave table with 8 bits of > resolution. This drives 8 output-ports connected to the R/2R ladder. > > So, for the best "quality" (stepping 1 value per clock-cycle in a 256 > value table) the frequency of the resulting sinewave is fclock/256. > Or, going the other way, for a 137 Khz sinewave, you need a 35.072 Mhz > clock. (which should of course not be a problem for a FPGA). The best quality by what measure? You're really not going to improve things much by clocking that fast. And what if you get your hands on a 16-bit DAC? Will you be asking how to do this at several GHz? > But, as said, this does mean that if you have a 8 bit R/2R ladder, you > risk have the port of the lowest bit switch at 35.072 Mhz (hum ... come > to think of it, probably only half of that). Rolling your own DAC from resistors and the output pins of a ginormous digital device is not a recipe for high quality. Unless you really, really know what you're doing here you're giving up a lot more than you're going to get by over-clocking your DDS so severely. > And this got me thinking about how fast you can actually switch a I/O > pin of a FPGA. I know that FPGAs are used for "very high speed" devices, > .. so I guess that the pins are able to switch very fast, ... but how > fast. > And, ... how do you actually interface it? > > > I noticed that the pinplanner in the Altera software allows you to > select a number of different modes for I/O pins: different voltages, > HSTL class I and II, LVCMOS, LVTTL, LVDS/PPDS/RSDS (in different > variants), SSTL. > > So I started reading documentation about all these different modes, what > speed they offer, how to interface them, etc. but the information was > -at least to me- quite daunting. > > (hence my question). My suggestion: If you stick to LVCMOS, then you won't be able to run super-blazing-fast, but you'll be plenty fast to clock a DAC at 50 or 100MHz. That should be plenty, and will, in fact, probably be challenging your PCB layout abilities (it gets ever-less trivial as the frequencies go up, although keeping the parts close together should help). You will be far happier if you just buy a DAC. Get something that's good for a sampling rate of around 50MHz, but that has an internal latch. I suspect that there will be affordable 12-bit ones, even. And then, since you need to put a good bandlimit filter in there _anyway_ to conform to good RF practice -- call it a "reconstruction filter" and be happy. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.comArticle: 159607
On 1/16/2017 6:59 PM, kristoff wrote: > Hi Tim, > > > > I am sorry but I am a bit short on time today. (to much fun things to > do, to little time), so I will just reply to your message. > > However, I do also like to thank everybody who replied (you, Gabor, Jon, > Rickman). I'll try to answers to all the remarks at once. > > > > > First, an answer to your other message, and to explain my setup. > > Yes, indeed, the goal is to create the RF-signal directly from the FPGA. > > As said, this is at this point just an exercise, by trying to make > something that is more-or-less "usefull" and -at the same time- a way > for me to learn more about FPGAs. At the same time, it's also my first > project in verilog. > > > So, I know, you can do a lot by adding analog circuits after the DAC, > but I am at this point trying to learn what exactly a FPGA is capable of > doing. > > It started after a fellow-ham in our radio-club have a talk on "digital > modes" a couple of weeks ago, mentioning PSK31. > (yes, "rickman", you are correct, it is PSK31, not FSK. My error). > > As the talk also mentioned building your own beacon for CW, QRSS (very > slow CW) or WSPR, mainly based on AD9850, I thought "it should be > possible to do this for PSK31 too. > > The problem is that PSK31 is not just phase-shift keying. To reduce > splatter, it reduces the amplitute of the signal to zero just before > change is phase-shift is done. (in fact, the signal is multiplied with a > cosine signal) > (see here: > https://upload.wikimedia.org/wikipedia/commons/7/78/Bpsk31bits.png) > So it was not possible to use a AD9850 for that and -I think- a FPGA > would be ideal for this. > > > My idea was to port the design of (I think) a 2011 "elektor" project for > a DDS from using a microcontroller (ATtiny) to using a FPGA. The design > is very basic, using a R/2R ladder as DAC. > > The DDS is based on a 256-value sinewave table with 8 bits of > resolution. This drives 8 output-ports connected to the R/2R ladder. > > So, for the best "quality" (stepping 1 value per clock-cycle in a 256 > value table) the frequency of the resulting sinewave is fclock/256. > Or, going the other way, for a 137 Khz sinewave, you need a 35.072 Mhz > clock. (which should of course not be a problem for a FPGA). > > > But, as said, this does mean that if you have a 8 bit R/2R ladder, you > risk have the port of the lowest bit switch at 35.072 Mhz (hum ... come > to think of it, probably only half of that). > > > And this got me thinking about how fast you can actually switch a I/O > pin of a FPGA. I know that FPGAs are used for "very high speed" devices, > .. so I guess that the pins are able to switch very fast, ... but how fast. > And, ... how do you actually interface it? > > > I noticed that the pinplanner in the Altera software allows you to > select a number of different modes for I/O pins: different voltages, > HSTL class I and II, LVCMOS, LVTTL, LVDS/PPDS/RSDS (in different > variants), SSTL. > > So I started reading documentation about all these different modes, what > speed they offer, how to interface them, etc. but the information was > -at least to me- quite daunting. > > (hence my question). > > > BTW. My apologies to everybody for not making my original question more > clear. But then, the result was that I got some information that was not > planned, but not less interesting never-the-less :-) > > > > On 16-01-17 18:20, Tim Wescott wrote: >>> The problem to create a digital signal for even the lowest ham-bands >>> (137 Khz) using DDS, the I/O pin of the lowest bit needs to switch at >>> 35.6 Mhz (if using a nice 8bit DDS). For higher bands, the problem is >>> even worse, or I need to reduce the resolution of the DDS >> >> How are you arriving at that number? In a world where perfect >> reconstruction filters exist, you can run the output frequency all the >> way up to half of the clock frequency. If you want to make the >> reconstruction filtering much easier you'd limit the output to something >> like Fs/4 -- and 548kHz is a hell of a lot less than 35.6MHz. >> >> This article should help to clarify your thinking: >> http://wescottdesign.com/articles/Sampling/sampling.pdf > > Thanks for the link. (actually quite an interesting read) :-) > > > >> As for your question about I/O rates: probably up to hundreds of MHz, but >> it somewhat depends on your abilities. If you don't want to spread your >> output spectrum from the DDS you may want to make a stable clock source >> external of the FPGA and use that both to drive the DAC's sample clock >> and the FPGA. At least the last time I checked (which, granted, was 20 >> years ago), internal FPGA circuitry was too noisy to use as sampling >> clocks in communications applications. > > That is interesting information. Thanks. :-) > > > Again thanks to you and to all who replied. > > As said, currently this is just an exercise for myself, but the goal > does is to actually build this thing: get the analog backend of the this > done correctly and use it -as a portable FSK31-enabled beacon-, perhaps > for SOTA-operations. Ok, so some things have been explained more clearly, other things are more muddy. All the stuff about the PSK31 signal and other background is fine, but not terribly important to what you need from us. You are asking how fast an FPGA I/O can be switched which I think is also not terribly relevant to your real problem, but I believe someone answered that... "it depends". An I/O in an FPGA typically is programmable both in drive strength and in slew rate. This is to allow support of multiple I/O standards while also allowing a minimum of RF interference being created by the digital outputs. Very fast edges create high frequency harmonics. Slower edges reduce these harmonics. So this setting ultimately sets the limit to how fast you can switch an I/O pin. However, FPGAs are intended to be synchronously clocked devices, so usually what is more important is the internal maximum clock rate which will set the maximum rate for changing the value driven to the I/O pin. This is specified in most FPGA data sheets, but does not reflect a terribly useful parameter when the FPGA is doing much logic work. This logic slows the maximum clock rate and so the I/O toggle rate in any useful design. Now, to the DDS. A DDS is typically designed with two sections, a phase accumulator and a sine generator. The phase accumulator does not always count by one. It can be programmable with a variable step size to generate a variable frequency sine wave from a fixed frequency digital clock. The formula is Fout = Fclk * N / M where Fclk is the digital clock rate, N is the step size added to the phase accumulator on each clock and M is the modulus of the phase accumulator which does not have to be a binary number. It is only important that the counter count from 0 to M-1 and then wrap around to 0 again. What is not clear to me is if the PSK31 signal is a PSK31 modulated audio tone that is then modulated on a carrier, or if the carrier is directly modulated with PSK31. The articles I've seen talk about using a PC sound card output to generate the audio signal but they don't say how this is modulated on the carrier... perhaps I'm showing my ignorance of ham radio. lol The design of a directly modulated PSK31 signal at RF means you will generate a carrier, but it needs to be modulated both in phase and amplitude. I don't know how they accomplished that in the article you read, but in the FPGA the phase modulation is just an increment that is added to the output of the phase accumulator in the DDS, equal to half the modulus M of the accumulator (180 degrees). The amplitude would be adjusted by a multiplier after the sine wave generator. BTW, in an FPGA there is no reason to limit yourself to a 256 entry look up table (LUT) for the sine wave generator. There are also shortcuts you can use to cut the size of this table by 4. So using a 2048 entry table you can use 8192 points per cycle of the sine wave. These take advantage of the redundancy of the values in a sine wave cycle, ramping up vs ramping down and positive values vs. negative values. You also don't even need to use a LUT. There are approximations using multiplies that can get you 18 bits of resolution on the input to the sine generator. This reduces what is called phase truncation which creates close in spurs to the carrier which are hard to filter out. More phase resolution reduces these spurs and gives you a cleaner signal. I spent some time looking at DDS designs in FPGAs and found that most designs stop well short of squeezing the best performance available. -- Rick CArticle: 159608
On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: > On 1/16/2017 6:59 PM, kristoff wrote: >> snip << > What is not clear to me is if the PSK31 signal is a PSK31 modulated > audio tone that is then modulated on a carrier, or if the carrier is > directly modulated with PSK31. The articles I've seen talk about using > a PC sound card output to generate the audio signal but they don't say > how this is modulated on the carrier... perhaps I'm showing my ignorance > of ham radio. lol If it's coming out of a sound card then the assumption is that you're plugging it into a single-sideband transceiver. > The design of a directly modulated PSK31 signal at RF means you will > generate a carrier, but it needs to be modulated both in phase and > amplitude. I don't know how they accomplished that in the article you > read, but in the FPGA the phase modulation is just an increment that is > added to the output of the phase accumulator in the DDS, equal to half > the modulus M of the accumulator (180 degrees). The amplitude would be > adjusted by a multiplier after the sine wave generator. Which should be easy-peasy, even for a beginner. > BTW, in an FPGA there is no reason to limit yourself to a 256 entry look > up table (LUT) for the sine wave generator. There are also shortcuts > you can use to cut the size of this table by 4. So using a 2048 entry > table you can use 8192 points per cycle of the sine wave. These take > advantage of the redundancy of the values in a sine wave cycle, ramping > up vs ramping down and positive values vs. negative values. You also > don't even need to use a LUT. There are approximations using multiplies > that can get you 18 bits of resolution on the input to the sine > generator. This reduces what is called phase truncation which creates > close in spurs to the carrier which are hard to filter out. More phase > resolution reduces these spurs and gives you a cleaner signal. > > I spent some time looking at DDS designs in FPGAs and found that most > designs stop well short of squeezing the best performance available. I'm not sure that he needs the best performance available, but given that he's a beginner I think he needs something simple. Later on he can get more complicated. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159609
On 1/17/2017 1:40 AM, Tim Wescott wrote: > On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: > >> On 1/16/2017 6:59 PM, kristoff wrote: > >>> snip << > >> What is not clear to me is if the PSK31 signal is a PSK31 modulated >> audio tone that is then modulated on a carrier, or if the carrier is >> directly modulated with PSK31. The articles I've seen talk about using >> a PC sound card output to generate the audio signal but they don't say >> how this is modulated on the carrier... perhaps I'm showing my ignorance >> of ham radio. lol > > If it's coming out of a sound card then the assumption is that you're > plugging it into a single-sideband transceiver. Apples and oranges. The sound card method is what many do because they don't need to build anything. I can't tell if the design being transcribed from an MCU to an FPGA is intended to work that way or rather it would seem RF will be generated directly. It has been a while since I looked much at single side band. Is that just AM with filtering applied or is some other method used to generate the RF signal? I was studying to get a ham license a half year ago. I should remember this. >> The design of a directly modulated PSK31 signal at RF means you will >> generate a carrier, but it needs to be modulated both in phase and >> amplitude. I don't know how they accomplished that in the article you >> read, but in the FPGA the phase modulation is just an increment that is >> added to the output of the phase accumulator in the DDS, equal to half >> the modulus M of the accumulator (180 degrees). The amplitude would be >> adjusted by a multiplier after the sine wave generator. > > Which should be easy-peasy, even for a beginner. *If* this is the method intended. >> BTW, in an FPGA there is no reason to limit yourself to a 256 entry look >> up table (LUT) for the sine wave generator. There are also shortcuts >> you can use to cut the size of this table by 4. So using a 2048 entry >> table you can use 8192 points per cycle of the sine wave. These take >> advantage of the redundancy of the values in a sine wave cycle, ramping >> up vs ramping down and positive values vs. negative values. You also >> don't even need to use a LUT. There are approximations using multiplies >> that can get you 18 bits of resolution on the input to the sine >> generator. This reduces what is called phase truncation which creates >> close in spurs to the carrier which are hard to filter out. More phase >> resolution reduces these spurs and gives you a cleaner signal. >> >> I spent some time looking at DDS designs in FPGAs and found that most >> designs stop well short of squeezing the best performance available. > > I'm not sure that he needs the best performance available, but given that > he's a beginner I think he needs something simple. > > Later on he can get more complicated. Maybe, maybe not. Amateur radio has specs on unintended emissions. I don't know if an 8 bit input/360 degree sine table would provide low enough noise. That's only 6 bits of magnitude resolution. This degree of truncation in the phase word will generate lots of close in spurs which can't be easily filtered. -- Rick CArticle: 159610
On 1/17/2017 7:50 PM, rickman wrote: > On 1/17/2017 1:40 AM, Tim Wescott wrote: >> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >> >>> On 1/16/2017 6:59 PM, kristoff wrote: >> >>>> snip << >> >>> What is not clear to me is if the PSK31 signal is a PSK31 modulated >>> audio tone that is then modulated on a carrier, or if the carrier is >>> directly modulated with PSK31. The articles I've seen talk about using >>> a PC sound card output to generate the audio signal but they don't say >>> how this is modulated on the carrier... perhaps I'm showing my ignorance >>> of ham radio. lol >> >> If it's coming out of a sound card then the assumption is that you're >> plugging it into a single-sideband transceiver. > > Apples and oranges. The sound card method is what many do because they > don't need to build anything. I can't tell if the design being > transcribed from an MCU to an FPGA is intended to work that way or > rather it would seem RF will be generated directly. > > It has been a while since I looked much at single side band. Is that > just AM with filtering applied or is some other method used to generate > the RF signal? > > I was studying to get a ham license a half year ago. I should remember > this. > > >>> The design of a directly modulated PSK31 signal at RF means you will >>> generate a carrier, but it needs to be modulated both in phase and >>> amplitude. I don't know how they accomplished that in the article you >>> read, but in the FPGA the phase modulation is just an increment that is >>> added to the output of the phase accumulator in the DDS, equal to half >>> the modulus M of the accumulator (180 degrees). The amplitude would be >>> adjusted by a multiplier after the sine wave generator. >> >> Which should be easy-peasy, even for a beginner. > > *If* this is the method intended. > > >>> BTW, in an FPGA there is no reason to limit yourself to a 256 entry look >>> up table (LUT) for the sine wave generator. There are also shortcuts >>> you can use to cut the size of this table by 4. So using a 2048 entry >>> table you can use 8192 points per cycle of the sine wave. These take >>> advantage of the redundancy of the values in a sine wave cycle, ramping >>> up vs ramping down and positive values vs. negative values. You also >>> don't even need to use a LUT. There are approximations using multiplies >>> that can get you 18 bits of resolution on the input to the sine >>> generator. This reduces what is called phase truncation which creates >>> close in spurs to the carrier which are hard to filter out. More phase >>> resolution reduces these spurs and gives you a cleaner signal. >>> >>> I spent some time looking at DDS designs in FPGAs and found that most >>> designs stop well short of squeezing the best performance available. >> >> I'm not sure that he needs the best performance available, but given that >> he's a beginner I think he needs something simple. >> >> Later on he can get more complicated. > > Maybe, maybe not. Amateur radio has specs on unintended emissions. I > don't know if an 8 bit input/360 degree sine table would provide low > enough noise. That's only 6 bits of magnitude resolution. This degree > of truncation in the phase word will generate lots of close in spurs > which can't be easily filtered. I did a little reading an found that SSB is a bit more complex to generate than the PSK31 signal. So directly generating a PSK31 modulated SSB signal will be a bit harder to do than just using a DDS circuit. But then nothing says the PSK31 signal *has* to be SSB modulated. Still not sure what the OP intends here. I hope he is coming up to speed on how a DDS works. -- Rick CArticle: 159611
On Tue, 17 Jan 2017 20:30:51 -0500, rickman wrote: > On 1/17/2017 7:50 PM, rickman wrote: >> On 1/17/2017 1:40 AM, Tim Wescott wrote: >>> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >>> >>>> On 1/16/2017 6:59 PM, kristoff wrote: >>> >>>>> snip << >>> >>>> What is not clear to me is if the PSK31 signal is a PSK31 modulated >>>> audio tone that is then modulated on a carrier, or if the carrier is >>>> directly modulated with PSK31. The articles I've seen talk about >>>> using a PC sound card output to generate the audio signal but they >>>> don't say how this is modulated on the carrier... perhaps I'm showing >>>> my ignorance of ham radio. lol >>> >>> If it's coming out of a sound card then the assumption is that you're >>> plugging it into a single-sideband transceiver. >> >> Apples and oranges. The sound card method is what many do because they >> don't need to build anything. I can't tell if the design being >> transcribed from an MCU to an FPGA is intended to work that way or >> rather it would seem RF will be generated directly. >> >> It has been a while since I looked much at single side band. Is that >> just AM with filtering applied or is some other method used to generate >> the RF signal? >> >> I was studying to get a ham license a half year ago. I should remember >> this. >> >> >>>> The design of a directly modulated PSK31 signal at RF means you will >>>> generate a carrier, but it needs to be modulated both in phase and >>>> amplitude. I don't know how they accomplished that in the article >>>> you read, but in the FPGA the phase modulation is just an increment >>>> that is added to the output of the phase accumulator in the DDS, >>>> equal to half the modulus M of the accumulator (180 degrees). The >>>> amplitude would be adjusted by a multiplier after the sine wave >>>> generator. >>> >>> Which should be easy-peasy, even for a beginner. >> >> *If* this is the method intended. >> >> >>>> BTW, in an FPGA there is no reason to limit yourself to a 256 entry >>>> look up table (LUT) for the sine wave generator. There are also >>>> shortcuts you can use to cut the size of this table by 4. So using a >>>> 2048 entry table you can use 8192 points per cycle of the sine wave. >>>> These take advantage of the redundancy of the values in a sine wave >>>> cycle, ramping up vs ramping down and positive values vs. negative >>>> values. You also don't even need to use a LUT. There are >>>> approximations using multiplies that can get you 18 bits of >>>> resolution on the input to the sine generator. This reduces what is >>>> called phase truncation which creates close in spurs to the carrier >>>> which are hard to filter out. More phase resolution reduces these >>>> spurs and gives you a cleaner signal. >>>> >>>> I spent some time looking at DDS designs in FPGAs and found that most >>>> designs stop well short of squeezing the best performance available. >>> >>> I'm not sure that he needs the best performance available, but given >>> that he's a beginner I think he needs something simple. >>> >>> Later on he can get more complicated. >> >> Maybe, maybe not. Amateur radio has specs on unintended emissions. I >> don't know if an 8 bit input/360 degree sine table would provide low >> enough noise. That's only 6 bits of magnitude resolution. This degree >> of truncation in the phase word will generate lots of close in spurs >> which can't be easily filtered. > > I did a little reading an found that SSB is a bit more complex to > generate than the PSK31 signal. So directly generating a PSK31 > modulated SSB signal will be a bit harder to do than just using a DDS > circuit. But then nothing says the PSK31 signal *has* to be SSB > modulated. > > Still not sure what the OP intends here. I hope he is coming up to > speed on how a DDS works. If all you want to do is generate PSK31 and drive an antenna with it, you do exactly the same thing at RF that you would do at audio to drive it out a sound card, only with a higher carrier. If you treat a SSB transmitter as a black box, it's just shifting up the frequency of the stuff coming in by many MHz, and pumping the result out the antenna. How that's _done_ is complicated, but it's conceptually simple. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159612
On 1/18/2017 12:12 AM, Tim Wescott wrote: > On Tue, 17 Jan 2017 20:30:51 -0500, rickman wrote: > >> On 1/17/2017 7:50 PM, rickman wrote: >>> On 1/17/2017 1:40 AM, Tim Wescott wrote: >>>> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >>>> >>>>> On 1/16/2017 6:59 PM, kristoff wrote: >>>> >>>>>> snip << >>>> >>>>> What is not clear to me is if the PSK31 signal is a PSK31 modulated >>>>> audio tone that is then modulated on a carrier, or if the carrier is >>>>> directly modulated with PSK31. The articles I've seen talk about >>>>> using a PC sound card output to generate the audio signal but they >>>>> don't say how this is modulated on the carrier... perhaps I'm showing >>>>> my ignorance of ham radio. lol >>>> >>>> If it's coming out of a sound card then the assumption is that you're >>>> plugging it into a single-sideband transceiver. >>> >>> Apples and oranges. The sound card method is what many do because they >>> don't need to build anything. I can't tell if the design being >>> transcribed from an MCU to an FPGA is intended to work that way or >>> rather it would seem RF will be generated directly. >>> >>> It has been a while since I looked much at single side band. Is that >>> just AM with filtering applied or is some other method used to generate >>> the RF signal? >>> >>> I was studying to get a ham license a half year ago. I should remember >>> this. >>> >>> >>>>> The design of a directly modulated PSK31 signal at RF means you will >>>>> generate a carrier, but it needs to be modulated both in phase and >>>>> amplitude. I don't know how they accomplished that in the article >>>>> you read, but in the FPGA the phase modulation is just an increment >>>>> that is added to the output of the phase accumulator in the DDS, >>>>> equal to half the modulus M of the accumulator (180 degrees). The >>>>> amplitude would be adjusted by a multiplier after the sine wave >>>>> generator. >>>> >>>> Which should be easy-peasy, even for a beginner. >>> >>> *If* this is the method intended. >>> >>> >>>>> BTW, in an FPGA there is no reason to limit yourself to a 256 entry >>>>> look up table (LUT) for the sine wave generator. There are also >>>>> shortcuts you can use to cut the size of this table by 4. So using a >>>>> 2048 entry table you can use 8192 points per cycle of the sine wave. >>>>> These take advantage of the redundancy of the values in a sine wave >>>>> cycle, ramping up vs ramping down and positive values vs. negative >>>>> values. You also don't even need to use a LUT. There are >>>>> approximations using multiplies that can get you 18 bits of >>>>> resolution on the input to the sine generator. This reduces what is >>>>> called phase truncation which creates close in spurs to the carrier >>>>> which are hard to filter out. More phase resolution reduces these >>>>> spurs and gives you a cleaner signal. >>>>> >>>>> I spent some time looking at DDS designs in FPGAs and found that most >>>>> designs stop well short of squeezing the best performance available. >>>> >>>> I'm not sure that he needs the best performance available, but given >>>> that he's a beginner I think he needs something simple. >>>> >>>> Later on he can get more complicated. >>> >>> Maybe, maybe not. Amateur radio has specs on unintended emissions. I >>> don't know if an 8 bit input/360 degree sine table would provide low >>> enough noise. That's only 6 bits of magnitude resolution. This degree >>> of truncation in the phase word will generate lots of close in spurs >>> which can't be easily filtered. >> >> I did a little reading an found that SSB is a bit more complex to >> generate than the PSK31 signal. So directly generating a PSK31 >> modulated SSB signal will be a bit harder to do than just using a DDS >> circuit. But then nothing says the PSK31 signal *has* to be SSB >> modulated. >> >> Still not sure what the OP intends here. I hope he is coming up to >> speed on how a DDS works. > > If all you want to do is generate PSK31 and drive an antenna with it, you > do exactly the same thing at RF that you would do at audio to drive it > out a sound card, only with a higher carrier. > > If you treat a SSB transmitter as a black box, it's just shifting up the > frequency of the stuff coming in by many MHz, and pumping the result out > the antenna. How that's _done_ is complicated, but it's conceptually > simple. It is my impression simply mixing the baseband signal up to RF is *not* what SSB is. -- Rick CArticle: 159613
> That seems pretty niche. In particular it's an FPGA protocol, so it's > expected that you're going to be adding hardware to it. It isn't a > something you would buy off the shelf. Is it though? I imagine emulating a (not ready yet) FPGA that has an Aurora= link to another one would be a common use-case. Anyway, that's OT I guess I want to take something like a Hitech Global Xilinx Kintex 7 (HTG-K700) wi= th suitable SFP+ daughter board and connect one full duplex Aurora (64B/66B= ) single lane to the PCIe interface. The goal would be to DMA data frames r= eceived from the Aurora link into the host PC's RAM and DMA data frames fro= m the host PC's RAM. Maybe raise an interrupt in the host when the transfer= is complete? I'm guessing it's not a simple as connecting the AXI4 interfaces back to ba= ck? ;)Article: 159614
rickman wrote: > On 1/18/2017 12:12 AM, Tim Wescott wrote: >> On Tue, 17 Jan 2017 20:30:51 -0500, rickman wrote: >> >>> On 1/17/2017 7:50 PM, rickman wrote: >>>> On 1/17/2017 1:40 AM, Tim Wescott wrote: >>>>> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >>>>> >>>>>> On 1/16/2017 6:59 PM, kristoff wrote: >>>>> >>>>>>> snip << >>>>> >>>>>> What is not clear to me is if the PSK31 signal is a PSK31 modulated >>>>>> audio tone that is then modulated on a carrier, or if the carrier is >>>>>> directly modulated with PSK31. The articles I've seen talk about >>>>>> using a PC sound card output to generate the audio signal but they >>>>>> don't say how this is modulated on the carrier... perhaps I'm showing >>>>>> my ignorance of ham radio. lol >>>>> >>>>> If it's coming out of a sound card then the assumption is that you're >>>>> plugging it into a single-sideband transceiver. >>>> >>>> Apples and oranges. The sound card method is what many do because they >>>> don't need to build anything. I can't tell if the design being >>>> transcribed from an MCU to an FPGA is intended to work that way or >>>> rather it would seem RF will be generated directly. >>>> >>>> It has been a while since I looked much at single side band. Is that >>>> just AM with filtering applied or is some other method used to generate >>>> the RF signal? >>>> >>>> I was studying to get a ham license a half year ago. I should remember >>>> this. >>>> >>>> >>>>>> The design of a directly modulated PSK31 signal at RF means you will >>>>>> generate a carrier, but it needs to be modulated both in phase and >>>>>> amplitude. I don't know how they accomplished that in the article >>>>>> you read, but in the FPGA the phase modulation is just an increment >>>>>> that is added to the output of the phase accumulator in the DDS, >>>>>> equal to half the modulus M of the accumulator (180 degrees). The >>>>>> amplitude would be adjusted by a multiplier after the sine wave >>>>>> generator. >>>>> >>>>> Which should be easy-peasy, even for a beginner. >>>> >>>> *If* this is the method intended. >>>> >>>> >>>>>> BTW, in an FPGA there is no reason to limit yourself to a 256 entry >>>>>> look up table (LUT) for the sine wave generator. There are also >>>>>> shortcuts you can use to cut the size of this table by 4. So using a >>>>>> 2048 entry table you can use 8192 points per cycle of the sine wave. >>>>>> These take advantage of the redundancy of the values in a sine wave >>>>>> cycle, ramping up vs ramping down and positive values vs. negative >>>>>> values. You also don't even need to use a LUT. There are >>>>>> approximations using multiplies that can get you 18 bits of >>>>>> resolution on the input to the sine generator. This reduces what is >>>>>> called phase truncation which creates close in spurs to the carrier >>>>>> which are hard to filter out. More phase resolution reduces these >>>>>> spurs and gives you a cleaner signal. >>>>>> >>>>>> I spent some time looking at DDS designs in FPGAs and found that most >>>>>> designs stop well short of squeezing the best performance available. >>>>> >>>>> I'm not sure that he needs the best performance available, but given >>>>> that he's a beginner I think he needs something simple. >>>>> >>>>> Later on he can get more complicated. >>>> >>>> Maybe, maybe not. Amateur radio has specs on unintended emissions. I >>>> don't know if an 8 bit input/360 degree sine table would provide low >>>> enough noise. That's only 6 bits of magnitude resolution. This degree >>>> of truncation in the phase word will generate lots of close in spurs >>>> which can't be easily filtered. >>> >>> I did a little reading an found that SSB is a bit more complex to >>> generate than the PSK31 signal. So directly generating a PSK31 >>> modulated SSB signal will be a bit harder to do than just using a DDS >>> circuit. But then nothing says the PSK31 signal *has* to be SSB >>> modulated. >>> >>> Still not sure what the OP intends here. I hope he is coming up to >>> speed on how a DDS works. >> >> If all you want to do is generate PSK31 and drive an antenna with it, you >> do exactly the same thing at RF that you would do at audio to drive it >> out a sound card, only with a higher carrier. >> >> If you treat a SSB transmitter as a black box, it's just shifting up the >> frequency of the stuff coming in by many MHz, and pumping the result out >> the antenna. How that's _done_ is complicated, but it's conceptually >> simple. > > It is my impression simply mixing the baseband signal up to RF is *not* > what SSB is. > I suspect all the quadrature stuff is what Tim's putting in that black box. I could be wrong. -- Les CargillArticle: 159615
On Wed, 18 Jan 2017 07:07:39 -0600, Les Cargill wrote: > rickman wrote: >> On 1/18/2017 12:12 AM, Tim Wescott wrote: >>> On Tue, 17 Jan 2017 20:30:51 -0500, rickman wrote: >>> >>>> On 1/17/2017 7:50 PM, rickman wrote: >>>>> On 1/17/2017 1:40 AM, Tim Wescott wrote: >>>>>> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >>>>>> >>>>>>> On 1/16/2017 6:59 PM, kristoff wrote: >>>>>> >>>>>>>> snip << >>>>>> >>>>>>> What is not clear to me is if the PSK31 signal is a PSK31 >>>>>>> modulated audio tone that is then modulated on a carrier, or if >>>>>>> the carrier is directly modulated with PSK31. The articles I've >>>>>>> seen talk about using a PC sound card output to generate the audio >>>>>>> signal but they don't say how this is modulated on the carrier... >>>>>>> perhaps I'm showing my ignorance of ham radio. lol >>>>>> >>>>>> If it's coming out of a sound card then the assumption is that >>>>>> you're plugging it into a single-sideband transceiver. >>>>> >>>>> Apples and oranges. The sound card method is what many do because >>>>> they don't need to build anything. I can't tell if the design being >>>>> transcribed from an MCU to an FPGA is intended to work that way or >>>>> rather it would seem RF will be generated directly. >>>>> >>>>> It has been a while since I looked much at single side band. Is >>>>> that just AM with filtering applied or is some other method used to >>>>> generate the RF signal? >>>>> >>>>> I was studying to get a ham license a half year ago. I should >>>>> remember this. >>>>> >>>>> >>>>>>> The design of a directly modulated PSK31 signal at RF means you >>>>>>> will generate a carrier, but it needs to be modulated both in >>>>>>> phase and amplitude. I don't know how they accomplished that in >>>>>>> the article you read, but in the FPGA the phase modulation is just >>>>>>> an increment that is added to the output of the phase accumulator >>>>>>> in the DDS, equal to half the modulus M of the accumulator (180 >>>>>>> degrees). The amplitude would be adjusted by a multiplier after >>>>>>> the sine wave generator. >>>>>> >>>>>> Which should be easy-peasy, even for a beginner. >>>>> >>>>> *If* this is the method intended. >>>>> >>>>> >>>>>>> BTW, in an FPGA there is no reason to limit yourself to a 256 >>>>>>> entry look up table (LUT) for the sine wave generator. There are >>>>>>> also shortcuts you can use to cut the size of this table by 4. So >>>>>>> using a 2048 entry table you can use 8192 points per cycle of the >>>>>>> sine wave. These take advantage of the redundancy of the values in >>>>>>> a sine wave cycle, ramping up vs ramping down and positive values >>>>>>> vs. negative values. You also don't even need to use a LUT. >>>>>>> There are approximations using multiplies that can get you 18 bits >>>>>>> of resolution on the input to the sine generator. This reduces >>>>>>> what is called phase truncation which creates close in spurs to >>>>>>> the carrier which are hard to filter out. More phase resolution >>>>>>> reduces these spurs and gives you a cleaner signal. >>>>>>> >>>>>>> I spent some time looking at DDS designs in FPGAs and found that >>>>>>> most designs stop well short of squeezing the best performance >>>>>>> available. >>>>>> >>>>>> I'm not sure that he needs the best performance available, but >>>>>> given that he's a beginner I think he needs something simple. >>>>>> >>>>>> Later on he can get more complicated. >>>>> >>>>> Maybe, maybe not. Amateur radio has specs on unintended emissions. >>>>> I don't know if an 8 bit input/360 degree sine table would provide >>>>> low enough noise. That's only 6 bits of magnitude resolution. This >>>>> degree of truncation in the phase word will generate lots of close >>>>> in spurs which can't be easily filtered. >>>> >>>> I did a little reading an found that SSB is a bit more complex to >>>> generate than the PSK31 signal. So directly generating a PSK31 >>>> modulated SSB signal will be a bit harder to do than just using a DDS >>>> circuit. But then nothing says the PSK31 signal *has* to be SSB >>>> modulated. >>>> >>>> Still not sure what the OP intends here. I hope he is coming up to >>>> speed on how a DDS works. >>> >>> If all you want to do is generate PSK31 and drive an antenna with it, >>> you do exactly the same thing at RF that you would do at audio to >>> drive it out a sound card, only with a higher carrier. >>> >>> If you treat a SSB transmitter as a black box, it's just shifting up >>> the frequency of the stuff coming in by many MHz, and pumping the >>> result out the antenna. How that's _done_ is complicated, but it's >>> conceptually simple. >> >> It is my impression simply mixing the baseband signal up to RF is *not* >> what SSB is. >> >> > I suspect all the quadrature stuff is what Tim's putting in that black > box. I could be wrong. Yup. Or the modulate to IF and filter, if you want to be mid-fashioned about it (_old_ fashioned, i.e. early 1950's is "quadrature stuff" all done in analog. Filtering came later). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159616
On Wed, 18 Jan 2017 00:24:25 -0500, rickman wrote: > On 1/18/2017 12:12 AM, Tim Wescott wrote: >> On Tue, 17 Jan 2017 20:30:51 -0500, rickman wrote: >> >>> On 1/17/2017 7:50 PM, rickman wrote: >>>> On 1/17/2017 1:40 AM, Tim Wescott wrote: >>>>> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >>>>> >>>>>> On 1/16/2017 6:59 PM, kristoff wrote: >>>>> >>>>>>> snip << >>>>> >>>>>> What is not clear to me is if the PSK31 signal is a PSK31 modulated >>>>>> audio tone that is then modulated on a carrier, or if the carrier >>>>>> is directly modulated with PSK31. The articles I've seen talk >>>>>> about using a PC sound card output to generate the audio signal but >>>>>> they don't say how this is modulated on the carrier... perhaps I'm >>>>>> showing my ignorance of ham radio. lol >>>>> >>>>> If it's coming out of a sound card then the assumption is that >>>>> you're plugging it into a single-sideband transceiver. >>>> >>>> Apples and oranges. The sound card method is what many do because >>>> they don't need to build anything. I can't tell if the design being >>>> transcribed from an MCU to an FPGA is intended to work that way or >>>> rather it would seem RF will be generated directly. >>>> >>>> It has been a while since I looked much at single side band. Is that >>>> just AM with filtering applied or is some other method used to >>>> generate the RF signal? >>>> >>>> I was studying to get a ham license a half year ago. I should >>>> remember this. >>>> >>>> >>>>>> The design of a directly modulated PSK31 signal at RF means you >>>>>> will generate a carrier, but it needs to be modulated both in phase >>>>>> and amplitude. I don't know how they accomplished that in the >>>>>> article you read, but in the FPGA the phase modulation is just an >>>>>> increment that is added to the output of the phase accumulator in >>>>>> the DDS, equal to half the modulus M of the accumulator (180 >>>>>> degrees). The amplitude would be adjusted by a multiplier after >>>>>> the sine wave generator. >>>>> >>>>> Which should be easy-peasy, even for a beginner. >>>> >>>> *If* this is the method intended. >>>> >>>> >>>>>> BTW, in an FPGA there is no reason to limit yourself to a 256 entry >>>>>> look up table (LUT) for the sine wave generator. There are also >>>>>> shortcuts you can use to cut the size of this table by 4. So using >>>>>> a 2048 entry table you can use 8192 points per cycle of the sine >>>>>> wave. These take advantage of the redundancy of the values in a >>>>>> sine wave cycle, ramping up vs ramping down and positive values vs. >>>>>> negative values. You also don't even need to use a LUT. There are >>>>>> approximations using multiplies that can get you 18 bits of >>>>>> resolution on the input to the sine generator. This reduces what >>>>>> is called phase truncation which creates close in spurs to the >>>>>> carrier which are hard to filter out. More phase resolution >>>>>> reduces these spurs and gives you a cleaner signal. >>>>>> >>>>>> I spent some time looking at DDS designs in FPGAs and found that >>>>>> most designs stop well short of squeezing the best performance >>>>>> available. >>>>> >>>>> I'm not sure that he needs the best performance available, but given >>>>> that he's a beginner I think he needs something simple. >>>>> >>>>> Later on he can get more complicated. >>>> >>>> Maybe, maybe not. Amateur radio has specs on unintended emissions. >>>> I don't know if an 8 bit input/360 degree sine table would provide >>>> low enough noise. That's only 6 bits of magnitude resolution. This >>>> degree of truncation in the phase word will generate lots of close in >>>> spurs which can't be easily filtered. >>> >>> I did a little reading an found that SSB is a bit more complex to >>> generate than the PSK31 signal. So directly generating a PSK31 >>> modulated SSB signal will be a bit harder to do than just using a DDS >>> circuit. But then nothing says the PSK31 signal *has* to be SSB >>> modulated. >>> >>> Still not sure what the OP intends here. I hope he is coming up to >>> speed on how a DDS works. >> >> If all you want to do is generate PSK31 and drive an antenna with it, >> you do exactly the same thing at RF that you would do at audio to drive >> it out a sound card, only with a higher carrier. >> >> If you treat a SSB transmitter as a black box, it's just shifting up >> the frequency of the stuff coming in by many MHz, and pumping the >> result out the antenna. How that's _done_ is complicated, but it's >> conceptually simple. > > It is my impression simply mixing the baseband signal up to RF is *not* > what SSB is. Not _simply_ mixing, no -- just doing that gets you a double sideband signal, with few advantages over AM. You need to remove one sideband in the mixing process. But that's all inside the black box. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159617
On 1/18/2017 12:40 PM, Tim Wescott wrote: > On Wed, 18 Jan 2017 00:24:25 -0500, rickman wrote: > >> On 1/18/2017 12:12 AM, Tim Wescott wrote: >>> On Tue, 17 Jan 2017 20:30:51 -0500, rickman wrote: >>> >>>> On 1/17/2017 7:50 PM, rickman wrote: >>>>> On 1/17/2017 1:40 AM, Tim Wescott wrote: >>>>>> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >>>>>> >>>>>>> On 1/16/2017 6:59 PM, kristoff wrote: >>>>>> >>>>>>>> snip << >>>>>> >>>>>>> What is not clear to me is if the PSK31 signal is a PSK31 modulated >>>>>>> audio tone that is then modulated on a carrier, or if the carrier >>>>>>> is directly modulated with PSK31. The articles I've seen talk >>>>>>> about using a PC sound card output to generate the audio signal but >>>>>>> they don't say how this is modulated on the carrier... perhaps I'm >>>>>>> showing my ignorance of ham radio. lol >>>>>> >>>>>> If it's coming out of a sound card then the assumption is that >>>>>> you're plugging it into a single-sideband transceiver. >>>>> >>>>> Apples and oranges. The sound card method is what many do because >>>>> they don't need to build anything. I can't tell if the design being >>>>> transcribed from an MCU to an FPGA is intended to work that way or >>>>> rather it would seem RF will be generated directly. >>>>> >>>>> It has been a while since I looked much at single side band. Is that >>>>> just AM with filtering applied or is some other method used to >>>>> generate the RF signal? >>>>> >>>>> I was studying to get a ham license a half year ago. I should >>>>> remember this. >>>>> >>>>> >>>>>>> The design of a directly modulated PSK31 signal at RF means you >>>>>>> will generate a carrier, but it needs to be modulated both in phase >>>>>>> and amplitude. I don't know how they accomplished that in the >>>>>>> article you read, but in the FPGA the phase modulation is just an >>>>>>> increment that is added to the output of the phase accumulator in >>>>>>> the DDS, equal to half the modulus M of the accumulator (180 >>>>>>> degrees). The amplitude would be adjusted by a multiplier after >>>>>>> the sine wave generator. >>>>>> >>>>>> Which should be easy-peasy, even for a beginner. >>>>> >>>>> *If* this is the method intended. >>>>> >>>>> >>>>>>> BTW, in an FPGA there is no reason to limit yourself to a 256 entry >>>>>>> look up table (LUT) for the sine wave generator. There are also >>>>>>> shortcuts you can use to cut the size of this table by 4. So using >>>>>>> a 2048 entry table you can use 8192 points per cycle of the sine >>>>>>> wave. These take advantage of the redundancy of the values in a >>>>>>> sine wave cycle, ramping up vs ramping down and positive values vs. >>>>>>> negative values. You also don't even need to use a LUT. There are >>>>>>> approximations using multiplies that can get you 18 bits of >>>>>>> resolution on the input to the sine generator. This reduces what >>>>>>> is called phase truncation which creates close in spurs to the >>>>>>> carrier which are hard to filter out. More phase resolution >>>>>>> reduces these spurs and gives you a cleaner signal. >>>>>>> >>>>>>> I spent some time looking at DDS designs in FPGAs and found that >>>>>>> most designs stop well short of squeezing the best performance >>>>>>> available. >>>>>> >>>>>> I'm not sure that he needs the best performance available, but given >>>>>> that he's a beginner I think he needs something simple. >>>>>> >>>>>> Later on he can get more complicated. >>>>> >>>>> Maybe, maybe not. Amateur radio has specs on unintended emissions. >>>>> I don't know if an 8 bit input/360 degree sine table would provide >>>>> low enough noise. That's only 6 bits of magnitude resolution. This >>>>> degree of truncation in the phase word will generate lots of close in >>>>> spurs which can't be easily filtered. >>>> >>>> I did a little reading an found that SSB is a bit more complex to >>>> generate than the PSK31 signal. So directly generating a PSK31 >>>> modulated SSB signal will be a bit harder to do than just using a DDS >>>> circuit. But then nothing says the PSK31 signal *has* to be SSB >>>> modulated. >>>> >>>> Still not sure what the OP intends here. I hope he is coming up to >>>> speed on how a DDS works. >>> >>> If all you want to do is generate PSK31 and drive an antenna with it, >>> you do exactly the same thing at RF that you would do at audio to drive >>> it out a sound card, only with a higher carrier. >>> >>> If you treat a SSB transmitter as a black box, it's just shifting up >>> the frequency of the stuff coming in by many MHz, and pumping the >>> result out the antenna. How that's _done_ is complicated, but it's >>> conceptually simple. >> >> It is my impression simply mixing the baseband signal up to RF is *not* >> what SSB is. > > Not _simply_ mixing, no -- just doing that gets you a double sideband > signal, with few advantages over AM. You need to remove one sideband in > the mixing process. But that's all inside the black box. Yes, I know. I was taking exception with your statement, "it's /just/ shifting up the frequency". Also, I'm pretty sure to get SSB you *don't* do exactly the same thing at RF that you would do at audio to generate a PSK31 signal. SSB seems to be the convention for transmitting PSK31 since this is mostly used for QRP and SSB will get a better range. -- Rick CArticle: 159618
rickman wrote: > It is my impression simply mixing the baseband signal up to RF is *not* > what SSB is. > Right, you mix the audio with a carrier, then use a sharp filter to cut off the carrier and everything on one side of the carrier. So, only the frequencies above (for upper SSB) or below (for lower SSB) are sent through. This is usually done at some fixed frequency, and then hetrodyned up to whatever frequency you actually want to transmit at. JonArticle: 159619
On Wed, 18 Jan 2017 14:23:43 -0500, rickman wrote: > On 1/18/2017 12:40 PM, Tim Wescott wrote: >> On Wed, 18 Jan 2017 00:24:25 -0500, rickman wrote: >> >>> On 1/18/2017 12:12 AM, Tim Wescott wrote: >>>> On Tue, 17 Jan 2017 20:30:51 -0500, rickman wrote: >>>> >>>>> On 1/17/2017 7:50 PM, rickman wrote: >>>>>> On 1/17/2017 1:40 AM, Tim Wescott wrote: >>>>>>> On Mon, 16 Jan 2017 23:40:22 -0500, rickman wrote: >>>>>>> >>>>>>>> On 1/16/2017 6:59 PM, kristoff wrote: >>>>>>> >>>>>>>>> snip << >>>>>>> >>>>>>>> What is not clear to me is if the PSK31 signal is a PSK31 >>>>>>>> modulated audio tone that is then modulated on a carrier, or if >>>>>>>> the carrier is directly modulated with PSK31. The articles I've >>>>>>>> seen talk about using a PC sound card output to generate the >>>>>>>> audio signal but they don't say how this is modulated on the >>>>>>>> carrier... perhaps I'm showing my ignorance of ham radio. lol >>>>>>> >>>>>>> If it's coming out of a sound card then the assumption is that >>>>>>> you're plugging it into a single-sideband transceiver. >>>>>> >>>>>> Apples and oranges. The sound card method is what many do because >>>>>> they don't need to build anything. I can't tell if the design >>>>>> being transcribed from an MCU to an FPGA is intended to work that >>>>>> way or rather it would seem RF will be generated directly. >>>>>> >>>>>> It has been a while since I looked much at single side band. Is >>>>>> that just AM with filtering applied or is some other method used to >>>>>> generate the RF signal? >>>>>> >>>>>> I was studying to get a ham license a half year ago. I should >>>>>> remember this. >>>>>> >>>>>> >>>>>>>> The design of a directly modulated PSK31 signal at RF means you >>>>>>>> will generate a carrier, but it needs to be modulated both in >>>>>>>> phase and amplitude. I don't know how they accomplished that in >>>>>>>> the article you read, but in the FPGA the phase modulation is >>>>>>>> just an increment that is added to the output of the phase >>>>>>>> accumulator in the DDS, equal to half the modulus M of the >>>>>>>> accumulator (180 degrees). The amplitude would be adjusted by a >>>>>>>> multiplier after the sine wave generator. >>>>>>> >>>>>>> Which should be easy-peasy, even for a beginner. >>>>>> >>>>>> *If* this is the method intended. >>>>>> >>>>>> >>>>>>>> BTW, in an FPGA there is no reason to limit yourself to a 256 >>>>>>>> entry look up table (LUT) for the sine wave generator. There are >>>>>>>> also shortcuts you can use to cut the size of this table by 4. >>>>>>>> So using a 2048 entry table you can use 8192 points per cycle of >>>>>>>> the sine wave. These take advantage of the redundancy of the >>>>>>>> values in a sine wave cycle, ramping up vs ramping down and >>>>>>>> positive values vs. >>>>>>>> negative values. You also don't even need to use a LUT. There >>>>>>>> are approximations using multiplies that can get you 18 bits of >>>>>>>> resolution on the input to the sine generator. This reduces what >>>>>>>> is called phase truncation which creates close in spurs to the >>>>>>>> carrier which are hard to filter out. More phase resolution >>>>>>>> reduces these spurs and gives you a cleaner signal. >>>>>>>> >>>>>>>> I spent some time looking at DDS designs in FPGAs and found that >>>>>>>> most designs stop well short of squeezing the best performance >>>>>>>> available. >>>>>>> >>>>>>> I'm not sure that he needs the best performance available, but >>>>>>> given that he's a beginner I think he needs something simple. >>>>>>> >>>>>>> Later on he can get more complicated. >>>>>> >>>>>> Maybe, maybe not. Amateur radio has specs on unintended emissions. >>>>>> I don't know if an 8 bit input/360 degree sine table would provide >>>>>> low enough noise. That's only 6 bits of magnitude resolution. >>>>>> This degree of truncation in the phase word will generate lots of >>>>>> close in spurs which can't be easily filtered. >>>>> >>>>> I did a little reading an found that SSB is a bit more complex to >>>>> generate than the PSK31 signal. So directly generating a PSK31 >>>>> modulated SSB signal will be a bit harder to do than just using a >>>>> DDS circuit. But then nothing says the PSK31 signal *has* to be SSB >>>>> modulated. >>>>> >>>>> Still not sure what the OP intends here. I hope he is coming up to >>>>> speed on how a DDS works. >>>> >>>> If all you want to do is generate PSK31 and drive an antenna with it, >>>> you do exactly the same thing at RF that you would do at audio to >>>> drive it out a sound card, only with a higher carrier. >>>> >>>> If you treat a SSB transmitter as a black box, it's just shifting up >>>> the frequency of the stuff coming in by many MHz, and pumping the >>>> result out the antenna. How that's _done_ is complicated, but it's >>>> conceptually simple. >>> >>> It is my impression simply mixing the baseband signal up to RF is >>> *not* >>> what SSB is. >> >> Not _simply_ mixing, no -- just doing that gets you a double sideband >> signal, with few advantages over AM. You need to remove one sideband >> in the mixing process. But that's all inside the black box. > > Yes, I know. I was taking exception with your statement, "it's /just/ > shifting up the frequency". Also, I'm pretty sure to get SSB you > *don't* do exactly the same thing at RF that you would do at audio to > generate a PSK31 signal. SSB seems to be the convention for > transmitting PSK31 since this is mostly used for QRP and SSB will get a > better range. If you shift the carrier by 180 degrees at audio, you shift the carrier 180 degrees at RF. If you reduce the signal by a factor of five at audio, you reduce the signal by a factor of five at RF. That's just how SSB works. Direct-to-RF PSK just does all of it's manipulations to an RF carrier, and forgoes making an audio signal that's then converted up to RF. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159620
Hi Tim, On 17-01-17 07:40, Tim Wescott wrote: >> I spent some time looking at DDS designs in FPGAs and found that most >> designs stop well short of squeezing the best performance available. > I'm not sure that he needs the best performance available, but given that > he's a beginner I think he needs something simple. > Later on he can get more complicated. That's correct. Just to have something that I can play with. The big advantage of direct synthesis is that I do not need anything else except equipement that I already have. Just a small wire from output of the DDS next to the antenna of my FT857D (as SSB receiver) and that should be enough to get the signal back into my PC using my standard "digimode" setup. If I have done everything correctly, fldigi (digimode application on linux- should then be able to decode what I have created on the FPGA. After all, this started as a small exercise for verilog for something that is -more or less- usefull. If the PSK31 encoding part works, we can then work on the analog part: add filters to "clean up" the signal, amplify, antenna-adjusment, ... but I'll do that together with some people who are better on "analog" then myself. :-) The question on "how fast can an I/O port on a FPGA actually switch" just came up while working on this. Another element I like to explore is the question what an implemention on a CPLD looks like. I have two boards with cheap altera CPLDs. It's interesting to see what the lack of a hardware multiplying unit (as compaired to a FPGA) does to a design. Cheerio! Kr. Bonne. (or, as we hams like to say) 73 kristoff - ON1ARFArticle: 159621
Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign and others are integers, who can help how to convert it to Q15 data format in VHDL? Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and others are fractional from -1 to 1 Sensor is ADC output is 16 bit format, one sign and other integer so it need only divide ? ADC output to 32768 ??Article: 159622
On Sat, 21 Jan 2017 07:58:02 -0800, abirov wrote: > Sensor data length is 16 bit data, value is from -32768 to 32767,i think > data format represented as one highest is sign and others are integers, > who can help how to convert it to Q15 data format in VHDL? > > Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and > others are fractional from -1 to 1 > > Sensor is ADC output is 16 bit format, one sign and other integer > > so it need only divide ? ADC output to 32768 ?? OK. First, in an FPGA, if you're going to start with 16 bits and end up with 16 bits and divide by 32768, what do you need to do other than relabel the bits? Second, review your number formats very carefully. I strongly suspect that everything is in 2's compliment where, indeed, the MSB is the sign bit, but things are more complicated than that. As far as I know, if it's called Q15, it's just 2's compliment integer shifted down by 15 bits. Third, verify what the ADC is putting out. Some put out 2's compliment, some put out straight binary, and it's up to you to invert the first bit to get 2's compliment. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.comArticle: 159623
Den l=C3=B8rdag den 21. januar 2017 kl. 17.38.01 UTC+1 skrev Tim Wescott: > On Sat, 21 Jan 2017 07:58:02 -0800, abirov wrote: >=20 > > Sensor data length is 16 bit data, value is from -32768 to 32767,i thin= k > > data format represented as one highest is sign and others are integers, > > who can help how to convert it to Q15 data format in VHDL? > >=20 > > Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and > > others are fractional from -1 to 1 > >=20 > > Sensor is ADC output is 16 bit format, one sign and other integer > >=20 > > so it need only divide ? ADC output to 32768 ?? >=20 > OK. First, in an FPGA, if you're going to start with 16 bits and end up= =20 > with 16 bits and divide by 32768, what do you need to do other than=20 > relabel the bits? >=20 > Second, review your number formats very carefully. I strongly suspect=20 > that everything is in 2's compliment where, indeed, the MSB is the sign= =20 > bit, but things are more complicated than that. As far as I know, if=20 > it's called Q15, it's just 2's compliment integer shifted down by 15 bits= . >=20 > Third, verify what the ADC is putting out. Some put out 2's compliment,= =20 > some put out straight binary, and it's up to you to invert the first bit= =20 > to get 2's compliment. >=20 yes it is just a relabeling until you start multiplying.=20 1.15 * 1.15 results in 2.30 to get back to 1.15 you need skip an msb and us= e the upper bits (and keep in mind the -1*-1 results in overflow) -LasseArticle: 159624
On Sat, 21 Jan 2017 09:14:18 -0800, lasselangwadtchristensen wrote: > Den lørdag den 21. januar 2017 kl. 17.38.01 UTC+1 skrev Tim Wescott: >> On Sat, 21 Jan 2017 07:58:02 -0800, abirov wrote: >> >> > Sensor data length is 16 bit data, value is from -32768 to 32767,i >> > think data format represented as one highest is sign and others are >> > integers, who can help how to convert it to Q15 data format in VHDL? >> > >> > Q15 like https://en.wikipedia.org/wiki/Q_(number_format) one sigh and >> > others are fractional from -1 to 1 >> > >> > Sensor is ADC output is 16 bit format, one sign and other integer >> > >> > so it need only divide ? ADC output to 32768 ?? >> >> OK. First, in an FPGA, if you're going to start with 16 bits and end >> up with 16 bits and divide by 32768, what do you need to do other than >> relabel the bits? >> >> Second, review your number formats very carefully. I strongly suspect >> that everything is in 2's compliment where, indeed, the MSB is the sign >> bit, but things are more complicated than that. As far as I know, if >> it's called Q15, it's just 2's compliment integer shifted down by 15 >> bits. >> >> Third, verify what the ADC is putting out. Some put out 2's >> compliment, some put out straight binary, and it's up to you to invert >> the first bit to get 2's compliment. >> >> > yes it is just a relabeling until you start multiplying. > > 1.15 * 1.15 results in 2.30 to get back to 1.15 you need skip an msb and > use the upper bits (and keep in mind the -1*-1 results in overflow) > > -Lasse I wrote my own set of Q15 and Q31 code (software, not HDL) that travels around with me. Even though it takes a few clock ticks on every operation, I simply forbid 0x80..0 -- it makes life ever so much simpler. Dunno how hard it'd be with an FPGA, but it might be worthwhile. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.com
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