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In article <airea7$1hrg$1@agate.berkeley.edu>, nweaver@ribbit.CS.Berkeley.EDU says... > In article <3D50E7C6.4488BFFA@algor.co.uk>, > Rick Filipkiewicz <rick@algor.co.uk> wrote: > >One thing I noticed is the the V-2 3DES keys are 64-bit but IIRC 3DES allows > >up to 112-bit. Is this down to the US cryptographic export restrictions ? Or > >is there some way of chaining together the 2 sets of 3 keys ? > > Hu? THe DES keys are 56 bits (with headers, padded to 64 bits), and 3 > are chaned together to create a 3DES encryption. DES uses 56bit keys with a parity bit added for each seven key bits to round out each octet, giving 64 bits per key. Since the 8th bit of each octet is defined by the other seven, it's cryptographic strength is 56 bits. 3DES uses two DES keys and Encycpher(k1), Decypher(k2), Encypher (K1) for the three cycles. The purpose of the three cycles with only two keys was to thwart meet in the middle attacks (longer keys weren't seen as a need). Since only two keys of strength56 are used it is effectively a 112 bit key. Later versions of "DES" use three keys, one for each operation. It would presumably have a strength of 168bits. ---- KeithArticle: 45851
I am using standard PALs (16L8, 20L8, 20R4, etc.) and GALs (16V8, 20V8, 22V10, etc.). The main problem that I have is that my programmer does not work in a PCI buss machine, only an old 4mb 286 ISA system that I have (it gets device address conflicts -- ??). So, I can't run Windows in my programmer system and I really don't want to run two systems where I have to move data between them. My big problem at the moment is that I have no way to re-load my CUPL (it is version 4.0a, not 4.2) into any kind of system. It's funny - the literature from Logical says that their CUPL is not copy protected. As long as you don't hide your S/N, I guess. If I could find someone who sells old s/w like this or a reference to a legitimate workaround, I'd be OK again. Bob "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3D503FD1.39D1@designtools.co.nz... > Bob Woolley wrote: > > > > I put my original CUPL disk away for safekeeping and now it is really safe - > > from me, even. I have the Tutorial, PAL search and the 4.2 upgrade disks (4 > > of them - this is DOS based CUPL), but I can't run the upgrade without the > > serial number from my original. I can't seem to find DOS-based CUPL or any > > way around the S/N. > > > > Anyone know a fix, or a source for CUPL 4.2? My old 286 has my programmer on > > it (takes an ISA slot) and an old, old 540mb drive. I really, really don't > > want to go to Windows for CUPL - must I? > > > > Thanks for the help - Bob > > What devices do you need to target ? > > -jgArticle: 45852
There is only one way to foil someone from reverse engineering your bitstream is --- don't give it to them. If someone wants to bore a hole into the device and put an atomic force microscope on the part itself, or half a dozen more expensive and complicated procedures, they can break your bitstream. Now if it costs them many times more to reverse engineer a function from the bitstream than it costs to just hire someone to roll it from scratch, who needs to worry? I look at it as software. Your bitstream is software. How do you protect software 100% of time? You don't! You make things hard enough to break into for a reasonably honest person not to try and circumvent your work. Baring that you should look at it more like software. If the function your providing is hard to do and contains a lot of stuff then it is going to be _very_ hard to reverse engineer it from the bitstream. If what your selling is just a very little, but clever, design it may be just _plain_ hard to be reverse engineered. In the mean time if I were you I'd relax until someone comes out with a program that reverses the bitstream. Till then the job of reverse engineering the bitstream is harder than re-engineering what ever function your trying to sell. Steve Casselman > Thus the safest way to prevent them from reverse engineering is to have a > large complex design that is just not worth their time to try to figure > out. >Article: 45853
A 22V10 is a GAL - PALs are 20L8 or 20R8 or something like that. There does not seem to be a lot of consistency here - Cypress calls their 22V10 a "universal PAL". Anything that has the ability to re-configure itself is a GAL - output macrocells, fuse maps, etc. I have Lattice 22V10s (and 22V10Bs) that I think I got at Jameco (or, maybe JDR Microdevices). Why don't you try them? This is the best way to go - use the part that the programmer expects. The B and D suffix refers to how the chips initialize themselves mostly, but I would be careful nonetheless. National refers to a "vertical fuse programmer" for its D PALs. Who knows what else is different? Lattice says their 22V10B is fuse map compatible with the standard part. The programmer is a different story - it may care a lot about how it applies the fuse map you give it. If it complains, you have selected the wrong part. Bob "Loi Tran" <leotran@att.net> wrote in message news:jC_39.1097$Ke2.75221@bgtnsc04-news.ops.worldnet.att.net... > I've been trying to get a simple GAL22v10 programmed so that I can get my > little personal project going. I grabbed the old PALASM software off the net > get a JEDEC file from it just fine. I buy some 22v10 except they're not GALs. > They're PALs. I have an EMP10 (needham's) programmer, but it won't take PAL > parts. Only Lattice GAL parts. I try anyway. The programming software tells > me that the number of fuses in the file doesn't match the number of fuses in > the device. Silly me! I thought 22V10 parts were all the same. It tells me > that there are 5892 fuses in the GAL22V10 I specified in software and that the > loaded JEDEC file only indicates 5828 fuses. Then it gives me an option to > fill in the last 64 fuse map addresses with 0. So here are my questions. > > > 1) Can I just tell it to fill in the remaining 64 and program a Lattice > GAL22v10 just fine? > > 2) The palasm software spits out JEDEC files for the old PAL22V10. Can I use > it to program a "modern" GAL part? Or do I have to juggle some more to get > the proper software? If not, can anyone direct me to where I can find free or > relatively cheapish software that will put out modern GAL jedec files? > > 3) Here's the other problem. The EMP10 programmer gives me 2 options in the > GAL selection. One is GAL22V10 and the other is GAL22V10B (note the B > suffix). I searched high and low and I can't find the GAL22V10B. It's been > obseleted. All they sell are D suffix parts. What's the difference? > > If anyone can answer these questions, please answer. Don't be shy. You won't > get much for your altruism, but you'll get a warm fuzzy for doing it. I hope. > > Thanks, > > LT >Article: 45854
Hi. I fail to understand from xilinx constraint manual how to do the following : I have 2 registers RG1, RG2. I do not care where they are placed in the fpga, I only want that the distance between them will be less than "10" i.e inside the square X0Y0:X9Y9 . I guess that RLOC RANGE & RLOC ORIGIN should be used, but I need an example to see how this is combined. ThankX NAHUM.Article: 45855
If you got a chance to work for a company like Xilinx grab it no matter what the situation....forget relocation and everything else! jakab John Jakson <johnjakson@earthlink.net> wrote in message news:38111bbc.0208061013.78861ca3@posting.google.com... > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3D4FE14B.D56334C2@xilinx.com>... > > John, > > > > Times are tough. Xilinx did not have layoffs (oops, not pc), or have a > > 'RIF' as all other silicon companies did. We tightened our belts, stuck > > to what we do best, and continued to execute. > > > > Recently, we realized we have an opportunity to hire the absolute best > > engineers that had to be let go by their companies who were unable to > > weather the downturn. > > > > The terms and conditions are ours to make: since no one else is hiring > > (for ASIC, ASSP, or FPGA), it matters little if we do not offer relocation > > as a benefit. We have many other benefits that are more important. It is > > up to the candidate to decide what the trade-offs are, and if they make > > sense for them. > > > > > > > > As for Peter, and myself, no one ever offered us a relocation bonus. In > > the "old days" (and Peter is such a distinguished gentleman I would not > > offer to state when that was) for me, I was told that if I wanted the job, > > I could show up and interview for it. > > > > I know, we walked uphill in the snow to and from school, but hey, if you > > have never experienced tough times, you have nothing to provide you with a > > reference. > > > > As for discrimination, that is unfair and scurrilous to suggest: we hire > > the best, end of statement. I have engineers in their 60's working for > > me. I have engineers in their 20's working for me. I don't care how old > > they are, and neither do any other managers here. > > > > Peter worked in Sweden after he graduated from college in Germany. > > > > Austin > > > > > Hi Austin > > Thanks for your response, I apologize for implying anything untoward. > > I very glad to hear that more senior engineers are working hard at > Xilinx. > > Anyway I was really unaware that reloc packages were so severely > limited by the industry at large today, as it has always been my > fortune to have been offered this in prior times for out of state > changes even when I think the economy was far worse 84 etc. I will > bear this in mind next time I talk to folks. > > Perhaps the head hunter should have been warned too, and I couldn't > find this info on your job site or on any of the positions in B & W. > > RegardsArticle: 45856
In article <c6efc5c9.0208070911.4230c999@posting.google.com>, kkps <kkps@rapid5.com> wrote: >Hi all, > >I need to implement AES (rijndael) in Xilinx VirtexE. I need to >implement the encryptor / decryptor. > >Can anybody who has done this before give me a rough estimate on how >complex this design is in terms of the time it will take. What is your performance goal? It makes a BIG difference in how long it takes. As our your design tools. If you only need about 300 Mbps, just do a single round, unpipelined, with HDL. The single round register should be at the BLockRAMs if you are doing xilinx. More performance, consider pipelining and floorplaning. Write little C programs to generate the S-box contents from the C reference code. Write a little C program to generate the specialized XOR patterns for the mix column multiplications. Can you do encryption only? CTR mode is a NIIICE mode for hardware implementation, both from performance and implementation. The biggest time is probably testing. The AES spec has some nice single case test vectors. For longer testing, just feed the data back through the algorithm and do a software version which does the same thing. >Krishna >ps: thanks Nicholas C. Weaver for your last post. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45857
Bob Woolley wrote: > > I am using standard PALs (16L8, 20L8, 20R4, etc.) and GALs (16V8, 20V8, > 22V10, etc.). The main problem that I have is that my programmer does not > work in a PCI buss machine, only an old 4mb 286 ISA system that I have (it > gets device address conflicts -- ??). So, I can't run Windows in my > programmer system and I really don't want to run two systems where I have to > move data between them. My big problem at the moment is that I have no way > to re-load my CUPL (it is version 4.0a, not 4.2) into any kind of system. > It's funny - the literature from Logical says that their CUPL is not copy > protected. As long as you don't hide your S/N, I guess. If I could find > someone who sells old s/w like this or a reference to a legitimate > workaround, I'd be OK again. Send me an email addr, and allow a couple of days to dig in the dusty archives, and I'll see what surfaces.... -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 45858
John Larkin <John@0.com> wrote in message news:<nc1ekucejrhdgou12htoi6srlm89cht9l7@4ax.com>... > Hi, > > we have a gadget that receives a lot of clocked serial data words, in > chunks of 20 bits. Each 20 bit word comes into our chip (Xilinx > XC2S50) with its own data and clock lines, and each gives us a burst > of 20 clocks + data at approximately an expected time (actually, when > a laser fires). > > We have a bunch of these, too many to use an official clock net to > clock each 20-bit shift register. So we're just using a regular net as > the clock line; we're doing plain vanilla schematic design under > ISE4.2i. > > The burst clock frequencies are nominally 20 MHz, and the available > 'official' clock is 20 MHz, so there are no obvious resynchronization > tricks available. > > So, is this safe? Since the flipflops are fast and routing delays are > sorta random, it's possible for flop N to be clocked before N+1; then, > if the Qn to Dn+1 path is fast, the N+1 flipflop could conceivably > strobe the wrong data. > > Any thoughts? > > Thanks, > > John How soon after the data comes in does it need to be read out, and is there appreciable time between the bursts? You might tie two SRL16s back to back in a single clb (they get the same clock), and after the data is in, parallelize it to the visible registers using a global clock. Still have the worry about delays of clock routing vs. data to the clb, but only at a single point for each 20-bit S/R.Article: 45859
Prashant wrote:
>
> Hi,
>
> I would like to give someone the programming bits for an FPGA for my
> design. Is there anyway the programming bits could be used to reverse
> engineer to my design ? What is the safest way to let someone use your
> design without them being able to figure out your FPGA design ?
>
> Thanks,
> Prashant
If what you are trying to do is to safe guard your design, then
giving someone the FPGA bit stream image of your design sounds risky to
me because that person can make unlimited copies of it.
However, I believe it will be pretty tough to figure out what you are
doing on in your design, since that user will be getting very low level
device information (a bit stream file), and FPGA device vendors, in
general, don't make the internal bit stream fuse map information public.
So, as long as you don't mind that the person getting it can make
unlimited copies of it, you shouldn't have to worry too much about your
design being modified.
A little off topic, but it is not impossible to figure out the
internal bit stream fuse map, as long as that person or company is very
wealthy, because a company called Clear Logic (http://www.clear-logic)
did figure out Altera's MAX CPLD and FLEX10K internal bit stream fuse
map information, and cloned them.
However, a few weeks ago there was a preliminary injunction against
Clear Logic barring them from using Altera's bit stream image within
Clear Logic devices because the Altera software licensing clause (The
legal stuff you see when you install MAX+PLUS II or Quartus II.) says
that Altera software can be used solely for Altera devices only.
If you are so concerned about your design, perhaps you may want
to consider using OTP (One Time Programmable) antifuse FPGAs from Actel
or Quicklogic, or flash-based FPGAs from Actel.
As long as you program the chip, and give it to someone (I know that's
the case.), it should be reasonably safe against someone else figuring
out the design inside.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45860I recommend that you don't instantiate IBUF, OBUFT, IOBUF, etc. I/O pad primitives from your design unless there are some special reasons (i.e., Instantiating an I/O padless IP core.), since that will make your design unnecessarily vendor specific. I/O pads are usually automatically added by the synthesis tool when synthesized, unless you ask it not to add them. If you are new to Xilinx devices, that's another reason you shouldn't be dealing with I/O pad primitives, at least initially, until you get used to the target device. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Daryl wrote: > > Hi, Assaf and others, > > Thanks for your issues, Assaf. > Now I got your idea, I think I'd better instantiate all of IBUFs and > OBUFs explicitly in my top-level code, as well as IBUFGP and FDs, but NO > PADs. > Right? > Now, my puzzle turned to whether I should/had better add IBUFs or add > IFDs in on certain conditions. If I want to use OFD to save DFFs in interval > logic and reduce output delay, I have to code asynchronous outputs in > submodules? Is there a method for me to force a process or "always@.." block > to use OFD as DFF? > > Best Regards, > > DarylArticle: 45861
Well, good luck with your PCI IP core. Again, since the Insight Electronics Spartan-II 200 PCI Development Kit comes with a slower -5 part, that will probably make your life harder when trying to reduce setup time (Tsu). Since your target frequency is 50MHz, you will likely need to get the setup time somewhere between 7ns (For 33MHz PCI) and 3ns (For 66MHz PCI). Almost certainly, you will need to rely on Floorplanner to reduce routing delays. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Erik wrote: > > Hallo Kevin, > > Yes, its right. > > Some day's ago, i have ordered the "DS-KIT-2S200-PAK-EURO" from Insight. > On this Card is a "XC2S200-5FG456C" chip and i can begin with my project. > For debugging (or others) are on this card two Digit 7-Segment-LED-Displays, > manual switches and many more interisting toys plus VHDL-Samples . > I think its a good startpoint for my project and if my PCI-Core ready and my > backside-core to big for this chip i can bay a Virtex-E (XCV300E-8BG432C), > finished my project and at the end sell the Insight-Kit (or use it for my next). > > Ciao > ErikArticle: 45862
Sylvain Yon wrote: > > I'm not sure I understand what you've done: only external signals should be > declared in the entity statement, internal signals are declared between the > architecture and begin keyword. These last one are not instantiated as iob > by any synthetizer I used (XST, leonardo). My entities have internal connections that go to each other. To keep them from going external I set up the attribute "iob" to be "false" for the connections I wanted to keep internal. It worked! Thanks to everyone here - I now have my "matrix" working. Next step is to use the multipliers as rotation shifters so I can do a fast transpose. I think that should be pretty simple. Now I at least have a clue on how VHDL works.... Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45863
Ray Andraka wrote: > First there is relatively very little expertise in DSP hardware as > opposed to DSP software out there, since most of the DSP work in the last > quarter century has been targeted at software platforms. The algorithms > developed in this time are generally optimized to software implementation > and map quite poorly to hardware, and frankly many of the good hardware > designers do not also have the DSP expertise needed to do the algorithmic > work needed for a smooth transition to hardware. Unfortunately, I don't > think tools will ever fully bridge the gap. So far, I have found it is > much easier to train a hardware designer to do signal processing than it > is to train a DSP saavy software expert to do hardware design. The > bottom line is the transition to a hardware based DSP system is not a > trivial transition, but it is well worth the rewards if executed well. Cool, there's hope for me yet! :-) Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45864
maimuna wrote: > the width of the array which i have used in my program changes with some inputs. > is there any way to set the width of the array according to the inputs. > if so please tell me > Do you mean something like signal x : array (width-1 downto 0) of std_logic ? Just specify the different width for each variable. Is that what you mean? Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45865
And Works great too.....Good show guys. -Xanatos "LET" <vvcd@ath.forthnet.gr> wrote in message news:3D51661F.976EDFC6@ath.forthnet.gr... > QUARTUS II V2.1 LINUX (C) ALTERA > fully functional > just arrived > >Article: 45866
"Daryl" <e-engineer@eastday.com> wrote in message news:<3d50bf9c@shknews01>... > Hi, Assaf and others, > > Thanks for your issues, Assaf. > Now I got your idea, I think I'd better instantiate all of IBUFs and > OBUFs explicitly in my top-level code, as well as IBUFGP and FDs, but NO > PADs. > Right? > Now, my puzzle turned to whether I should/had better add IBUFs or add > IFDs in on certain conditions. If I want to use OFD to save DFFs in interval > logic and reduce output delay, I have to code asynchronous outputs in > submodules? Is there a method for me to force a process or "always@.." block > to use OFD as DFF? > > Best Regards, > > Daryl We use a home-grown package (VHDL-speak; can't remember verilog syntax) for I/O pads but it's basically just out <= in for combinatorial I/O, registers or registers and 3-state buffers. We use this package to make everyone looking at the design be aware that these signals are going off-chip and to make things standard; it's easier to put constraints for both Synplify and PAR if the I/O pad is a separate entity. If you look at the Xilinx library guide, you will see that there is no such animal as a registered I/O pad; all synthesis tools just wire normal FFs to the pads and let/force PAR to stuff the FF into the pad.Article: 45867
Hi I have XST VHDL project with the package. There are some constants, and component declarations in this package. But if I try to simulate this project Modelsim gives following lines, and stops: # ERROR: Could not find work.mizar_pkg # ERROR: mizartest_tbwf.translate_vhw(20): cannot find expanded name: work.mizar_pkg # ERROR: mizartest_tbwf.translate_vhw(20): Unknown field: mizar_pkg. # -- Loading package textio # -- Loading package std_logic_textio # ERROR: mizartest_tbwf.translate_vhw(26): VHDL Compiler exiting # ERROR: c:/Modeltech_xe/win32xoem/vcom failed. WHY? furiaArticle: 45868
O.K. thanx for reading, but I solved my problem myself. Problem was that Xilinx's file glbl.v (contains declaration of GTS< GSR ...) was not compiled. So I compiled it to simprims_ver and added "-L simprims_ver.glbl" HDL Designer. By. "Peter Baltazarovic" <baltazarovic@ncode.sk> wrote in message news:airb30$hh4$1@virtual.nextra.sk... > Hi, > > I am trying to simulate 4 x CLK multiplier with DLLs in Spartan2 (as > described in XAPP132), but in ModelSim I am getting this error: > # ** Error: (vsim-3043) d:/Xilinx/verilog/src/unisims/OBUF.v(21): > Unresolved reference to 'glbl' in glbl.GTS. > It is because of line: > OBUF lckpad (.I(LOCKED_DLL), .O(LOCKED)); > > Can anybody help me? > > Thank you a lot. > > Peter. > > > >Article: 45869
furia1024@news.secom.com.pl wrote: [...] > But if I try to simulate this project Modelsim gives following lines, and > stops: > > # ERROR: Could not find work.mizar_pkg > # ERROR: mizartest_tbwf.translate_vhw(20): cannot find expanded name: > work.mizar_pkg [...] > WHY? Look like you didn't compile the package. You need to do that, before you compile the entity which uses it. Cheers Stefan -- Stefan Doll, München, Germany http://www.stefanVHDL.comArticle: 45870
John_H wrote: > > Shorts? Opens? Wrong test point on the board? I'd look for the > obvious problems *outside* the part. Actually that was it: the testpoint. I really feel silly. > It sounds like your internals are fine unless you've forgotten a > tristate or reset or some such. Good luck! There is another problem, somewhere else but that's another story. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 02 http://www.IPricot.com/Article: 45871
You can control this flag using the ISE GUI interface (at least, in 4.2 release). It's under MAP properties but you need to set the Property Display Level for the Process Settings to ADVANCED, not STANDARD, to see this property. You can change this in the preferences options. Francois Choquette LACIME nahum_barnea@yahoo.com (Nahum Barnea) wrote in message news:<fc23bdfc.0208062214.669a167e@posting.google.com>... > Hi. > I would like to hear about the experience of xilinx users that used > "-k" flag in the "map" program. > > I did'nt see a way to control this flag from the GUI, the help says > > > -k 4|5|6|7|8 Function size for covering combinational logic. > If -k > is not specified, the default is -k 4. This > gives the > best balance of runtime to quality of results. > Using > larger values of -k can give superior results > at the > expense of runtime. > > And I wishto know did it realy helped virtex2 users or did it just > consume more time ? > > ThankX, > NAHUMArticle: 45872
Than differ IOBUF PCI33_5 and LVTTLArticle: 45873
> data <= do when dot = '0' else (others => 'z'); (do from submodule) > din <= data; (din to submodule) That will work fine. > If I am sure that the synthesis tool will infer the > components I need properly, I could adopt the coding style a bit abstrctly. That's how I do it. > tell me some resource to study? Start with http://www.vhdl.org/comp.lang.vhdl/FAQ1.html -- Mike TreselerArticle: 45874
Anyone actually managed to get one of these yet? Doesn't show up at findchips.com
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