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Messages from 49875

Article: 49875
Subject: Re: C\C++ to VHDL Converter
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Sat, 23 Nov 2002 10:43:10 -0500
Links: << >>  << T >>  << A >>
Hi Ray,

"Ray Andraka" <ray@andraka.com> wrote in message
news:3DDD2E65.3DE3AEE8@andraka.com...
> But is not the placement attributes that are tool specific.  If you do
those
> with user attributes, like my example, those do not change from tool to
tool,
> and you get EXACTLY the same result regardless of the tool provided your
tool
> supports user attributes.
>  It is the attributes for RTL level stuff, things
> like keep buffers, preserving inferred registers and what not that can
> differ....basically the synthesis directive type attributes.

Understood.  It's that the overall issue of tool dependency still exists
(and may always) even with HDLs, to some degree, and of course, depends on
your level of use.

> This part of the discussion started with your asking about, and positing
that
> mapping and placement in a structural design makes the code tool-specific.
My
> arguement is that it does not, and in fact makes the code more portable
than
> 'rope-pushed' RTL.  The vendor specific attributes have nothing to do with
> place and map for the most part (although some do have vendor equivalents,
> xc_map and xc_rloc in synplify, for example, which I don't use because a)
they
> are not portable, b) they had been broken for a while, c) they are not as
> flexible as the user attributes).

The issue, at least in my book, is repeatibility and predictibility,
irrespective as to what the cause is.  If you don't instantiate/netlist etc.
your design (which most no one does), you won't get repeatable (or
predictable) results, between tool vendor and even tool revision...or much
less even changes to your own code.  For some people, that isn't an issue.
For some, it is a very big issue.

Austin



Article: 49876
Subject: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: m8931612@student.nsysu.edu.tw (Ru-Chin Tsai)
Date: 23 Nov 2002 11:22:34 -0800
Links: << >>  << T >>  << A >>
I apply the same testbench to simulate pre-synthesys(function) and
post-synthesis(timming) top-design. Function simulation result is
correct. But timming simulation exists unknow result, that is the
value of many register outputs fall into 'X' or "XX..." over the whole
simulation time range.  The code has work function on FPGA correctly.
Why the post-synthesis registers present 'X' and "XX.." state?

Article: 49877
Subject: Re: C\C++ to VHDL Converter
From: Ray Andraka <ray@andraka.com>
Date: Sat, 23 Nov 2002 19:38:44 GMT
Links: << >>  << T >>  << A >>
Agreed.  For schematics, the issue is file format prevents portability between
tools.  Unless you have a conversion program, you are unlikely to be able to
read the schematics by anything other than the program that created them.  HDLs
have the portability to be read by pretty much any synth tool, however for stuff
that is not structural, the results may not be the same.  One of the points for
HDLs is that you can delegate some of the detail design to the tool (RTL
synthesis).  They fortunately leave the hooks for you to instantiate what you
don't want inferred, in which case you keep that responsibility and the tool
becomes a generator rather than a synthesizer for that part of the design.
Remember, schematics are equivalent to graphical structural instantiation.  The
capability of inferring logic from an abstracted representation can save time in
the design, provided you can tolerate the uncertainty in what the exact
implementation is.  For most users, that uncertainty is not an issue and is
therefore far offset by the abstraction gained.  The trouble spot is in between
where users doing an abstracted design expect to get the performance of an
instantiated design without having to put in the effort that goes with it.
About the only true advantage I still see to schematics is the visual vs textual
representation of the netlist.

We do a mix of RTL and structural in our designs.  The data path is generally
placed structural logic comprised of library elements for common functions.  The
control is generally carefully executed RTL (combinatorial terms between ff's
kept simple enough to be mapped into one or two logic layers).

Austin Franklin wrote:

>
>
> The issue, at least in my book, is repeatibility and predictibility,
> irrespective as to what the cause is.  If you don't instantiate/netlist etc.
> your design (which most no one does), you won't get repeatable (or
> predictable) results, between tool vendor and even tool revision...or much
> less even changes to your own code.  For some people, that isn't an issue.
> For some, it is a very big issue.
>
> Austin

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 49878
Subject: Re: BGA footprints
From: hmurray@suespammers.org (Hal Murray)
Date: Sat, 23 Nov 2002 19:50:39 -0000
Links: << >>  << T >>  << A >>
>Ah, I found the footprints - somewhat odd to not have them in the
>datasheets. But there were no gerbers and no pcb files.

It's reasonably common to omit package descriptions from data sheets.
I assume it's done primarily to save paper (or reduce clutter)
and/or make it easier to keep things up to date.

In my experience, it's not common to find gerbers or PCB files.
Are you looking for prototype boards?  Something you can use
as a good example?  That seems like a good idea.  Perhaps we should
encourage vendors to make them available.  (Then we would have to
argue over which tool set they should use.)

It is common to see suggested patterns/footprints for packages.
They might be in an app note rather than the data sheet.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 49879
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: Muzaffer Kal <kal@dspia.com>
Date: Sat, 23 Nov 2002 23:16:47 GMT
Links: << >>  << T >>  << A >>
On 23 Nov 2002 11:22:34 -0800, m8931612@student.nsysu.edu.tw (Ru-Chin
Tsai) wrote:

>I apply the same testbench to simulate pre-synthesys(function) and
>post-synthesis(timming) top-design. Function simulation result is
>correct. But timming simulation exists unknow result, that is the
>value of many register outputs fall into 'X' or "XX..." over the whole
>simulation time range.  The code has work function on FPGA correctly.
>Why the post-synthesis registers present 'X' and "XX.." state?

X or unknown state happens because of two reasons: uninitialized
register or timing violations. The former is possible even in RTL but
the latter usually only happens in back-annotated gate-level. If the
functional simulation is OK in gate-level this means all the X values
you're seeeing are happening because of timing violations. When you
run back-annotated post-layout simulations, if the setup or hold
checks of flip-flops are violated the outputs are set to X. To prevent
this, you have to run Static timing analysis and make sure that you're
meeting your timing constraints for synchronous paths. Also you have
to check that the registers which accept asynchronous inputs are
double-flopped (at least) and that the first flop is prevented from
generating timing violations.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 49880
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: strut911@hotmail.com (strut911)
Date: 23 Nov 2002 17:42:02 -0800
Links: << >>  << T >>  << A >>
If you see a lot of XXX's in your post-synth simulation, the first
things you want to do are check the clock and the reset (same as on
the board). Make sure that your clocks are valid, especially coming
out of the DLL if you are using it. The DLL has a certain delay in
order to lock the output to the input waveform. During this time,
there is no clock. If your testbench is writing to the registers to
initialize your design at this point, then that would explain your
XXX's. Also, if you are using block ram and are using the Xilinx
models, you may want to check for some type of timing violation on the
block ram. It could be multiple reasons. I would recommend a few
things before you proceed:

1. If you are using any library specific structures such as (for
Xilinx:)
CLOCKDLL, BUFGMUX, etc..., I recommend you to use the verilog models
that come with the tool. In Xilinx, these can be found in
/Xilinx/verilog/src/unisims.

2. Re-run your RTL simulations using these models and see if you can
duplicate your post-synthesis problem.

3. If it is still okay, then make sure your post-synth netlist is
using the same models as your RTL simulation (when applicable. such as
for RAM, MULTIPLIERS, DLL...). If not, modify it so it does and re-run
simulation.

4. If you still have a mismatch, you will need to do some tracing. I
have also had mismatches between RTL and synth in the past when I used
the Synplify Pro v7.02 Resource Sharing option. I am not sure what
synthesis tool you are using, but you may want to check to see if
there is any errata available.

Good Luck. This is the important part of engineering so enjoy the
frustration.
strut911

m8931612@student.nsysu.edu.tw (Ru-Chin Tsai) wrote in message news:<d22f039b.0211231122.48ff914f@posting.google.com>...
> I apply the same testbench to simulate pre-synthesys(function) and
> post-synthesis(timming) top-design. Function simulation result is
> correct. But timming simulation exists unknow result, that is the
> value of many register outputs fall into 'X' or "XX..." over the whole
> simulation time range.  The code has work function on FPGA correctly.
> Why the post-synthesis registers present 'X' and "XX.." state?

Article: 49881
Subject: Re: Metastability in FPGAs
From: hmurray@suespammers.org (Hal Murray)
Date: Sun, 24 Nov 2002 01:43:32 -0000
Links: << >>  << T >>  << A >>
>The results would have some randomness because noise is random which is why
>I previously suggested a high frequency agitation signal. Vibrating the
>hill side to side with 5 feet amplitude would limit the duration of
>metastability to a fraction of one cycle of the agitation signal + however
>long it takes the ball to roll down the side of the hill. 

I don't like the phrase "limit the duration of metastability".

Your trick might make things better, but it won't solve the problem.
At best it will just change the probabilities.

Consider your ball and very steep hill example.  If you vibrate
the hill, the ball might bounce back and forth between opposite
extremes of the vibrating hill.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 49882
Subject: Re: Global clock routing
From: wangmanxi@yahoo.com (siriuswmx)
Date: 23 Nov 2002 18:31:53 -0800
Links: << >>  << T >>  << A >>
agreed.

vishker@yahoo.com (Vishker) wrote in message news:<9ea7e3a3.0211210000.6ba5bd0@posting.google.com>...
> Best way is to use a single fast clock and sample the signals. But if
> you want it to implement it in multiple clocks and doesn't want xilinx
> to use global clocks then you can use some attributes in synthesis ...
> like for synplify you can use syn_noclockbuf attribute .. you can find
> something similar in Leonardo spectrum  or you can instantiate IBUFs
> for the clock signals. I guess this way you can prevent xilinx from
> using global clocks.
> 
> -Vishker
> 
> 
> "Mirko Scarana" <mirko.scarana@tiscali.it> wrote in message news:<295d08614c0ab0edc721718738d6dbca.114635@mygate.mailgate.org>...
> > Hi all,
> > I am relatively new to fpga design, and I am experiencing a problem with
> > global clock routing.
> > I am using ISE v5.1 targeting a Xilinx x2v500fg456 device.
> > The point is that my design uses some (slow) signals to edge-trigger
> > different internal registers.
> > When it comes to the place & route phase, the tool tries to consider all
> > those signals as global clocks and fails the routing.
> > Apart from modifying the design by avoiding edge-triggering on those
> > signals, is it possible to force the P&R tool not to route the signals
> > as global clocks?
> > By the way, the signals are internally generated, they are not external
> > inputs.
> > Thanks in advance, best regards.
> > 
> > Mirko Scarana 
> > PhD Student
> > "La Sapienza" University of Rome

Article: 49883
Subject: What's the matter with "clock skew and data delay"?
From: wangmanxi@yahoo.com (siriuswmx)
Date: 23 Nov 2002 18:52:08 -0800
Links: << >>  << T >>  << A >>
hi,all
   i am a newer to fpga, and i am using QUARTUS to target
EP20k200rc240-3v.
   the problem is that: when i complied the project the complication
report always gave me the message "Circuit may not operate. 12017
non-operational path(s) clocked by clock gclk have clock skew larger
than the data delay. See the Compilation Report for details."
  can you tell me what's the matter with "clock skew and data delay"?
 thanks a lot!

Article: 49884
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: "Srinivasan Venkataramanan" <srinivasan@siliconsystems.no_spam.co.in>
Date: Sat, 23 Nov 2002 19:15:08 -0800
Links: << >>  << T >>  << A >>
Hi,
   As others have suggested, there could be some uninitalized
registers/inputs and/or timing violations. Another major cause could be that
your memories are not initialized, try initializing them to say "0".

Good Luck,
Srinivasan


--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

I don't speak for Intel
"Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message
news:d22f039b.0211231122.48ff914f@posting.google.com...
> I apply the same testbench to simulate pre-synthesys(function) and
> post-synthesis(timming) top-design. Function simulation result is
> correct. But timming simulation exists unknow result, that is the
> value of many register outputs fall into 'X' or "XX..." over the whole
> simulation time range.  The code has work function on FPGA correctly.
> Why the post-synthesis registers present 'X' and "XX.." state?



Article: 49885
Subject: Re: What's the matter with "clock skew and data delay"?
From: "Subroto Datta" <sdatta@altera.com>
Date: Sun, 24 Nov 2002 03:33:55 GMT
Links: << >>  << T >>  << A >>
Timing Analysis using Quartus is covered in detail in the following
Application Note:

http://www.altera.com/literature/an/an123.pdf

Typically when conditions like this occur, it is an indication that there
are setup or hold time violations. One way of minimizing clock skew is to
assign the clock to a global clock.

- Subroto Datta

"siriuswmx" <wangmanxi@yahoo.com> wrote in message
news:4528663b.0211231852.33ba9a8f@posting.google.com...
> hi,all
>    i am a newer to fpga, and i am using QUARTUS to target
> EP20k200rc240-3v.
>    the problem is that: when i complied the project the complication
> report always gave me the message "Circuit may not operate. 12017
> non-operational path(s) clocked by clock gclk have clock skew larger
> than the data delay. See the Compilation Report for details."
>   can you tell me what's the matter with "clock skew and data delay"?
>  thanks a lot!



Article: 49886
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: Ken McElvain <ken@synplicity.com>
Date: Sun, 24 Nov 2002 04:33:38 GMT
Links: << >>  << T >>  << A >>
One of the most common problems in simulation at the
gate level is caused by the conservative way that X's
are propagated.

Take the expression:

out = sel & a | ~sel & b;

if sel = X, a = 1, b = 1 then what should out be?

In a simulator ~X is X so the expression evaluates to X.
In a real circuit with X coming from an uninitialized
register, it is either 0 or 1, you just don't know which.
In both cases out will have the value 1.

Another RTL/gate correlation problem:
In RTL I might write something like

if (sel)
    out = a;
else
    out = b;

What do you think a simulator does when sel is X.  A hint is
that it will execute one of the two branches.  Most RTL
code does not explicitly check for X in branch conditions.
It could, but it is too much work for the value for most designers.
	

- Ken


Ru-Chin Tsai wrote:

> I apply the same testbench to simulate pre-synthesys(function) and
> post-synthesis(timming) top-design. Function simulation result is
> correct. But timming simulation exists unknow result, that is the
> value of many register outputs fall into 'X' or "XX..." over the whole
> simulation time range.  The code has work function on FPGA correctly.
> Why the post-synthesis registers present 'X' and "XX.." state?
> 


Article: 49887
Subject: Re: An Virtex FPGA architecture question
From: muthu_nano@yahoo.co.in (Muthu)
Date: 23 Nov 2002 21:26:30 -0800
Links: << >>  << T >>  << A >>
Kuan Zhou <zhouk@rpi.edu> wrote in message news:<Pine.SOL.3.96.1021122214053.15861A-100000@vcmr-86.server.rpi.edu>...
> Hi,
>     I am a newbie in FPGA.Currently I am looking the Virtex TM
> 2.5V datasheet.In Figure 5 of DS003-2.pdf Page 5, there is a detailed view
> of Virtex Slice.But I can't understand what WSO,WSH,DI,DG do in the CLB.
> Seems like WSO and WSH provide the WE signal and DI,DG provide the data.
> Can anyone specify these control logics to me?
> 
>     Thank you very much!
>  
> 
> 
> sincerely
> -------------
> Kuan Zhou
> ECSE department

Hi,
If you see the diagram, there is 2 inputs Bx and By. These are Data
input pins, from which the LUTs outputs will be initialised. These
pins will act as a data input pins if you are using the LUT as a
SelectRAM.

That 2 Block what you metioned will control this initialisation of LUT
to a particular value / reset condition

correct me if i am wrong.

Best regards,
Muthu

Article: 49888
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: muthu_nano@yahoo.co.in (Muthu)
Date: 23 Nov 2002 21:40:07 -0800
Links: << >>  << T >>  << A >>
Muzaffer Kal <kal@dspia.com> wrote in message news:<tl20uucjh6cl13omrht1825325t7cka6ll@4ax.com>...
> On 23 Nov 2002 11:22:34 -0800, m8931612@student.nsysu.edu.tw (Ru-Chin
> Tsai) wrote:
> 
> >I apply the same testbench to simulate pre-synthesys(function) and
> >post-synthesis(timming) top-design. Function simulation result is
> >correct. But timming simulation exists unknow result, that is the
> >value of many register outputs fall into 'X' or "XX..." over the whole
> >simulation time range.  The code has work function on FPGA correctly.
> >Why the post-synthesis registers present 'X' and "XX.." state?
> 
> X or unknown state happens because of two reasons: uninitialized
> register or timing violations. The former is possible even in RTL but
> the latter usually only happens in back-annotated gate-level. If the
> functional simulation is OK in gate-level this means all the X values
> you're seeeing are happening because of timing violations. When you
> run back-annotated post-layout simulations, if the setup or hold
> checks of flip-flops are violated the outputs are set to X. To prevent
> this, you have to run Static timing analysis and make sure that you're
> meeting your timing constraints for synchronous paths. Also you have
> to check that the registers which accept asynchronous inputs are
> double-flopped (at least) and that the first flop is prevented from
> generating timing violations.
> 
> Muzaffer Kal
> 
> http://www.dspia.com
> ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations


Hi,

Run the post-synthesis simulation with lesser frequency and assure
that your design don't have any timing violation. If the value X comes
even with the lesser frequency, then check the appy of reset signal.
Normally if you are using asynchronous, make sure that you are not
de-asserting the reset signal exactly at the active edge of the clock
and
Better to apply reset as a pulse. 
Hope this helps.

Best regards,
Muthu

Article: 49889
Subject: How to use altera's IP core in QUARTUS?
From: wangmanxi@yahoo.com (siriuswmx)
Date: 23 Nov 2002 22:57:58 -0800
Links: << >>  << T >>  << A >>
HI,all
 i am newer to fpga, and i am always puzzled by something.
 When i place the symbol and click the MegaWizard plug-in manager
button , i see the "IP Mega store" in the left window,  what is the
use of these IP core, and how use it correctly?
  thank you very much!

Article: 49890
Subject: Re: What's the matter with "clock skew and data delay"?
From: Kumaran Selvaratnam <selvars@yahoo.com>
Date: Sun, 24 Nov 2002 02:09:09 -0500
Links: << >>  << T >>  << A >>
However, I think the problem is that you are not really doing
anything with the creation of the clock network.
For FPGAs the clock network is pre-designed during the FPGA fabric 
design considering the external clock source as the input.
(correct me if I am wrong)
I think the mapping software software takes care of the clock network by 
mapping appropriate logic at certain places to achieve the best results 
for the pre-existing clock-tree. Therefore, you may have to change the 
way log blocks are mapped between different clock-tree leaves.
I think you may get this kind of errors due to poor floorplanning as well.
Good luck.
Kumaran

Subroto Datta wrote:

> Timing Analysis using Quartus is covered in detail in the following
> Application Note:
> 
> http://www.altera.com/literature/an/an123.pdf
> 
> Typically when conditions like this occur, it is an indication that there
> are setup or hold time violations. One way of minimizing clock skew is to
> assign the clock to a global clock.
> 
> - Subroto Datta
> 
> "siriuswmx" <wangmanxi@yahoo.com> wrote in message
> news:4528663b.0211231852.33ba9a8f@posting.google.com...
> 
>>hi,all
>>   i am a newer to fpga, and i am using QUARTUS to target
>>EP20k200rc240-3v.
>>   the problem is that: when i complied the project the complication
>>report always gave me the message "Circuit may not operate. 12017
>>non-operational path(s) clocked by clock gclk have clock skew larger
>>than the data delay. See the Compilation Report for details."
>>  can you tell me what's the matter with "clock skew and data delay"?
>> thanks a lot!
>>
> 
> 


Article: 49891
Subject: Re: BGA footprints
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 23 Nov 2002 23:16:10 -0800
Links: << >>  << T >>  << A >>
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<arnrag$l5s$1@news.tu-darmstadt.de>...
....
> For me it looks like Altera like Xilinx in their application notes don't
> make proposals for the decoupling capacitors. Or does Altera?
> 
> I refrain to sign up yet on another site just for checking that fact. Can
> anybody confirm?
> 
> Thanks


Actually, I thought Xilinx did a very nice job in several App notes
describing how to calculate decoupling capacitors. I don't know
about Altera ... 

rudi
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Article: 49892
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: russelmann@hotmail.com (Rudolf Usselmann)
Date: 23 Nov 2002 23:22:20 -0800
Links: << >>  << T >>  << A >>
m8931612@student.nsysu.edu.tw (Ru-Chin Tsai) wrote in message news:<d22f039b.0211231122.48ff914f@posting.google.com>...
> I apply the same testbench to simulate pre-synthesys(function) and
> post-synthesis(timming) top-design. Function simulation result is
> correct. But timming simulation exists unknow result, that is the
> value of many register outputs fall into 'X' or "XX..." over the whole
> simulation time range.  The code has work function on FPGA correctly.
> Why the post-synthesis registers present 'X' and "XX.." state?


My guess is, you have timing violations somewhere. Otherwise
I would expect the functional only simulation would result in
unknowns as well. Usually your verilog simulator and gate level
simulation models of your target technology library should print
out warning messages. Make sure you enable all warning and error
messages in your verilog (or vhdl) simulation tool, and if
applicable in the library as well (I have seen libraries that
required a `define <some_flag> to report timing violations...).

Good Luck !

rudi
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Article: 49893
Subject: Re: BGA footprints
From: Marcin E. Hamerla <mehamerla@pro.onet.pl>
Date: Sun, 24 Nov 2002 10:45:37 +0100
Links: << >>  << T >>  << A >>
Rudolf Usselmann napisal(a):

>> For me it looks like Altera like Xilinx in their application notes don't
>> make proposals for the decoupling capacitors. Or does Altera?
>> 
>> I refrain to sign up yet on another site just for checking that fact. Can
>> anybody confirm?
>
>Actually, I thought Xilinx did a very nice job in several App notes
>describing how to calculate decoupling capacitors. I don't know
>about Altera ... 

In Altera datasheets (EPM, FLEX10k) decoupling is described. I can not
compare it to X because I never used X parts.

-- 
Pozdrowienia, Marcin E. Hamerla

"What is it about audio that brings out all the idiots?"

Article: 49894
Subject: Re: Why do post-synthesis simulation result fall into unknow output
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 24 Nov 2002 09:48:36 +0000
Links: << >>  << T >>  << A >>


Ken McElvain wrote:

> One of the most common problems in simulation at the
> gate level is caused by the conservative way that X's
> are propagated.
>
> Take the expression:
>
> out = sel & a | ~sel & b;
>
> if sel = X, a = 1, b = 1 then what should out be?
>
> In a simulator ~X is X so the expression evaluates to X.
> In a real circuit with X coming from an uninitialized
> register, it is either 0 or 1, you just don't know which.
> In both cases out will have the value 1.
>
> Another RTL/gate correlation problem:
> In RTL I might write something like
>
> if (sel)
>     out = a;
> else
>     out = b;
>
> What do you think a simulator does when sel is X.  A hint is
> that it will execute one of the two branches.  Most RTL
> code does not explicitly check for X in branch conditions.
> It could, but it is too much work for the value for most designers.
>
>

This A | ~A problem is definitely one for ASIC synthesis but I've never seen
it in Xilinx post-route sim since they fixed up the LUT simprims model in
2.1i. Prior to that I had to use my own hacked versions of these models.

There's another source of this stuff, again from overly conservative models.
This arises on a FF:

always (posedge clk)
    if (set)
        out <= 1;
    else
        out <= in;

If  in is 1 and set is `X' at the clock re then the new value of out should
be 1 since this would be the case no matter whether set = 0 or 1. Once again
the old, pre 2.1i, Xilinx FF UDPs would put the output to X in this case.


Article: 49895
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: "Niv" <niv@ntlworld.com>
Date: Sun, 24 Nov 2002 09:58:26 -0000
Links: << >>  << T >>  << A >>
If you're using ModelSim, try turning off the propogation of 'X's.  This is
done by typing -GXon = FALSE in the command line. It prevents setup & hold
violations propogating. This is useful when you have multiple clock domains
and link them with meta stability registers, which inevitably produce setup
& hold violations.

HOWEVER, you MUST understand the cause of these errors to ensure they are
not real problems.
Niv.
"Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message
news:d22f039b.0211231122.48ff914f@posting.google.com...
> I apply the same testbench to simulate pre-synthesys(function) and
> post-synthesis(timming) top-design. Function simulation result is
> correct. But timming simulation exists unknow result, that is the
> value of many register outputs fall into 'X' or "XX..." over the whole
> simulation time range.  The code has work function on FPGA correctly.
> Why the post-synthesis registers present 'X' and "XX.." state?



Article: 49896
Subject: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
From: "wallytempe" <wallytempe@earthlink.net>
Date: Sun, 24 Nov 2002 14:13:12 GMT
Links: << >>  << T >>  << A >>
The main difference between functional simulation and post timing simulation
is that the no timing check are done at functional.  In timing simulation
the setup and hold times of devices are checked and violation are reported,
outputs go to 'X'.  The problem with simulators is that unlike the real
world the simulator does not recover, if the input to a FF is an X the ouput
goes to an X after the next clock and simply propagates through out your
system.

It is very important that the test testbench and logic use a RESET.  Another
problem is that in testbench writting it is typical to somthing like this.

if rising_edge(clk) then
    d <= input;
end if;

The problem is that now the clock and input change at exactly the same time
if your FF does not have zero hold time the you violate hold time,  and many
newer devices are requireing a hold time.  You can rewrite the above
expression like this.

constant thold : time := 2 ns;



if rising_edge(clk) then
    d <= input after thold;
end if;


Hope this helps you out.

Walt


"Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message
news:d22f039b.0211231122.48ff914f@posting.google.com...
> I apply the same testbench to simulate pre-synthesys(function) and
> post-synthesis(timming) top-design. Function simulation result is
> correct. But timming simulation exists unknow result, that is the
> value of many register outputs fall into 'X' or "XX..." over the whole
> simulation time range.  The code has work function on FPGA correctly.
> Why the post-synthesis registers present 'X' and "XX.." state?



Article: 49897
Subject: Re: What's the matter with "clock skew and data delay"?
From: wangmanxi@yahoo.com (siriuswmx)
Date: 24 Nov 2002 07:31:28 -0800
Links: << >>  << T >>  << A >>
Thank you for your reply.
To assign the clock to a global clock is absolutely a good approach to
resolve my puzzle, however i have no other higher clock in my design
to synchronize them , and i find out that the errors in the report
don't have influence on some of my design's functions. I want to put
some registers into the embedded system block (ESB) and make the RAM
function synchronous to avoid these errors, can it works?
By the way, can you tell how to fill with blank of tsu,tco,th,tpd in
the timing setting in QUARTUS .?

"Subroto Datta" <sdatta@altera.com> wrote in message news:<DMXD9.1201$h11.359@newssvr19.news.prodigy.com>...
> Timing Analysis using Quartus is covered in detail in the following
> Application Note:
> 
> http://www.altera.com/literature/an/an123.pdf
> 
> Typically when conditions like this occur, it is an indication that there
> are setup or hold time violations. One way of minimizing clock skew is to
> assign the clock to a global clock.
> 
> - Subroto Datta
> 
> "siriuswmx" <wangmanxi@yahoo.com> wrote in message
> news:4528663b.0211231852.33ba9a8f@posting.google.com...
> > hi,all
> >    i am a newer to fpga, and i am using QUARTUS to target
> > EP20k200rc240-3v.
> >    the problem is that: when i complied the project the complication
> > report always gave me the message "Circuit may not operate. 12017
> > non-operational path(s) clocked by clock gclk have clock skew larger
> > than the data delay. See the Compilation Report for details."
> >   can you tell me what's the matter with "clock skew and data delay"?
> >  thanks a lot!

Article: 49898
Subject: Re: What's the matter with "clock skew and data delay"?
From: wangmanxi@yahoo.com (siriuswmx)
Date: 24 Nov 2002 07:36:48 -0800
Links: << >>  << T >>  << A >>
thank you for your reply.
Yes, i doubt of the floorplanning ,too. But you know , i am too new to
know how edit the floorplan though i have opened it amng times, can
you give me some advice ?

Kumaran Selvaratnam <selvars@yahoo.com> wrote in message news:<3DE07B15.4020509@yahoo.com>...
> However, I think the problem is that you are not really doing
> anything with the creation of the clock network.
> For FPGAs the clock network is pre-designed during the FPGA fabric 
> design considering the external clock source as the input.
> (correct me if I am wrong)
> I think the mapping software software takes care of the clock network by 
> mapping appropriate logic at certain places to achieve the best results 
> for the pre-existing clock-tree. Therefore, you may have to change the 
> way log blocks are mapped between different clock-tree leaves.
> I think you may get this kind of errors due to poor floorplanning as well.
> Good luck.
> Kumaran
> 
> Subroto Datta wrote:
> 
> > Timing Analysis using Quartus is covered in detail in the following
> > Application Note:
> > 
> > http://www.altera.com/literature/an/an123.pdf
> > 
> > Typically when conditions like this occur, it is an indication that there
> > are setup or hold time violations. One way of minimizing clock skew is to
> > assign the clock to a global clock.
> > 
> > - Subroto Datta
> >

Article: 49899
Subject: Re: Global clock routing
From: already5chosen@yahoo.com (Michael S)
Date: 24 Nov 2002 08:03:52 -0800
Links: << >>  << T >>  << A >>
Apart from already mentioned "normal" solution (sample your clocks
with faster global clock, detect edge etc...), I see two other
possible solution for you problem.
1. Assuming your slow clocks a really clocks, i.e. their duty cycle is
not very far from 50% you can insert falling-edge triggered flip-flops
between rising-edge triggered ones. This technique eliminates the
possibility of "clock vs. data" race conditions at cost of reduced
maximum frequency of your (slow) clocks and consumption of twice as
many LCs.
2. Switch to other FPGA architecture. For example, Altera's Stratix.
Stratix has plenty of global and regional clocks.



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