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Athlon all the way!!! but make certain it has a good fan, they like overheating and going pop were PIII and 4's will shut down. Cyber_spook_man Pete Fraser wrote: > We're upgrading a few of our old 800 MHz PIII machines > to speed Xilinx design. > > Has anybody published benchmarks to indicate > if we'd be better of with fast Athlons or Fast P 4s? > > Thanks.Article: 33176
You could use a better synthesis tool. I believe synplicity will infer ROM into block ram, for example. The other option, and the one I prefer, is to do the design hierarchically so that the ROM is its own design file. You have two versions of the rom file, one for each architecture. Each has an identical entity declaration and behavior, but the code underneath is optimized for the specific architecture. To change between the two just change the file name in the compile script. You can also handle other device specific features this way without losing too much to portability. If your design is hierarchical, the top levels are probably just structural netlists anyway, so you change the components that depend on an architecture. Martin Schoeberl wrote: > Hi Ekram, > > Thanks for the sample, but isn't there a way to code this architecture > independent. I would like to use the code for Altera and Xilinx > FPGAs. > > Martin > -- > Whant to see the evolution of a Java processor? > > http://www.jopdesign.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33177
Achlys wrote: > I understand that Xilinx has recalled stock from distributors for > rescreening. Something about metal particle defects shorting routing > channels around BRAM's - this would explain why certain parts work w/ > certain bit files. And why the failures are of the "hard" type - not > intermittent as in a timing related failure. > > Buyer beware, I'd be interested in anyone else's story. > > Thanks Any idea which parts/datecodes ? or who to ask ?Article: 33178
What's the minimum length of an lpm_fifo? I can't seem to find this documented anywhere. I'm using the fifo primarily to create a clean break between two portions of my design, and I don't need it to be very long. I KNOW that if I make it less than 5 it simply won't work (even in simulation). Is there anything else I should know about it? Thanks! Michael Kohne mhkohne@discordia.orgArticle: 33179
Nial Stewart wrote:
>
> I still think the VHDL is simpler. As this is a sub part of a
> design I'll not include the entity or architecture declarations.
> I've included a reset to make it more useful.
Yes :-). The original example had BitP.ar = ENn;, that got lost in the
reply.
> signal count : std_logic_vector(3 downto 0);
>
> (all signals are declared in the architecture defn before the begin
> statement).
>
> process(clk)
> begin
> if(rising_edge(clk)) then
> if(rst = '1') then
> count <= "0000";
> elsif(count /= "1111") then
> count <= count + 1;
> end if;
> end if;
> end process;
Yes, clear enough. ( rst is Sync, not async, but that's a detail )
However, now can you tell me:
- exactly what resource this will use in a CPLD ?
- How many product terms will this require ?
- Can this be buried in a macrocell ?
- CUPL allows the use Foldback, for Speed/PT reduction
this way
PINNODE 45 = BitPneq16;
PROPERTY ATMEL {FOLD=BitPneq16};
BitPneq16 = !(BitP : 'b'1111);
Any pointers on how to do this in VHDL ?
A glance at the cupl source shows it will use one foldback, and needs
one PT per .D, and one PT per .CE - absolute, and completely VHDL vendor
independant.
It's a bit like High Level Assembler and Java. Both have their uses...
-jg
Article: 33180Pete Fraser wrote: > We're upgrading a few of our old 800 MHz PIII machines > to speed Xilinx design. > > Has anybody published benchmarks to indicate > if we'd be better of with fast Athlons or Fast P 4s? > > Thanks. Two data points: Upgrading a 450-PII -> 600-PIII with the same motherboard reduced a PAR that was taking 61 min by a princely 5 min i.e. down to 56 min. Upgrading the PIII to a 1.3GHz DDR266 Athlon took the PAR time down to 36 min, a 60% improvement. My conclusion from this small sample is that the P&R tool speed is dominated by memory performance.Article: 33181
If you want the node terms to be visible even in a timing simulation, you can always recast the terms as LCELLs rather than NODEs. This has a downside risk of adding additional combinatorial delay, which will skew the logic timing. On the other hand, it sometimes improves timing and/or mapping density. Just my $.02 (US). -- Bob Elkind, eteam fpga/design consulting Russell Shaw wrote: > Hi all, > > With this bit of code: > > SUBDESIGN Test( > Ain: input; > Dout: output; > ) > > variable > link: node; > > BEGIN > link=Ain; > Dout=link; > END; > > After i compiled it and load the nodes into the waveform editor, > buried nodes such as 'link' aren't there. On bigger designs, lots > of buried nodes aren't there. How do i get them too? > > -- > ___ ___ > / /\ / /\ > / /__\ / /\/\ > /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ > \ \ / Victoria, Australia, Down-Under \ \/\/ > \__\/ \__\/Article: 33182
Michael Kohne wrote: > > What's the minimum length of an lpm_fifo? I can't seem to find this > documented anywhere. I'm using the fifo primarily to create a clean > break between two portions of my design, and I don't need it to be > very long. I KNOW that if I make it less than 5 it simply won't work > (even in simulation). Is there anything else I should know about it? http://www.edif.org/lpmweb/documentation/docu_index.html http://www.edif.org/lpmweb/more/vhdl.htm --Mike TreselerArticle: 33183
Austin, this is (in my own opinion) unworthy and uncharacteristic of you. My comments are below, in context... -- Bob Elkind, the eteam: fpga/design consulting Austin Lesea wrote: > thomas, > > My own highly biased opinion: > > You will be very, very alone. It will be quiet. Maybe too quiet. Now what the heck does this mean? FUD spreading? Please! > Wake up. Look at the support Xilinx has for its users! Hmmm, are you saying Altera doesn't have decent support also? > Not just the > features (although again, I feel we are now three generations ahead > there, too). Neither the 2XCS30 nor the 1K30 are the "feature rich" glam parts. These are the cost/performance devices for both companies. > Use the hotline (or if a student, use the university support system -- a > hotline just for students alone via email). > > As for HDL's: don't learn a non-standard language, learn verilog or > VHDL. I have many here who are "schematic-saurs" ( I am one as well!) > and they (me) have all now taken a verilog classes. You may still do > schematics with our tools, it is just that it gets so hard to keep track > of the millions of gates in the larger designs. Barring a teeny design, I would tend to ignore the schematic option. AHDL is *so* easy to use, any advantage schematic entry may have is quickly overcome by the efficiencies of HDL editing (specifically AHDL). > Something like 95% of all new designs are in HDL's. Want a job? -- > learn the HDL's, and not the non-standard one! Very good point. If the object of the exercise to to bootstrap into the professional/commercial world of ASIC/FPGA design, then VHDL or Verilogs are *the* standard languages. If the object of the exercise is to get the design done quickly so the larger problem (system and/or board design) can be addressed, then learning and designing with AHDL (Altera proprietary) is going to be much less problematic than learning VHDL and/or Verilogs for a one-time foray into FPGA design. > Austin Lesea > Principal Engineer > ICDES > APG > Xilinx > > thomas daehler wrote: > > > Hello > > > > As a newbie, who has to decide between these devices, > > I found the following differencies: > > Altera advantages: > > -Better design tool (allows schematic entry) > > -Chips are mask programmable (by third party) > > Xilinx advantages: > > -Cheaper boot proms > > > > Has anyone compared these two devices and can give me > > further hints about advantages / disadvantages? > > The amount of RAM and Logic blocks, the pricing and even > > the archictecture seem to be almost the same for both devices. > > Is that right? > > > > ThomasArticle: 33184
Thomas Device Stats: ACEX 1K30: 1,728 LUT/FF elements, 6x4K RAM bits Spartan 2 XC2S30: 864 LUT/FF elements, 6x4K RAM bits Note that Spartan Device can trade LUTs for RAM at a 1 LUT to 16 bits of RAM ratio. Packages: ACEX 1K30: 144pin TQFP (102 user I/O), 208 pin PQFP (147), 256 pin 1-mm BGA (171). Spartan 2 XC2S30: 100 pin TQFP (60), 144pin TQFP (92). (Coming soon: 208 pin PQFP (132) and 144 pin 0.8 mm BGA (92)). Tools: Base tools are free from both Xilinx and Altera. Altera includes Synopsys FPGA Express and Exemplar's Leonardo Spectrum for Synthesis (useful if you' re planning on using an HDL). There are several differences between the tools at a low level, but the new designer will probably not have the need to get into the tools that deep. For most designs, the tools are equally capable. Support: For a new designer, one of the biggest factors in your decision should be who supports you the best. Try both hotline numbers (available off the web sites) or even give your local Altera/Xilinx FAE a call (note that the distributors - Avnet & Arrow - have FAEs available as well). Unfortunately, it's usually pretty hard to determine who's going to give you the best support until you actually need it. Final notes: The Altera/Xilinx debate is something like arguing religion. Some people get really worked up over it. I hope that today's announcement that Xilinx and Altera have agreed to stop suing each other for at least the next 5 years will foreshadow a return to calmer discussions about the true technical merits and shortcomings of each of the architectures. -Pete- thomas daehler <thomas.daehler@beb.ch> wrote in message news:3B557BD0.3C042F84@beb.ch... > Hello > > As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) > -Chips are mask programmable (by third party) > Xilinx advantages: > -Cheaper boot proms > > Has anyone compared these two devices and can give me > further hints about advantages / disadvantages? > The amount of RAM and Logic blocks, the pricing and even > the archictecture seem to be almost the same for both devices. > Is that right? > > Thomas > >Article: 33185
Comments below: thomas daehler wrote: > Hello > > As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) > -Chips are mask programmable (by third party) There are 3rd party vendors for mask-programmed ASICs that will translate either Altera or Xilinx designs. This is *not* an Altera-specific attribute! Warnings for migration to mask-programmed devices: 1. Don't use anything fancy (e.g. PLL/DLLs, large embedded RAMs, etc.) if you want to maximise your mask-program migration options. 2. Don't use Altera LPMs if you want to migrate to mask-programmed devices. Altera's LPMs are "copyrighted" (or some equivalent), and 3rd party vendors will balk at translating them. Use of LPMs is switch selectable, so this shouldn't be a huge problem. 3. Stick to straight single-clock synchronous design. On the other hand, both FPGAs you mention are pretty darn cheap. You'd have to build a boatload of boards to justify the hassle/NREt/risk of mask-programmed devices. If 50K quantity is a real possibility, then sanity check the mask program option by first quoting 50K pricing from Altera and Xilinx (for FPGAs and PROMs). This will make the mask-program option justification point even further out. > Xilinx advantages: > -Cheaper boot proms Last time I looked, the ISP (re-programmable, In-System Programmable) boot PROMs were expensive (~$22) for either A or X (or Atmel). > Has anyone compared these two devices and can give me > further hints about advantages / disadvantages? > The amount of RAM and Logic blocks, the pricing and even > the archictecture seem to be almost the same for both devices. > Is that right? > > Thomas -- Bob Elkind, the eteam: fpga/design consultingArticle: 33186
Jon, Speaking from my experience of designing (commercial) avionics for several years (although not in the last three or so), here's what I know about FPGAs and the FAA and airframe manufacturers. The FAA doesn't like FPGAs in level A or even level B avionics boxes. Actel does a great bit of their business in these types of products because their OTP anti-fuse parts are not susceptable to SEU (Single Event Upsets - high-energy cosmic particles that can cause an SRAM memory or configuration cell to switch states). Redundancy and run-time testing can address some of the concerns, but all-in-all, the FAA and Boeing and Airbus and the many Regional/Business airframe mfgrs are uncomfortable with FPGAs in flight-critical applications. Xilinx has it's Q-PRO parts which are only good in cost-is-no-issue designs (they're mighty expensive). Altera has a Hardcopy solution that takes your FPGA design and converts it into a ASIC-like solution that is non-SEU susceptable, but you need to buy 5000 or more (depending on size) and pay an NRE in the $100,000 - $200,000 range. I know of no flight-critical box that has been certified on a commercial, regional, or business aircraft with an FPGA's reliability guarenteed by reading-back the configuration. My experience is only with one of the two big US avionics mfgrs and one of the tier-two mfgrs, but I would be very interested in hearing of a counter-example (for non-military, commercial projects). Maybe someone currently at Honeywell or Rockwell Collins would have some info on the latest thoughts on this subject. -Pete- Jon Harrison <jon.harrison@gecm.com> wrote in message news:3b5575d0@pull.gecm.com... > Hi, > > We are starting out on a new design for an airborne application, which will > employ a large numer of Virtex-E/II FPGAs. The issue of safety > classification has raised it's head, and whether the volatility of SRAM > FPGAs constitutes an intrinsic hazard. Conventionaly with SRAM devices which > hold program information in microprocessor based systems this is addressed > by the use of continuous memory testing and checksumming. > > Has anyone else crossed this thorny issue yet ? Guidance as to any > procedures / processes followed would be useful. > > We would propose to address this issue by using device readback to allow > checksumming of the configuration data - has this been found to be > acceptable eleswhere ? > > Cheers, > > Jon > > >Article: 33187
bob elkind wrote: > Hmmm, are you saying Altera doesn't have decent support also? I've dealt with support from both, and I can honestly say (And if you search the archives, you'll find I've said it before) that Xilinx's support, while not perfect, sets a standard the others should strive to achieve. I can't say the same for Altera's. > > > > Not just the > > features (although again, I feel we are now three generations ahead > > there, too). > > Neither the 2XCS30 nor the 1K30 are the "feature rich" glam parts. > These are the cost/performance devices for both companies. The XC2S30 has all the features of the virtex device, including clock DLLs and memory. Compared to VirtexE, it's major differences are that it is missing the extra i/o standards, has 4 instead of 8 DLLs, and has a limited selection of packages. It is also faster than the slowest speed grade virtex part. Not too shabby for not being the "feature rich glam part". > Barring a teeny design, I would tend to ignore the schematic option. > AHDL is *so* easy to use, any advantage schematic entry may have > is quickly overcome by the efficiencies of HDL editing (specifically > AHDL). > If someone is trying to learn how to design in FPGAs, I _strongly_ encourage them to do their first few designs in schematics. This forces them closer to the underlying architecture, and there is less temptation to code it like software. Once you learn how to design to the FPGA, then learn the HDL and figure out how to make it produce the hardware you envision. HDLs give you alot of power for parameterizing code, simulation and archiving, but they also make it very easy to abstract yourself into one of those "feature rich glam parts" where one of the cheap low end ones would have done fine. For a one time project, it also avoids learning both FPGA design and HDLs at the same time. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33188
bob elkind wrote: > > Barring a teeny design, I would tend to ignore the schematic option. > AHDL is *so* easy to use, any advantage schematic entry may have > is quickly overcome by the efficiencies of HDL editing (specifically > AHDL). > > > Something like 95% of all new designs are in HDL's. Want a job? -- > > learn the HDL's, and not the non-standard one! > > Very good point. If the object of the exercise to to bootstrap into > the professional/commercial world of ASIC/FPGA design, then VHDL > or Verilogs are *the* standard languages. If the object of the exercise > is to get the design done quickly so the larger problem (system and/or > board design) can be addressed, then learning and designing with AHDL > (Altera proprietary) is going to be much less problematic than learning > VHDL and/or Verilogs for a one-time foray into FPGA design. I learnt most of AHDL and put it to use in a weekend, thanks to a decent help system in maxplus2.Article: 33189
On Wed, 18 Jul 2001 15:23:20 -0700, Mike Treseler <mike.treseler@flukenetworks.com> wrote: >Michael Kohne wrote: >> >> What's the minimum length of an lpm_fifo? I can't seem to find this >> documented anywhere. I'm using the fifo primarily to create a clean >> break between two portions of my design, and I don't need it to be >> very long. I KNOW that if I make it less than 5 it simply won't work >> (even in simulation). Is there anything else I should know about it? > > >http://www.edif.org/lpmweb/documentation/docu_index.html > >http://www.edif.org/lpmweb/more/vhdl.htm > > > --Mike Treseler Hmm. My statement was not clear - is there anything else I should know about the LPM_NUMWORDS parameter? There is nothing in the edif documentation about lower limits on LPM_NUMWORDS. I had to figure that 5 was the lowest 'working' value by experimentation. Note: My target is an Altera FLEX 10K250 part, and I'm using Max +Plus II version 10.0 for development. Thanks!Article: 33190
Have you looked at the library source in the maxplus2 directory? You could simulate a simple design just with that component and see what happens... Michael Kohne wrote: > > What's the minimum length of an lpm_fifo? I can't seem to find this > documented anywhere. I'm using the fifo primarily to create a clean > break between two portions of my design, and I don't need it to be > very long. I KNOW that if I make it less than 5 it simply won't work > (even in simulation). Is there anything else I should know about it? > > Thanks! > > Michael Kohne > mhkohne@discordia.org -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33191
How about the other way around? How about a processor with some programmable logic on it? The Triscend E5 Configurable System-on-Chip (CSoC) family devices have an embedded accelerated 8051 microcontroller core with on-chip LUT-based programmable logic and SRAM. The smallest device in the family has about 3,000 gates of programmable logic and 52 free PIO pins while the largest has about 25,000 gates of programmable logic and up to 252 free PIO pins. The Triscend A7 is similar but has an embedded ARM7TDMI 32-bit RISC processor. Both families are supported by schematic capture and logic synthesis tools. The processor portion of the CSoC device is supported by industry-standard development tools for the specific architecture (i.e., Keil for the 8051, ARM for the ARM7TDMI, etc.). For both families, the CPU and the processor subsystem are pre-implemented, fully tested, and guaranteed to operate at speed. No additional design effort is required to implemented the processor. The smallest E5 device is single-digit U.S. dollars in volume. Triscend E5 CSoC Family http://www.triscend.com/products/indexe5.html Triscend A7 CSoC Family http://www.triscend.com/products/indexA7.html Steven Knapp sknapp@triscend.com www.triscend.com xyz1625us@yahoo.com (John Smith) wrote in message news:<8c835672.0107170405.224a2753@posting.google.com>... > I'm looking for a small processor core that fit in a 'cheap' fpga > leaving some space for IO. > Free or for little cost preferred. > > Thanks > JohnArticle: 33192
Nial Stewart wrote:
>
> I still think the VHDL is simpler. As this is a sub part of a
> design I'll not include the entity or architecture declarations.
> I've included a reset to make it more useful.
>
> signal count : std_logic_vector(3 downto 0);
>
> (all signals are declared in the architecture defn before the begin
> statement).
>
> process(clk)
> begin
> if(rising_edge(clk)) then
> if(rst = '1') then
> count <= "0000";
> elsif(count /= "1111") then
> count <= count + 1;
> end if;
> end if;
> end process;
>
> Nial.
Hmm. How about this one (with a reset):
SUBDESIGN Sat_cntr(
CLK,RST: input;
Dout[3..0]: output;
)
variable
cntr[3..0]: DFF;
BEGIN
cntr[].clk=CLK&!(cntr[]==H"f");
if(RST)
then
cntr[]=0;
else
cntr[]=cntr[]+1;
end if;
Dout[]=cntr[];
END;
--Russell
Article: 33193
Russell Shaw wrote:
>
> Nial Stewart wrote:
> >
> > I still think the VHDL is simpler. As this is a sub part of a
> > design I'll not include the entity or architecture declarations.
> > I've included a reset to make it more useful.
> >
> > signal count : std_logic_vector(3 downto 0);
> >
> > (all signals are declared in the architecture defn before the begin
> > statement).
> >
> > process(clk)
> > begin
> > if(rising_edge(clk)) then
> > if(rst = '1') then
> > count <= "0000";
> > elsif(count /= "1111") then
> > count <= count + 1;
> > end if;
> > end if;
> > end process;
> >
> > Nial.
>
> Hmm. How about this one (with a reset):
>
> SUBDESIGN Sat_cntr(
> CLK,RST: input;
> Dout[3..0]: output;
> )
>
> variable
> cntr[3..0]: DFF;
>
> BEGIN
> cntr[].clk=CLK&!(cntr[]==H"f");
> if(RST)
> then
> cntr[]=0;
> else
> cntr[]=cntr[]+1;
> end if;
>
> Dout[]=cntr[];
> END;
>
> --Russell
While I have not used HDL's would that not be in C like code
if(reset == active) reg = 0;
else { if(edge(clock) reg = reg++ ;}
--
"We do not inherit our time on this planet from our parents...
We borrow it from our children."
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
Article: 33194
Ben Franchuk wrote:
>
> Russell Shaw wrote:
> >
> > Hmm. How about this one (with a reset):
> >
> > SUBDESIGN Sat_cntr(
> > CLK,RST: input;
> > Dout[3..0]: output;
> > )
> >
> > variable
> > cntr[3..0]: DFF;
> >
> > BEGIN
> > cntr[].clk=CLK&!(cntr[]==H"f");
> > if(RST)
> > then
> > cntr[]=0;
> > else
> > cntr[]=cntr[]+1;
> > end if;
> >
> > Dout[]=cntr[];
> > END;
> >
> > --Russell
>
> While I have not used HDL's would that not be in C like code
> if(reset == active) reg = 0;
> else { if(edge(clock) reg = reg++ ;}
Yes, except i think that there's a mistake (in mine). When the
counter is incrementing, you can reset it. However, after the
counter has saturated, you can't reset it because you can't
load the counter with zero because the clock has been gated off!
Maybe something like:
SUBDESIGN test(
CLK,RST: input;
Dout[3..0]: output;
)
variable
cntr[3..0]: DFF;
BEGIN
cntr[].clk=CLK&!(cntr[]==H"f");
cntr[].clrn=!RST;
cntr[]=cntr[]+1;
Dout[]=cntr[];
END;
or like:
SUBDESIGN test(
CLK,RST: input;
Dout[3..0]: output;
)
variable
cntr[3..0]: DFF;
BEGIN
cntr[].clk=CLK;
if(RST)
then
cntr[]=0;
elseif(cntr[]!=H"f")
then
cntr[]=cntr[]+1;
else
cntr[]=cntr[];
end if;
Dout[]=cntr[];
END;
Anyone have a verilog example?
--Russell
Article: 33195Hi Does anyone know if there is a VHDL core available to interface a FPGA with a SmartMedia memory card? Is is possible to do this? Do you get an interface IC that will make the SmartMedia card look like RAM? Thanks AndrewArticle: 33196
Ben Franchuk wrote:
>
> Russell Shaw wrote:
> >
> > Nial Stewart wrote:
> > >
> > > I still think the VHDL is simpler. As this is a sub part of a
> > > design I'll not include the entity or architecture declarations.
> > > I've included a reset to make it more useful.
> > >
> > > signal count : std_logic_vector(3 downto 0);
> > >
> > > (all signals are declared in the architecture defn before the begin
> > > statement).
> > >
> > > process(clk)
> > > begin
> > > if(rising_edge(clk)) then
> > > if(rst = '1') then
> > > count <= "0000";
> > > elsif(count /= "1111") then
> > > count <= count + 1;
> > > end if;
> > > end if;
> > > end process;
> > >
> > > Nial.
> >
> > Hmm. How about this one (with a reset):
> >
> > SUBDESIGN Sat_cntr(
> > CLK,RST: input;
> > Dout[3..0]: output;
> > )
> >
> > variable
> > cntr[3..0]: DFF;
> >
> > BEGIN
> > cntr[].clk=CLK&!(cntr[]==H"f");
> > if(RST)
> > then
> > cntr[]=0;
> > else
> > cntr[]=cntr[]+1;
> > end if;
> >
> > Dout[]=cntr[];
> > END;
> >
> > --Russell
>
> While I have not used HDL's would that not be in C like code
> if(reset == active) reg = 0;
> else { if(edge(clock) reg = reg++ ;}
>
you forgot the saturation :)
but in verilog something like
module satcnt (clk, rst,cnt);
input clk,rst;
output [3:0] cnt;
reg [3:0] cnt;
always@(posedge clk or posedge rst)
begin
if(rst) cnt <= 4'b0000;
else if(cnt != 4'b1111) cnt <= cnt + 4'b0001;
end
endmodule
-Lasse
-- Lasse Langwadt Christensen,
-- A Dane in Phoenix, Arizona
Article: 33197Ray Andraka wrote: > > You could use a better synthesis tool. I believe synplicity will infer > ROM into block ram, for example. > > The other option, and the one I prefer, is to do the design hierarchically > so that the ROM is its own design file. You have two versions of the rom > file, one for each architecture. Each has an identical entity declaration > and behavior, but the code underneath is optimized for the specific > architecture. To change between the two just change the file name in the > compile script. You can also handle other device specific features this > way without losing too much to portability. If your design is > hierarchical, the top levels are probably just structural netlists anyway, > so you change the components that depend on an architecture. > yep , or use a simple model for simulation etc, since block ram is registered, I guess it's not always possible to infer blockram, unless there's an intput/output register and the synthesizer is smart enough to find it and move it into the blockram -Lasse -- Lasse Langwadt Christensen, -- A Dane in Phoenix, ArizonaArticle: 33198
Hi, I have to interface an 30 meters cable which is a simple cable. It is used to transfert video data from a CCD, it is LVDS, the max rate is 40 Mhz. I have to design the reception card, which is in fact the real time video treatment card. I have an Apex 400EFC672-2x on it, so I'd like to use it to acquire the data directly from the cable. The fact is that signal at my side of the cable are very perturbed, I don't know exactly what they look like but I was told there is a lot of, skew, jitter, and voltages are disturbed. The clock is also transmitted on the cable in LVDS protocol and I have to get the FPGA's clock out of it. My question is : Are the APEX's LVDS I/O directly compatible with such signals ? The main problem is the common mode which seems to be to small. Does anyone has already done such a thing ? Thanks. Stephane.Article: 33199
The LPM_FIFO instantiates either "scfifo.tdf" (single clock fifo) or "dcfifo.tdf" (dual clock fifo) from the "...\max2lib\mega_lpm" directory. Both dcfifo and scfifo have checking for the NUMWORDS parameter and the magic limt seems to be 2 words. Everything above two words should work. The following is from the on-line help about the dcfifo. Maybe it explains what you've seen: LPM_NUMWORDS: Number of words stored in memory, which is usually a power of 2. The last three words of the dcfifo may not be available for writing because of the synchronization pipelines between the two Clock schemes. These pipelines are intended to avoid internal metastability. Because of these pipelines, information available to one Clock scheme regarding when reads and writes occur may be temporarily unavailable to the other Clock. The wrfull and rdfull ports of a dcfifo must be raised high slightly before the dcfifo is completely full, in order to avoid overshooting the top of the fifo. This process may cause several words at the end of the fifo to become unavailable. Depending on the rate you are writing to the fifo, the wrfull and rdfull ports may go high with three words remaining, with two words remaining, or with one word remaining in the fifo. However, this process is necessary both to accommodate the clock synchronization and to ensure overshoot does not take place. If you need to maintain a specific number of words, you may want to specify a number for the LPM_NUMWORDS parameter that is up to three words greater than the amount you believe is needed. - Wolfgang http://www.elca.de Michael Kohne <mhkohne@discordia.org> wrote in message news:s21cltsqkaivnt10o2gp28399n797sjs0s@4ax.com... > What's the minimum length of an lpm_fifo? I can't seem to find this > documented anywhere. I'm using the fifo primarily to create a clean > break between two portions of my design, and I don't need it to be > very long. I KNOW that if I make it less than 5 it simply won't work > (even in simulation). Is there anything else I should know about it? > > Thanks! > > > Michael Kohne > mhkohne@discordia.org
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