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Messages from 81400

Article: 81400
Subject: Re: FIR choice
From: Ray Andraka <ray@andraka.com>
Date: Tue, 22 Mar 2005 18:30:35 -0500
Links: << >>  << T >>  << A >>

The system clock is usually some integer multiple of the sample (A/D) 
clock.  In order to minimize the hardware, you'll want to run the clock 
as fast as your design will allow so that you can take advantage of 
multiple clocks per sample.  You usually can use the clock managers in 
the FPGA to obtain the multiplied clock.  For multiple channels in a 
single filter, your  clock should be an integer multiple of 
(channels*sample clock).

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 81401
Subject: Re: ML300 Gigabit Ethernet Issues...
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Tue, 22 Mar 2005 23:53:53 +0000 (UTC)
Links: << >>  << T >>  << A >>
The resolution: The ML300 manual lies, and the errata sheet doesn't
seem to exist.  The crystal is 62.5 MHz on later ML300 boards, not 125
MHz.

Paul Hartke told me that there was a change in the board type to have
the 62.5 MHz crystal (to meet the RocketIO recommendations discussed
in the previous post.).

Looking on the crystal itself (component X101) revealed that I had a
newer board with the slower crystal.

Finding that out, and then changing the clocking of the design so

62.5 MHz (really) -> Refclk -> DLL  -> userclk
      				\x2 -> userclk2


And now all is happy, I can send between the board and PC.
-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu

Article: 81402
Subject: Re: Xilinx ISE 7.1 - Can this get any worse?
From: "Subroto Datta" <sdatta@altera.com>
Date: Wed, 23 Mar 2005 02:15:28 GMT
Links: << >>  << T >>  << A >>
Hi Big,

    We'd like to hear your view about how Quartus can be made better for 
your needs.

- Subroto Datta
Altera Corp.

<big_in_russia@yahoo.com> wrote in message 
news:d173f329.0503221256.2054797b@posting.google.com...
> "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> wrote in message 
> news:<Wr-dnbXaVOLeuaLfRVn-ow@rogers.com>...
>>
>> Try out Quartus II.  You can download the free version (called "Web
>> Edition") from our website www.altera.com.  The Quartus GUI is generally
>> pretty easy-to-use and has the look-and-feel of a modern Windows
>> application.
>>
>>
>> Paul Leventis
>> Altera Corp.
>
> Not that I expect any different from the group Altera pusher, but have
> you ever tried ISE???
>
> I can't believe that even you would even suggest Quartus, it is just
> as backwards as the ISE interface! 



Article: 81403
Subject: Re: PowerPC soft-core?
From: "Jan Gray" <jsgray@acm.org>
Date: Wed, 23 Mar 2005 02:53:58 GMT
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> wrote in message 
news:d1pma4$j3m$05$1@news.t-online.com...
> How many slices are needed to implement frequency divider by 2^37 ?
> ANSWER:
> P&R shows 3 slices for V2Pro or 4 slices for S3

Nice one!  The secret lies in understanding
1. Peter Alfke's appnote [direct.xilinx.com/bvdocs/appnotes/xapp210.pdf]
2. "On Arbitrary Cycle n-Bit LFSRs" [www.fpgacpu.org/usenet/lfsrs.html]
3. and the LFSR generator in [fpgacpu.org/xsoc/xsoc-beta-093.zip].

Jan Gray



Article: 81404
Subject: Re: How to readback a BRAM
From: mucikas <noemail@mail.com>
Date: Tue, 22 Mar 2005 21:31:58 -0600
Links: << >>  << T >>  << A >>
And then jaxato@gmail.com wrote:

> My design is microprocessor based, on which 8-bit binary values
> representing a picture are written to some region in my block rams. I
> would like to know if it is possible to extract those value by using a
> program, similar to data2bram, through JTAG out from the FPGA
> 
> Jacques


Article: 81405
Subject: Re: XC3000 non-recoverable lockup problem
From: "lecroy7200" <lecroy7200@chek.com>
Date: Wed, 23 Mar 2005 03:46:36 GMT
Links: << >>  << T >>  << A >>
> The oscillator itself is at a much higher frequency, and is divided down
> to the number listed in the data sheet.  At least, we still do it that
> way, even today.

This is not what the data sheet states.  The 4000 data sheet makes a
distinction that it runs at 8MHz and divides down to the 1MHz where the 3000
is at 1MHz.  I am not disagreeing with you.  I believe that the 3000 was
changed overtime and the clock was part of these changes and now runs at
around 16MHz.  The documents were never updated to reflect this change
because it was "transparrent" to the end user.  Of course this is all a
guess on my part.

> The accuracy of this oscillator would be from 1/2 to 2X the nominal (it
> just isn't critical).

Agree, it just needs to work.  Too bad it seems to have problems.

> Since this part still had paper schematics (REALLY) it is far too old
> for us to go look at its design.

Funny,  we can still pull up our paper documents if needed.  I agree, its
not fun but sometimes you just have to roll up your sleves and dig in.

> Phil is on the right track.
>
> This part did have a brownout issue (if the the voltage dropped just
> right, for just the right amount of time, and came back up) that would
> place it in a locked state that could not be recovered until the power
> was cycled.

Again, I read Xilinx's app. note on the brown out  problem and it makes it
clear that the part can be reset without removing power.  I don't disagree
that the internal logic could get into a locked state and that there was not
a problem with brown out.  I also think it is very possible that the current
devices being sold could have a second problem with the internal oscillator.
There is no mention anywhere about the oscillators failing to start or
locking up in the brown out app. note.  I am sure if Xilinx would have known
this, it would have been documented and the power cycle requirements would
have been called out, which they are not.

> I solved this problem 15 years ago by using a Dallas Semi Power on Reset
> part to reset the power supply if it detected a glitch.

Again, power cycling the device, no matter how it could be done, is not an
option for this system.

It sounds like Xilinx is not willing to dig into the root problem of the
oscillator.  I can understand this to some degree.  After all the software
has not supported the device in several years.   So my next question is if
you are able to tell me if the oscillator design used in the currently sold
3000s is being used in other Xilinx devices?

















Article: 81406
Subject: Re: XC3000 non-recoverable lockup problem
From: "lecroy7200" <lecroy7200@chek.com>
Date: Wed, 23 Mar 2005 03:52:26 GMT
Links: << >>  << T >>  << A >>

> >
> > Do you recall how low the Vcc had to cycle, in order to correctly
recover ?
>
> As I recall, it had to go below 150 mV to 300 mV to recover.
>
After testing the second failure, I tried the power cycle test again.  The
second part behaved the same as the first.  Removing power from the device
and shorting the supply (much less than 150mV) for over 1mS would not cause
the oscillator to restart (observing it with the spectrum analyzer).









Article: 81407
Subject: Re: Difference between simulation types
From: Jeremy Stringer <jeremy@_NOSPAM_endace.com>
Date: Wed, 23 Mar 2005 16:39:04 +1200
Links: << >>  << T >>  << A >>
Preben Holm wrote:
> can anybody tell me the real difference between
>  - behavior (guess this is pure VHDL)

This is purely behavioral - it literally just simulates what the VHDL 
describes, without any device-specific timing or anything.

>  - post-translate (guess this is after synthethis)
>  - post-map
>  - post place and route (guess this is when the design is "final" and is 
> known where to be put in the FPGA)

Post place-and-route simulates the behavior with timing, after the 
design has been fitted into the device.  I assume that post-map and 
post-translate just have less, or less accurate, information (I don't do 
these type of simulations).

As an example:

foo: process(clk)
begin
	if rising_edge(clk) then
		if rst = '1' then
			dout <= '0';
		else
			dout <= din;
		end if;
	end if;
end process foo;

In a pure behavioral simulation, dout would change exactly on the clock 
edge.  In a post place and route simulation, it wouldn't - it would take 
into account the delay of the flip-flops, and also the routing delay 
from the output to the next input - this might be, say, 5 ns later.

Jeremy

Article: 81408
Subject: Re: Xilinx ISE 7.1 - Can this get any worse?
From: "John Retta" <jretta@rtc-inc.com>
Date: Wed, 23 Mar 2005 06:24:02 GMT
Links: << >>  << T >>  << A >>
I agree with script based design flow.  In fact, once you have
tried it, you will never ... ever ... go back to gui.  The backend
Xilinx flow (ngdbuild ... map .... par .... bitgen) have not changed
in years.  Individual tool options have obviously to match new
architectures.

In a shameless plug of my website, I have a dos based script
avaiable for download.  It accepts command line two command
line options ... name of the base design.edf and the revision
number.  It uses the revision number as an appendix for
final output of filename, and pretty importantly, uses to fill
in the user ID as a bitgen option.  This is a quick way of
scanning a device chain an determining revision levels of
on board devices.

Key point though is that these script based approach defines
the design flow and synthesis parameters in a way which is
absolutely portable and self-documenting, are frees user
from the vagaries of GUI releases.

-- 
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

A Colorado based Xilinx design consultant.

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


"Rudolf Usselmann" <russelmann@hotmail.com> wrote in message
news:d1pai3$3vb$1@nobel.pacific.net.sg...
>
>
> I too dislike the user interfaces of todays leading FPGA
> providers. I don't think that either A or X have a useful
> or productive tool.
>
> BUT, what works for me very well, is to understand the flow,
> and use makefiles and scripts to drive the command line tools.
> I have been very successful with this method. My development
> cycle looks like this: 1) create a deign in verilog (including
> verification); 2) edit ucf file; 3) run my script to create a
> bit file from my rtl; 4) bring up FPGA.
>
> Once in a blue moon I still start up xps (EDK) to configure
> an SoC. But I usually just use the tools for the basic build,
> and than manually edit the appropriate configuration files,
> and rerun gmake ...
>
> Cheers,
> rudi
> =============================================================
> Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
> Your Partner for IP Cores, Design, Verification and Synthesis



Article: 81409
Subject: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 23 Mar 2005 07:32:51 +0100
Links: << >>  << T >>  << A >>
Hi

below is possible the most dense divide by 2^n ever implemented on any FPGA:
divide by 2^37 takes only 3 Virtex Slices! (4 slices on spartan-3)

Antti



--
-- http://gforge.openchip.org/projects/xilcores/
--
-- Divide by 2^n, n=21..37, code=0000 n=37, code=1111 n=21
-- Theory of operation:
-- bit serial NCO with 32 bit phase accumulator (2 LUT's as SRL16),
-- phase increment is fixed constant "..0001" (2LUT's as SRL16)
-- 1 LUT for 1 bit adder, 1 LUT for carry logic,
-- 1 flip-flop for carry, 1 flip-flop for 1 bit serial to parallel
conversion
-- total: 3 Slices (4 for Spartan3)
-- the bit serial auto divides the incoming clock by 2^5 that is the
frequency
-- for the NCO to operate, the phase accumulator gets overflow in 2^32 so
the
-- maximum divide constant is 2^37
-- :)
-- antti@openchip.org

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity div_2n_21_37 is Port (
clk : in std_logic;
code : in std_logic_vector(3 downto 0);
fout : out std_logic);
end div_2n_21_37;

architecture Behavioral of div_2n_21_37 is
signal one_L: std_logic;
signal one_H: std_logic;
signal one_X: std_logic;
signal accu_L: std_logic;
signal accu_in: std_logic;
signal accu_out: std_logic;
signal cy_out: std_logic;
signal cy_in: std_logic;

begin
-- rotating 1, 32 bit long
Instance_SRL16_1L: SRLC16E generic map (INIT => X"0001")
port map (CLK => clk, CE => '1', A0 => code(0), A1 => code(1), A2 =>
code(2), A3 => code(3), Q => one_X, D => one_H, Q15 => one_L);
Instance_SRL16_1H: SRLC16E generic map (INIT => X"0000")
port map (CLK => clk, CE => '1', A0 => '1', A1 => '1', A2 => '1', A3 => '1',
Q => one_H, D => one_L, Q15 => open);
-- rotating ACCU, 32 bit long
Instance_SRL16_AL: SRLC16E generic map (INIT => X"0000")
port map (CLK => clk, CE => '1', A0 => '0', A1 => '0', A2 => '0', A3 => '0',
Q => open, D => accu_in, Q15 => accu_L);
Instance_SRL16_AH: SRLC16E generic map (INIT => X"0000")
port map (CLK => clk, CE => '1', A0 => '0', A1 => '0', A2 => '0', A3 => '0',
Q => open, D => accu_L, Q15 => accu_out);
-- ALU add 1 with Carry, only when not 1
accu_in <= one_H xor accu_out xor (cy_out and not one_H);
-- Carry Logic
cy_in <= (one_H and accu_out) or (accu_out and cy_in);
-- Carry flip flop
Instance_Carry: FDR port map(Q => cy_out, C => clk, D => cy_in, R => '0');
-- 1 bit serial to parallel converter
Instance_fout: FDRE port map(Q => fout, C => clk, CE=> one_X, D => accu_out,
R => '0');
end Behavioral;




Article: 81410
Subject: Chipscope and Virtex4 LX25 ES
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 23 Mar 2005 16:42:55 +1000
Links: << >>  << T >>  << A >>
Hi,

Xilinx solution 20060 refers to the issue with the Virtex 4 LX25 ES 
parts and the JTAG chains, with workarounds for the EDK's XMD and 
opb_mdm tools.  However, this silicon bug also affects ChipScope Pro, 
but no solution is offered.

We are considering prototyping a large project on the ML401 (which uses 
V4-LX25 ES parts), but ChipScope support will be essential.  Does 
anybody have some good news for me that there is, or soon will be, a 
workaround for this?

Thanks,

John

Article: 81411
Subject: Re: Chipscope and Virtex4 LX25 ES
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 23 Mar 2005 07:44:25 +0100
Links: << >>  << T >>  << A >>
ChipScope works actually with LX25-ES
but you can not use MDM and Chipscope in the same design thats the
limitation
also on our board (memec LX25) Chipscope is not able to download the
bitstream
so the bitstream has to be loaded with impact, later chipscope would be
useable

Antti
PS I think there will be no complete workaround to get USER2 to work on ES
there was report that USER2 has reset polarity inverted? that is not
completly
dead, so I assume the silicon might allow for a fix, but my strong bet is
that
the USER2 fix for chipscope-mdm will not be offered by Xilinx


"John Williams" <jwilliams@itee.uq.edu.au> schrieb im Newsbeitrag
news:newscache$d8lsdi$pbh$1@lbox.itee.uq.edu.au...
> Hi,
>
> Xilinx solution 20060 refers to the issue with the Virtex 4 LX25 ES
> parts and the JTAG chains, with workarounds for the EDK's XMD and
> opb_mdm tools.  However, this silicon bug also affects ChipScope Pro,
> but no solution is offered.
>
> We are considering prototyping a large project on the ML401 (which uses
> V4-LX25 ES parts), but ChipScope support will be essential.  Does
> anybody have some good news for me that there is, or soon will be, a
> workaround for this?
>
> Thanks,
>
> John



Article: 81412
Subject: Re: PowerPC soft-core?
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 23 Mar 2005 08:00:16 +0100
Links: << >>  << T >>  << A >>

"Jan Gray" <jsgray@acm.org> schrieb im Newsbeitrag
news:aT40e.1546$z.336@newsread2.news.atl.earthlink.net...
> "Antti Lukats" <antti@openchip.org> wrote in message
> news:d1pma4$j3m$05$1@news.t-online.com...
> > How many slices are needed to implement frequency divider by 2^37 ?
> > ANSWER:
> > P&R shows 3 slices for V2Pro or 4 slices for S3
>
> Nice one!  The secret lies in understanding
> 1. Peter Alfke's appnote [direct.xilinx.com/bvdocs/appnotes/xapp210.pdf]
> 2. "On Arbitrary Cycle n-Bit LFSRs" [www.fpgacpu.org/usenet/lfsrs.html]
> 3. and the LFSR generator in [fpgacpu.org/xsoc/xsoc-beta-093.zip].
>
> Jan Gray

Hm... the LFSR is a nice try! Well my bet is that LFSR based approuch
would use at least 1 more slice (possible 2 more slices)...

http://gforge.openchip.org/projects/xilcores/

there is the actual solution :)

Antti



Article: 81413
Subject: Re: PowerPC soft-core?
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 23 Mar 2005 08:01:52 +0100
Links: << >>  << T >>  << A >>
"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag
news:42407bd6$0$28872$91cee783@newsreader01.highway.telekom.at...
> Hi Antti,
>
> > LOL, mercy mercy, :)
> > MicroBlaze is is defenetly more than 672/2 slices !
>
> You could use ERIC5... but it does not really compare to a PowerPC ;-)
>
> >
> > but I think I agree that the rule of thumb is OK!
> >
> > btw Jan I guess you are one of the few who could correctly
> > answer the following FPGA-Quiz question:
> >
> > How many slices are needed to implement frequency divider by 2^37 ?
> >
> > ANSWER:
> > Number of Slices:                       3  out of   1408     0%
> > Number of Slice Flip Flops:             2  out of   2816     0%
> > Number of 4 input LUTs:                 6  out of   2816     0%
> > Number of bonded IOBs:                  1  out of    140     0%
> > Number of GCLKs:                        1  out of     16     6%
> >
> > the above is synthesis report for divide by 2^n, n=21..37
> > P&R shows 3 slices for V2Pro or 4 slices for S3
> >
>
> This makes me curious: Is there other stuff like BRAM
> involved? Otherwise you HAVE to tell us how you do that (I would simply
> claim that this is not possible...)

dont claim things not possible!
there is no BRAM involved and no DSP48 either
a divider can be implemented with 0 slices when using BRAMs :)

http://gforge.openchip.org/projects/xilcores/

> Thomas
>
> www.entner-electronics.com
>
>



Article: 81414
Subject: Re: PowerPC soft-core?
From: "Thomas Entner" <aon.912710880@aon.at>
Date: Wed, 23 Mar 2005 09:00:07 +0100
Links: << >>  << T >>  << A >>

>>
>> This makes me curious: Is there other stuff like BRAM
>> involved? Otherwise you HAVE to tell us how you do that (I would simply
>> claim that this is not possible...)
>
> dont claim things not possible!
> there is no BRAM involved and no DSP48 either
> a divider can be implemented with 0 slices when using BRAMs :)
>
> http://gforge.openchip.org/projects/xilcores/
>
>> Thomas
>>
>> www.entner-electronics.com
>>
>>
>
>

Great stuff!

I forgot about the distributed RAM and SRL16 when I made my claim ;-) but at 
least I realized that myself... I sent a second post, but it did not appear 
in my Outlook Express which I use as news-reader. However, if you look at 
the post of Sylvain, at the very end, you can see that my post as arrived at 
least somewhere. Very strange... Do others see the same behavior of lost 
posts?

Thomas 



Article: 81415
Subject: Re: Spartan 3 to tempsensor interface
From: rgebru@gmail-dot-com.no-spam.invalid (rgebru)
Date: Wed, 23 Mar 2005 02:06:41 -0600
Links: << >>  << T >>  << A >>
Hi

thanks so much for the replies..both the Analog devices and the i2c
interface seem promising... will let you guys know of my progress :)
I haven't started working on it yet.  

To use the temp sensor on the ornado board though wouldn't I have to
use that board? I have to use the Spartan 3 board.. 

Ruth


Article: 81416
Subject: re:changing DDR2 pin LOC on UCF generated by MIG for virtex4
From: lamgh@hotmail-dot-com.no-spam.invalid (lgh)
Date: Wed, 23 Mar 2005 02:06:41 -0600
Links: << >>  << T >>  << A >>
anyone able to help me please ?


Article: 81417
Subject: re:WLAN in VHDL
From: nkavv@skiathos.physics.auth-dot-gr.no-spam.invalid (kavi)
Date: Wed, 23 Mar 2005 02:06:41 -0600
Links: << >>  << T >>  << A >>
This was the main objective of the EASY project
(http://easy.intranet.gr). I think they have made some of the project
deliverables public. 

The topic of this project is to implement a board-level system (lots
of functionalities however on a single-chip) for HIPERLAN/2 protocol.
This was the European initiative for WLAN applications (in contrast to
IEEE 802.11). The language used was VHDL (widely used in Europe).

But no public VHDL codes...

Nikolaos Kavvadias a.k.a. "kavi"


Article: 81418
Subject: nallatech BallySHARC boot JTAG problem
From: dario.gall@gmail.com
Date: 23 Mar 2005 00:09:41 -0800
Links: << >>  << T >>  << A >>
I'm working with Nallatech BallySHARC module and I have a problem to
boot
DSP through JTAG cable because it's done correctly only if I load on
the
FPGA the Nallatech bitstream and not my bitstream...
The error is:
"The processor core is hung at PC:0x3c1040 due to access to external
memory.
Typical causes for this are /HBR = 0, ACK = 0 or the DSP may not be the
current bus master.
If the processor does not clear itself, a software reset may be the
only way to regain control of the processor core." but in this board
the External Bus is dedicated to a bank of SDRAM .
Does anybody help me????Does anybody work with this board????

thank every body...

Dario


Article: 81419
Subject: Re: WLAN in VHDL
From: "Antonio Di Stefano" <write@distefano.at.diepa.unipa.it>
Date: Wed, 23 Mar 2005 09:32:44 +0100
Links: << >>  << T >>  << A >>
"Benjamin Menküc" <benjamin@menkuec.de> ha scritto nel messaggio 
news:d1mrmm$l8n$00$1@news.t-online.com...
> Hi,
>
> I am thinking about implementing a WLAN Interface with a FPGA. Has anybody 
> done this before, or does anybody have some information about this?

We have successfully deigned and implemented an 802.11 MAC in a Xilinx FPGA 
for a research project. It is feasable... but it was not so easy, and 
required a carefull design and a lot of work! :-) (802.11 is a very complex 
protocol to handle...)

Regards,
A.D. 



Article: 81420
Subject: Re: Xilinx backups
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 23 Mar 2005 03:06:44 -0600
Links: << >>  << T >>  << A >>
>What is the best backup procedure for Xilinx?

Good timing.

Use a makefile and your favorite source coutrol system.

See for example, John Retta's recent post:
  Subject: Re: Xilinx ISE 7.1 - Can this get any worse?
  Message-ID: <6Y70e.1797$gI5.682@newsread1.news.pas.earthlink.net>
  Date: Wed, 23 Mar 2005 06:24:02 GMT

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Article: 81421
Subject: Re: XC3000 non-recoverable lockup problem
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 23 Mar 2005 03:10:19 -0600
Links: << >>  << T >>  << A >>
>Just as a reminder, here what Hal Wrote:
>
>>I think there is a combined ~prog and done pin.  It's pulled low
>>(open drain) by the 3000 until it gets configured.  Power up starts
>>needing configutation.  A high-to-low transition on ~prog asks for
>>another configuration cycle.  If your attempted configuration gets
>>confused, there is no way to start over until you finish configuration
>>since ~done is held low so you can't make it go high-to-low.

>>Configuration starts with a 24 bit bit-count value.  After that many
>>configuration clocks, all the devices in the the chain release
>>their done pulldown.  If one of the devices in the chain gets
>>(somehow) a low value in that counter you have to cycle through
>>2**24 cycles to wrap around and finish the current cycle.

My memory if very fuzzy.  I think the Reset pin would break
out of that mess.  The catch was that the system we were working
on didn't have a way for the CPU that was supplying the bits
to flap Reset.

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Article: 81422
Subject: Re: clock division using DCM, how?
From: "Marc Randolph" <mrand@my-deja.com>
Date: 23 Mar 2005 04:47:55 -0800
Links: << >>  << T >>  << A >>
Vladislav Muravin wrote:

> From what i understand, you are manually dividing the clock by 4.
> there is nothing wrong with this. Xilinx tool automatically
identifies the
> clock signals, and tries assigning them a dedicated clock line.
> you can see it in the report of XST.

Howdy Vladislav,

His XST report confirms that the tools do not automaticly put manually
derived clocks on global clock nets.

> What you need to do is to tell Xilinx tool that the clock generated
by
> division is 25 MHz.
> Constraints! Otherwise, it would have no idea how to do the
placement.
> However, the use of DCM is not mandatory is you want to only divide
the
> clock by 4.

I haven't studied his design enough to know how much it would benefit
him, but in general, if you want to seemlessly transfer data between
the domains, it is best to generate the main and divided clock from the
same DCM so that they are phase aligned - and even then, depending on
how concerned with jitter you are, you may want to do the transfer
using a rising-falling edge combination.

> But if you have too much, really too much combinational logic, then
even the
> slow clock as 25 MHz will not meet timing.

Agreed, although in a Virtex-2Pro, that would take a huge number of
levels of logic at that speed (to make a WAG: 20 or 30 levels).

Have fun,

   Marc


Article: 81423
Subject: Re: changing DDR2 pin LOC on UCF generated by MIG for virtex4
From: "Marc Randolph" <mrand@my-deja.com>
Date: 23 Mar 2005 04:52:37 -0800
Links: << >>  << T >>  << A >>

lgh wrote:
> Am I allowed to change the pin location on the same bank generated by
> MIG for my virtex4 design ? Would it not be a hassle or restricted if
> I am forced to use the exact pin location for my DDR2 design ? One of
> my Virtex4 eval board has it's own fixed DDR2 pins and I would like
> MIG to follow those pins constraint. Thanks a lot.

Howdy,

I've not used MIG, so I don't know what kind of placement constraint(s)
it places on the design, but I find it a little hard to believe that
you could only use the set of pins that it chooses.  With the
exception, of course, that any clock pins (GCLK and CC_LC/BUFIO pins)
must move to other clock pins.

Good luck,

   Marc


Article: 81424
Subject: Re: Xilinx ISE 7.1 - Can this get any worse?
From: "lecroy7200@chek.com" <lecroy7200@chek.com>
Date: 23 Mar 2005 05:10:58 -0800
Links: << >>  << T >>  << A >>
I am still waiting on the latest ISE to show up so I can't comment.  I
will say that I like the new Quartus software, although I do not use
anything but text entry, so most of my work is done in Multiedit for
both tools.




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