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Hans-Bernhard Broeker wrote: > > In comp.arch.embedded Alex Rast <ad.rast.7@nwnotlink.nospam.com> wrote: > > [...] > > > Because of the design of the board, I need > > to use a synchronous, hardware-based protocol and interface to transfer the > > data. > > "A ... protocol" meaning exactly _what_? I'm quite sure you don't > just need some random protocol. You need a piece of hardware and > software that generates and read _exactly_ that protocol your device > under test uses. Regarding which you completely forgot to tell your > readers what that protocol actually is. From what you wrote, it might > well be some completely non-standard homegrown thing. If so, you're > obviously on your own --- oughtta have thought of that aspect, before > you designed that protocol into your hardware. Now you're stuck with > what you have. > > Odds are you'll have to build your test harness yourself, in this > case. Software alone won't do (not at 10Mhz on an ordinary PC...), > and a test pulse generator inside the budget limit you gave probably > won't be flexible enough for your needs. > > > do is dump bitstreams in either direction, synchronously, > ... synchronous to what? Moral: Don't design hardware without first thinking about testing it. Or at least enough of it :-) I learned that the hard way a long time ago, by building a marvelous device that we could never replicate. Each phase had been driven by a test jig, which was replaced by the next part of the real device. The final had no jigs, and no way to prod it. However I don't think it is quite as bad as you say. Nearly, but not quite. He will need some sort of hardware fifo, with dual ports, and a way of loading it from a pc. He probably also needs the synchronous interface module to unload the fifo, which may be another of his systems. He could start with something that continuously unloads one simple pattern. -- Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net> USE worldnet address!Article: 64926
Actually I shouldn't have called them "posted reads". Posting a transaction
means that the initiator never gets an explicit acknowledgement that the
transaction reached its destination (like posting a letter in the mail). PCI
writes are posted. A PCI read by definition is non-posted because the initiator
must receive an acknowledgement (the read data).
What I should have said was that the PCI-X protocol allows the initiator to
pipeline reads. If you have a copy, the PCI-X spec explains it pretty well.
Here's the short version:
In PCI-X, the target of a transaction can terminate the transaction with a split
response, which tells the initiator that the target will get back to him later
with a completion transaction (data if it's a read). The request is tagged with
a 5-bit number that will come back with the completion so that the initiator can
match completions to outstanding requests. The initiator is allowed to have up
to 32 split requests outstanding in the pipeline at any one time. Each read
request can be for up to 4kB of data. The throughput of a system that takes full
advantage of split transaction is highest when the amount of data being
transferred is large and the latency is small enough that 32 tags can keep the
pipeline full.
In PCI, the target of a read transaction must either respond with data
immediately, or repeatedly terminate the read attempts with retry while he goes
off and fetches the data. Once he's fetched it, he will be able to respond
immediately to the initiator on the initiator's next attempt. This is very
inefficient because there is only one transaction in the pipeline at a time. If
the latency is large (the initiator has to retry many times), the throughput is
much lower than when pipelined reads are used.
If PCI-X mode is available, use it. Or, there may be chipset settings that you
can use to improve PCI mode performance. The chipset may be able to do
pre-fetching of data in anticipation of you reading it. There may also be burst
length settings that allow you to increase the amount of data transferred in a
single transaction. You need to read the specs for the chipset you are using and
figure out what can be tweaked.
Mark
Brannon King wrote:
> For those speed tests the device was in PCI mode. I was assuming it would be
> the same speed as PCIX (at the same bus speed) because the timing diagrams
> all looked compatible between the two. Please explain what you mean by "post
> read requests". Is there some workaround for this to make the PCI mode
> handle this better?
>
>
Article: 64927According to the data sheet, the absolute maximum VCCINT is 1.32 volts. This would be 4% high side tolerence for a 1.25 V regulator. I am not aware of any derating Xilinx has for higher voltages with their Spartan 3 device. I would conclude a 1.25 V regulator would be acceptable. If you were really paranoid you could tweak down the regulator by adjusting the passives in the circuit. "Kolja Sulimma" <news@sulimma.de> wrote in message news:b890a7a.0401160555.6965219c@posting.google.com... > This again is a question for Austin: > > The recommended operating conditions for spartan-3 are VCCINT < 1.26V. > What will happen if I power it with 1.28V? > > Antything more serious than a live expectancy reduced from 20 years to > 15 years? > > You know, there a only a few small 1.2V regulators on the market but > there a plenty of 1.25V versions around. But those have a tolerance of > a few percent... > > Kolja SulimmaArticle: 64928
I was using WebPACK 3.3wp8 long time. One resource hungry project with CPLD XCR3256XL successfully fitted with 3.3wp8 I was not able to fit it under WebPACK 4. All tries failed and I continue to use 3.3wp8. Now I plan to use XC2C3256 (not supported in WebPACK 3.3wp8) in similar project. So I tried WebPACK 6.1.03i (the newest one) with no success with the XCR3256XL. XCR3384XL fitted, but I noticed none of foldback nands were used, although option "–nofbnand" were not used. How to enable the use of the Foldback Nand when fitting the design? File dev.pdf states that this is on by default, but this is not in my case. How correctly declare signal of type foldback nand (I am currently using 'com, keep' for them, but it must be a better way)?Article: 64929
As it seems a valuable response, here is Eric's answer: Hi, In PCI mode, when you try to "read" the host, most hosts will immediately issue retry. However, they have gleaned some valuable information -- the starting address. That is called a "delayed read request". Then, the host goes off and prefetches data from that starting address. How much it prefetches is up to the person that designed the host device. Probably 64 bytes or something small like that. While it is prefetching, if your device retries the read, you'll keep getting retry termination. Time is passing. Eventually, when the host is finished prefetching however much is is going to prefetch, and you return to retry the transaction (for the millionth attempt) it will this time NOT retry you but will give you some data (from one DWORD up to however much it prefetched...) That is called a "delayed read completion". If that satisfied your device, the "transaction" is over. If you actually wanted more data (the host has no idea how much data you wanted, since there are no attributes in PCI mode) your device will get disconnected. Then, your device will start a new "transaction" with a new starting address, and this horrible process repeats. It is terribly inefficient (but supposedly better than having the host insert thousands of wait states, which keeps the bus locked up so everyone else is not getting a turn...) This is replaced by something called split transactions in PCI-X mode, which is more efficient. It is a bit more complicated to explain, though. If you want me to give that a stab, write back and I'll give it a shot tomorrow. Eric "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:4006FF0D.6262552F@xilinx.com... > > Hi, > > > Results: > > Max host write speed: 70MB/s > > Max host read speed: 230MB/s > > > > The timer does not include the memory allocations. > > Any ideas why the write speed is so much slower? > > Would it be the latency parameters in the core? An > > OS issue? > > When you say "write speed" do you refer to your device > becoming bus master and doing memory writes to the > system RAM behind the host bridge? Likewise, by the > term "read speed" do you refer to your device becoming > bus master and doing memory reads of the system RAM > behind the host bridge? > > I just want to make sure I didn't mis-interpret your > question before I try to answer it. Or did I get it > backwards? > > EricArticle: 64930
On 16 Jan 2004 05:21:37 -0800, stevetshannon@yahoo.com (Steve T Shannon) wrote: >Thanks for the advice! My concern isn't the BUFGs so much as it is the >IBUFGs, which seem to be the only way to get a clock-able signal into >the chip. I'm already using them all :( I think I'm going to settle on >decoding the ALE signal externally with a latch, and just having the >entire system be sampled. I've had to move up to the PQ208 Spartan-IIE >(from the TQ144) which is a bit more expensive, but still should work. >Now I just have to tackle the metastability issues. (oh no!) I don't think you need to use an IBUFG if you are not using a BUFG for a clock, i.e. any old general purpose I/O pin will do. (But better to make it one close to where it's need to reduce routing delays inside the FPGA.) Regards, Allan.Article: 64931
VHDL-87 did not allow constants to be connected to ports. VHDL-93 does. Is there a switch that turns VHDL-93 on? To be compliant with the newest VHDL RTL synthesis standard IEEE P1076.6-2003, Xilinx needs to support this. If they don't, the work around is to create a signal, and assign it a value (in the concurrent part of code since often initializations of signals are not supported by synthesis). signal sig_XLXN_12 : std_logic_vector(7 downto 0) ; . . . sig_XLXN_12 <= XLXN_12(7 downto 0) ; Of course, rereading your post, it is curious why the creatino of buffers in your schematic did not do the above. good luck. Cheers, Jim Bob wrote: > I need help in creating constants to be used with schematic capture. > > In previous versions of Xilinx ISE I used to create schematic symbols > for constants (i.e. 0xA5) by creating a schmetic with 8 buffers. The > inputs were connected to gnd or vcc to create the constant. The > outputs of the buffer were connected to a bus CONST(7:0). > > Then I could use this constant anywhere in my schematic by inserting > this part. > > I tried this on the latest ISE 6.1 and got the following error when I > compiled. > > ERROR:Xst:1539 - C:/Projects/DemoTop.vhf line 122: Formal port in > component <const8_80> must be an identifier. > > Here is the DemoTop.vhf output: > > XLXI_30 : const8_80 > port map (Const(7 downto 0)=>XLXN_12(7 downto 0)); > > Why doesn't this work anymore? Is there a better way to create a > constant. I know that Altera has a constant macro. Is there any easy > way in Xilinx. > > Thanks, > > Bob > > P.S. Please post the answer in the newsgroup rather than emailing it. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 64932
I've made an image illustrating a certain optimization that the VHDL/Verilog compilers seem to make, but which the mapper does not seem to make. Can someone explain why this is not done in the mapper? Picture: http://www.starbridgesystems.com/images/brans/or_gates.png The picture shows some linearly cascaded OR gates vs. a binary tree of OR gates. The Xilinx Map/Par seem to have a much easier time with timing constraints when the incoming file is organized binarily, yet it would seem to me that would be an easy optimization for the mapper to perform. What I want to do is use some 3rd-party EDIF generator tools and yet I'm forced to manually tile out my gates binarily. Thoughts?Article: 64933
Brannon,
I find with most of my Xilinx questions I go to support.xilinx.com, the
data sheets and figure it out myself. I have been working with their parts
for years. I also have relationships with local FAE's some of who are
excellent design engineers. I don't like their support over the phone and
have had schedule slips because of it.
Article: 64934All, The voltage drop to the part might be just about 50mV.... Seriously. I would try it an see what voltage the part actually is at relative to the regulator. You might be pleasantly surprised. Remember the part is specified by Xilinx to operate at the abs max voltage AND temperature for the rated lifetime. We prefer you stay within the recommended values, however. Austin fabbl wrote: > According to the data sheet, the absolute maximum VCCINT is 1.32 volts. This > would be 4% high side tolerence for a 1.25 V regulator. I am not aware of > any derating Xilinx has for higher voltages with their Spartan 3 device. I > would conclude a 1.25 V regulator would be acceptable. If you were really > paranoid you could tweak down the regulator by adjusting the passives in the > circuit. > > "Kolja Sulimma" <news@sulimma.de> wrote in message > news:b890a7a.0401160555.6965219c@posting.google.com... > >>This again is a question for Austin: >> >>The recommended operating conditions for spartan-3 are VCCINT < 1.26V. >>What will happen if I power it with 1.28V? >> >>Antything more serious than a live expectancy reduced from 20 years to >>15 years? >> >>You know, there a only a few small 1.2V regulators on the market but >>there a plenty of 1.25V versions around. But those have a tolerance of >>a few percent... >> >>Kolja Sulimma > > >Article: 64935
Hello FPGA users, I am thinking about purchasing the Avnet Virtex-II Pro™ Development Kit and would like to find out if anyone is using it or has used it recently. I want to make sure I am not missing anything. It seems like it comes with all the tools, but I find it difficult to get a straight/consistant answer sometimes from Avnet. My confusion lies in the PowerPC tools and startup. I want to make sure that the board and tools (ISE 6.1 Foundation and EDK) are sufficient to get going. I don't need an RTOS for my project so I just want to be able to run my code on the PowerPC either from external RAM or internal BRAM. Confusion is about the BOOT up process and wether I will have to write alot of system level code. Can someone help me out or point me to a document that might clear up my concerns. I would love to talk with someone that is currently using this product. Please e-mail me. Thanks in advance, AJArticle: 64936
How long are the "power-up values" stable? The EP10K has a stabilization
time that will need to be taken into account and compared against your old
part.
"Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message
news:4007BE46.6040609@numeri-cable.fr...
> Hi
> I am working on a design involving the cloning of an obsolete chip in an
> FPGA (Altera EP10K family).
> The behavior of the chip depends on some input values "at power-up" (no
> mention of any reset there). My problem is to reliably detect power-up.
>
> I could still manage something with the reset condition but that's not
> exactly what the datasheet says ("If <input signal> is strapped Low at
> power-up...")
>
> --
> ____ _ __ ___
> | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
> | | | | | (_| |_| | Invalid return address: remove the -
> |_| |_|_|\__|\___/
>
Article: 64937Stephane, Sorry I can't help you with your problem. I don't have the Avent VirtexII pro board yet, but I am thinking of getting it. I would really like to talk with you to make sure the board is a good board. The PCI card will be put into a windows PC, which might be different than you are doing. Anyway, if you can help that would be great. AJ Mancini Stephane <nospam@nospam.nospam> wrote in message news:<pan.2003.12.23.09.18.55.112623@nospam.nospam>... > Hi, > Please could you tell me if there's a linux driver of the Virtex II Pro > development board from Avnet (Silica) ? > I would like to know if there's an equivalent to the PCIUtility for Linux. > Indeed, I would like to have my workstation with linux and work with the > board directly through the pci bus. > What could I do ? > Thanks for your help > StephaneArticle: 64938
Hi everyone, I am working on a project and I need to run different designs on a variety of FPGAs. More specifically, I would like to have 4 to 9 FPGAs running at once. I noticed that XILINX will not run in multiple instances. Is there any way that I can (1) simulate such a system? (2) download the design for each FPGA to that particular FPGA? - Thanks in advance.Article: 64939
I have a board with ten Virtex2 chips on it and they all run at the same time. I don't ever do simulations of the whole thing together, though. I simulate the parts, put them together, put them into the chips, and then pray she works. Most of the issues I've had have been with wire termination between chips and clock signal synchronization, and I don't know that you can simulate those very well anyhow. The bus controller on my board handles the programming of each of the chips through SelectMap Slave mode, though when I was working on the bus controller I could program all the chips with the JTAG. "Patrick Browne" <pbrowne0@excite.com> wrote in message news:15e7d80c.0401160839.2cd76ec9@posting.google.com... > Hi everyone, > I am working on a project and I need to run different designs on a > variety of FPGAs. More specifically, I would like to have 4 to 9 FPGAs > running at once. I noticed that XILINX will not run in multiple > instances. Is there any way that I can (1) simulate such a system? (2) > download the design for each FPGA to that particular FPGA? > > - Thanks in advance.Article: 64940
Hi, I would like to experiment with VHDL code, I was wondering if there is any good free tools (dont care about limits) that I could use? ThanksArticle: 64941
Sorry, but that subject line was just to make you read this post !
I had posted earlier but to no avail.
here it goes again:
I am using a Virtex 2 Pro (V2P7) device to perform some deserialization and
8b/10b decoding.
I use ISE 6.1SP3 and Active HDL 6.1 SP2.
Its a very simple design and right now all I am trying to do is to get
something out of the tranceiver.
The code is given below :
The DCM parts simulate ok but I am not sure about how to drive the RXP and
RXN inputs to the Transceiver.
I try to feed opposite polarity clocks into them in the hope that at least
Recoverd Clock i should get to see.
But i see nothing...
Any help will be apprecaiated,
Thanks in advance
Adarsh
//Top Level
module GT_TOP
(DinP,DinN,ClkP,ClkN,Dout,DCMLocked,RefClk80,UsrClk,RXRECCLK,RXRESET);
input DinP;
input DinN;
input ClkP,ClkN;
input RXRESET;
output [15:0] Dout;
output DCMLocked;
output RefClk80;
output UsrClk;
output RXRECCLK;
// ********************************************************************
// ******************** CLOCK SECTION *****************
// *********************************************
// XST is stupid at handling clocks and clock buffer, so we instantiate
// all the buffers and inihbit XST from changing them with the attribute.
wire RefClk80;
wire DCMLocked;
wire UsrClk,DCMClkFBOut,DCMUsrClk,DCMClkFBIn;
// Instantiate the Differential Global Input Buffer
IBUFGDS DIFCLKBUF (.I(ClkP), .IB(ClkN), .O(RefClk80) );
//synthesis attribute clock_buffer of ClkP is "none"
//synthesis attribute clock_buffer of ClkN is "none"
BUFG USRCLKBUF (.I(DCMUsrClk), .O(UsrClk)); // Use this output as
User clock to GTs
//synthesis attribute clock_buffer of DCMUsrClk is "none"
BUFG FBCLKBUF (.I(DCMClkFBOut), .O(DCMClkFBIn)); // clock for feedback
//synthesis attribute clock_buffer of DCMClkFBOut is "none"
// synthesis translate_off
defparam DCMGT.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCMGT.FACTORY_JF = 16'hC080;
defparam DCMGT.CLKDV_DIVIDE = 2.0;
defparam DCMGT.CLKFX_DIVIDE = 1;
defparam DCMGT.CLKFX_MULTIPLY = 4;
defparam DCMGT.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCMGT.CLK_FEEDBACK = "1X";
defparam DCMGT.DLL_FREQUENCY_MODE = "LOW";
defparam DCMGT.PHASE_SHIFT = 0;
defparam DCMGT.SIM_CLKIN_CYCLE_JITTER = 300;
defparam DCMGT.SIM_CLKIN_PERIOD_JITTER = 1000;
defparam DCMGT.MAXPERCLKIN = 41668;
defparam DCMGT.MAXPERPSCLK = 1264998735;
//synthesis translate_on
//synthesis attribute CLKDV_DIVIDE of DCMGT is "2.0"
//synthesis attribute DUTY_CYCLE_CORRECTION of DCMGT is "TRUE"
DCM DCMGT
(
.CLK0 (DCMClkFBOut),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLKDV (DCMUsrClk),
.CLKFX (),
.CLKFX180 (),
.LOCKED (DCMLocked),
.PSDONE (),
.STATUS (),
.CLKFB (DCMClkFBIn),
.CLKIN (RefClk80),
.DSSEN (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (1'b0)
);
wire RXRESET;
wire [1:0] RXBUFSTATUS;
wire [1:0] RXCHARISCOMMA;
wire [1:0] RXCHARISK;
wire RXCOMMADET;
wire [1:0] RXDISPERR;
wire [1:0] RXLOSSOFSYNC;
wire [1:0] RXNOTINTABLE;
wire RXREALIGN;
wire RXRECCLK;
wire [1:0] RXRUNDISP;
gtmacro1 GT1 (
.CONFIGENABLE(1'b0),
.CONFIGIN(1'b0),
.ENMCOMMAALIGN(1'b0),
.ENPCOMMAALIGN(1'b0),
.POWERDOWN(1'b0),
.REFCLK(RefClk80),
.REFCLK2(RefClk80),
.REFCLKSEL(1'b0),
.RXN(DinN),
.RXP(DinP),
.RXPOLARITY(1'b0),
.RXRESET(RXRESET),
.RXUSRCLK(UsrClk),
.RXUSRCLK2(UsrClk),
.TXUSRCLK(UsrClk),
.TXUSRCLK2(UsrClk),
.CONFIGOUT(),
.RXBUFSTATUS(RXBUFSTATUS),
.RXCHARISCOMMA(RXCHARISCOMMA),
.RXCHARISK(RXCHARISK),
.RXCLKCORCNT(),
.RXCOMMADET(RXCOMMADET),
.RXDATA(Dout),
.RXDISPERR(RXDISPERR),
.RXLOSSOFSYNC(RXLOSSOFSYNC),
.RXNOTINTABLE(RXNOTINTABLE),
.RXREALIGN(RXREALIGN),
.RXRECCLK(RXRECCLK),
.RXRUNDISP(RXRUNDISP)
);
endmodule
// instantiation of the macro
module gtmacro1(
CONFIGENABLE,
CONFIGIN,
ENMCOMMAALIGN,
ENPCOMMAALIGN,
POWERDOWN,
REFCLK,
REFCLK2,
REFCLKSEL,
RXN,
RXP,
RXPOLARITY,
RXRESET,
RXUSRCLK,
RXUSRCLK2,
TXUSRCLK,
TXUSRCLK2,
CONFIGOUT,
RXBUFSTATUS,
RXCHARISCOMMA,
RXCHARISK,
RXCLKCORCNT,
RXCOMMADET,
RXDATA,
RXDISPERR,
RXLOSSOFSYNC,
RXNOTINTABLE,
RXREALIGN,
RXRECCLK,
RXRUNDISP);
input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input TXUSRCLK;
input TXUSRCLK2;
output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;
GT_ETHERNET_2 GT_ETHERNET_INST(
.CONFIGENABLE (CONFIGENABLE),
.CONFIGIN (CONFIGIN),
.ENMCOMMAALIGN (ENMCOMMAALIGN),
.ENPCOMMAALIGN (ENPCOMMAALIGN),
.LOOPBACK (2'b00),
.POWERDOWN (POWERDOWN),
.REFCLK (REFCLK),
.REFCLK2 (REFCLK2),
.REFCLKSEL (REFCLKSEL),
.BREFCLK (1'b0),
.BREFCLK2 (1'b0),
.RXN (RXN),
.RXP (RXP),
.RXPOLARITY (RXPOLARITY),
.RXRESET (RXRESET),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.TXBYPASS8B10B (2'b00),
.TXCHARDISPMODE (2'b00),
.TXCHARDISPVAL (2'b00),
.TXCHARISK (2'b00),
.TXDATA (16'b0000000000000000),
.TXFORCECRCERR (1'b0),
.TXINHIBIT (1'b0),
.TXPOLARITY (1'b0),
.TXRESET (1'b0),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.CONFIGOUT (CONFIGOUT),
.RXBUFSTATUS (RXBUFSTATUS[1:0]),
.RXCHARISCOMMA (RXCHARISCOMMA[1:0]),
.RXCHARISK (RXCHARISK[1:0]),
.RXCHECKINGCRC (),
.RXCLKCORCNT (RXCLKCORCNT[2:0]),
.RXCOMMADET (RXCOMMADET),
.RXCRCERR (),
.RXDATA (RXDATA[15:0]),
.RXDISPERR (RXDISPERR[1:0]),
.RXLOSSOFSYNC (RXLOSSOFSYNC[1:0]),
.RXNOTINTABLE (RXNOTINTABLE[1:0]),
.RXREALIGN (RXREALIGN),
.RXRECCLK (RXRECCLK),
.RXRUNDISP (RXRUNDISP[1:0]),
.TXBUFERR (),
.TXKERR (),
.TXN (),
.TXP (),
.TXRUNDISP ());
// synthesis attribute ALIGN_COMMA_MSB of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CHAN_BOND_LIMIT of GT_ETHERNET_INST is 1
// synthesis attribute CHAN_BOND_MODE of GT_ETHERNET_INST is "OFF"
// synthesis attribute CHAN_BOND_OFFSET of GT_ETHERNET_INST is 0
// synthesis attribute CHAN_BOND_ONE_SHOT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute CHAN_BOND_SEQ_2_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CHAN_BOND_SEQ_LEN of GT_ETHERNET_INST is 1
// synthesis attribute CHAN_BOND_WAIT of GT_ETHERNET_INST is 7
// synthesis attribute CLK_CORRECT_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute CLK_COR_INSERT_IDLE_FLAG of GT_ETHERNET_INST is
"FALSE"
// synthesis attribute CLK_COR_KEEP_IDLE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CLK_COR_REPEAT_WAIT of GT_ETHERNET_INST is 1
// synthesis attribute CLK_COR_SEQ_1_1 of GT_ETHERNET_INST is 00110111100
// synthesis attribute CLK_COR_SEQ_1_2 of GT_ETHERNET_INST is 00001010000
// synthesis attribute CLK_COR_SEQ_1_3 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_1_4 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_1 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_2 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_3 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_4 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CLK_COR_SEQ_LEN of GT_ETHERNET_INST is 2
// synthesis attribute COMMA_10B_MASK of GT_ETHERNET_INST is 1111111000
// synthesis attribute CRC_END_OF_PKT of GT_ETHERNET_INST is "K29_7"
// synthesis attribute CRC_FORMAT of GT_ETHERNET_INST is "ETHERNET"
// synthesis attribute CRC_START_OF_PKT of GT_ETHERNET_INST is "K27_7"
// synthesis attribute DEC_MCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute DEC_PCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute DEC_VALID_COMMA_ONLY of GT_ETHERNET_INST is "TRUE"
// synthesis attribute MCOMMA_10B_VALUE of GT_ETHERNET_INST is 1100000000
// synthesis attribute MCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute PCOMMA_10B_VALUE of GT_ETHERNET_INST is 0011111000
// synthesis attribute PCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_BUFFER_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_CRC_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute RX_DATA_WIDTH of GT_ETHERNET_INST is 2
// synthesis attribute RX_DECODE_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_LOSS_OF_SYNC_FSM of GT_ETHERNET_INST is "FALSE"
// synthesis attribute RX_LOS_INVALID_INCR of GT_ETHERNET_INST is 1
// synthesis attribute RX_LOS_THRESHOLD of GT_ETHERNET_INST is 4
// synthesis attribute TERMINATION_IMP of GT_ETHERNET_INST is 50
// synthesis attribute SERDES_10B of GT_ETHERNET_INST is "TRUE"
// synthesis attribute TX_BUFFER_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute TX_CRC_FORCE_VALUE of GT_ETHERNET_INST is 11010110
// synthesis attribute TX_CRC_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute TX_DATA_WIDTH of GT_ETHERNET_INST is 2
// synthesis attribute TX_DIFF_CTRL of GT_ETHERNET_INST is 500
// synthesis attribute TX_PREEMPHASIS of GT_ETHERNET_INST is 0
// synthesis attribute REF_CLK_V_SEL of GT_ETHERNET_INST is 0
// synthesis translate_off
defparam GT_ETHERNET_INST.CLK_COR_INSERT_IDLE_FLAG="FALSE";
defparam GT_ETHERNET_INST.CLK_COR_KEEP_IDLE="FALSE";
defparam GT_ETHERNET_INST.CLK_COR_REPEAT_WAIT=1;
defparam GT_ETHERNET_INST.RX_CRC_USE="FALSE";
defparam GT_ETHERNET_INST.RX_LOSS_OF_SYNC_FSM="FALSE";
defparam GT_ETHERNET_INST.RX_LOS_INVALID_INCR=1;
defparam GT_ETHERNET_INST.RX_LOS_THRESHOLD=4;
defparam GT_ETHERNET_INST.TERMINATION_IMP=50;
defparam GT_ETHERNET_INST.SERDES_10B="TRUE";
defparam GT_ETHERNET_INST.TX_CRC_FORCE_VALUE=8'b11010110;
defparam GT_ETHERNET_INST.TX_CRC_USE="FALSE";
defparam GT_ETHERNET_INST.TX_DIFF_CTRL=500;
defparam GT_ETHERNET_INST.TX_PREEMPHASIS=0;
defparam GT_ETHERNET_INST.REF_CLK_V_SEL=0;
// synthesis translate_on
endmodule
Article: 64942Hi, I have read the article about slack and margins written by Austin Lesea and I am anxious to have more information concerning "any ripple or noise detracts directly from the speed of the part. 200 mV peak-to-peak of noise and ripple on the internal core power supply of a 1.5 volt part results in a significant slowdown". How big is the impact of the ripple on the timings. I believe the converters on the board I have can provide 50mV peak-to-peak of ripple/noise. Will my timing margins degrade ? Any type of information will be welcome. Thanks, JFArticle: 64943
Allan Herriman wrote:
>
> On Thu, 15 Jan 2004 23:59:35 -0500, Ralph Malph <noone@yahoo.com>
> wrote:
>
> >Trying to treat this as a synchronous interface would be very, very
> >difficult. I have tried to do this on a chip where I *had access* to
> >the CPU clock. But the relative timing was not spec'd. So the best I
> >could do was to use the edges of strobes to clock data and then resync
> >to the clock.
>
> I've had a lot of success treating nominally asynchronous interfaces
> as synchronous. But then, these were all low speed (<= 50MHz) with
> timing specified in terms of the clock, except for one which I
> measured (and took the attendant risk).
It can be done, but if the edges are spec'd relative to the clock, then
in essence this *is* a synchonous interface to async memory. If the
edges are *not* spec'd relative to the clock, then you are playing with
fire since the timing can vary from lot to lot and with temperature,
etc. It may work well, or it may fail on every hundredth board.
> >Although your ALE may be very short, you can use the trailing edge to
> >clock or gate the data into FFs. Then you should be able to retime the
> >strobes (and assert the RDY/WAIT or otherwise add wait states) to allow
> >your FPGA a couple of internal clock cycles to read the data.
>
> I've done this too, and I agree that it's a better solution for the
> OP.
>
> Also,
> - ALE doesn't need to be on a BUFG even though it is used as a clock
> (since there is no skew issue).
>
> - Even if ALE is reallllly narrow, it's still possible to get it into
> your clock domain by stretching it. Connecting ALE to the clock of a
> FF. Tie D high, so that Q goes high on the rising edge of ALE.
> Asynchronously reset the FF once Q is sampled in the other clock
> domain. It's ugly but it works.
>
> E.g.
>
> Your clock --o---------------------+
> | |
> | |
> | |
> | |
> | |
> .---. | .---. __ | .---.
> '1'-------|D Q|---------|D Q|-----| | +-----|D Q|----+--
> ALE----------|>C | +----|>C | |& |-+ +---|>C | |
> +---|R | | | +-|__| | |o-+ |
> | '---' '---' | '---' | |
> | +-------------------+ |
> | |
> +-----------------------------------------------+
>
> created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
>
> The and gate is needed to ensure that the output pulse is only one
> clock wide. (Note that this could be turned into a synchronous reset
> on the third flip flop, which removes the and gate delay from the
> metastability resolution time of the second flip flop.)
>
> For some reason, the Xilinx tools won't trace delays on async resets
> by default. There's some magic incantation in the pcf that makes it
> work though (I can't remember it right now).
>
> I don't mean to claim that this is the only way you can do it -
> there are many other equivalent circuits that would work just as well.
I was once shown a circuit similar to yours above, that gets rid of the
async reset and replaces the and gate with an XOR.
___G1
+-----------| | Output1
| |XOR|---
+-----------------------------+--|___|
| | | Output2
| FF1 | | ___G2
| .---. | | +-----------| |
+--|D |- | | | |XOR|---
ALE | | FF2 | FF3 | | FF4 +-|___|
-----o|>C | .---. | .---. | | .---. |
| |o-----|D |--+--|D |-+--+--|D |--+
'---' | | | | | |
+--o|>C | +-o|>C | +-o|>C |
| | |o | | |o | | |
| '---' | '---' | '---'
| | | Clock
+----------+-----------+------------------
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
This circuit toggles the FFs each time the ALE clocks the first FF. No
reset is needed. FF2 and FF3 sync the edge to the new clock domain.
You can use G1 to output a one clock wide pulse if the gate does not
take too much time from the metastable settling. Or if you are running
a very fast clock, you can use FF4 and G2 to generate the one clock wide
pulse.
Thanks for the ASCII art reference. This is very useful.
Article: 64944On Fri, 16 Jan 2004 16:58:52 GMT, x86asm <isaac_8e@hotmail.com> wrote: > Hi, I would like to experiment with VHDL code, I was wondering if there > is any good free tools (dont care about limits) that I could use? If you have a no problems with large file downloads, then I suggest you the ModelSim simulator. There is a special Xilinx edition which comes together with ISE WebPack for free. I think it's a good start. You can download it at the Xilinx website (free registration required): <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack> HTH & HAND, SteffArticle: 64945
Chris Carlen wrote: > Hi: > > I am using Xilinx Webpack and Modelsim XEII starter 5.7c to simulate > Verilog. > > If I put a `timescale directive in my uut, the compiler complains > "module 'xxx' has a `timescale directive in effect, but previous modules > do not." > > If I don't put in a `timescale directive, then it makes the same message > about the 'glbl' module. > > Right now it gives peculiar results with the `timescale 10ns/1ns in my > source, but simulates correctly without the directive. Trouble is, it > has units of 1ps for each timestep without the directive. > > How can I properly use the `timescale directive? This is only for > functional simulation to learn Verilog. I know that things will get > more complicated for synthesis for real devices. > > Thanks for comments. > > Good day! I made some progress by putting the `timescale directive in both the source and test Verilog files. Then I just have to fiddle with the options available in the Simulate and Simulate Options menus in Modelsim to get the length of simulation and time axis resolution I want. Good day! -- ____________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.govArticle: 64946
Hello, Excuse me, but I can't enter in WebCase in http://www.xilinx.com/support, then I will post here for someone post there. When I copy something twice, in HDL Bencher, or when i copy once then close the Bencher, the HDL Bencher crash. and pop-up the following message: FATA_ERROR:GuiUtilities:WinAPP.c:657:$Revision - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answer Database and other online resources at http://support.xilinx.com. If you need further assistance,please open a Webcase by clicking on the "Webcase" link at http://support.xilinx.com Then, after I press OK: The instruction at "0x73dd1351" referenced memory at "0x00000004". The memory could not be "read". Thank, Tonny Matos SiqueiraArticle: 64947
JF, As long as the voltage never goes below the min (1.425V in this case), noise included, all timing will be met (we guard-band the speeds files and do all testing at hot, and low Vcc). If, however, the noise takes you below 1.425V, then you degrade the timing. Additionally, noise adds jitter, which should be characterized (measured) which also reduces the slack. Austin jean-francois hasson wrote: > Hi, > > I have read the article about slack and margins written by Austin Lesea and > I am anxious to have more information concerning "any ripple or noise > detracts directly from the speed of the part. 200 mV peak-to-peak of noise > and ripple on the internal core power supply of a 1.5 volt part results in a > significant slowdown". How big is the impact of the ripple on the timings. I > believe the converters on the board I have can provide 50mV peak-to-peak of > ripple/noise. Will my timing margins degrade ? Any type of information will > be welcome. > > Thanks, > > JF > >Article: 64948
Alex Rast wrote: > I have an FPGA-based prototype for a PCI product in development. Since the > intended product application will involve very high speed data transfers, > we have designed all the I/O and internal busses in the FPGA to work on > synchronous protocols. Now, however, I'm running into a real stumbling > block. > > The problem is in testing the board. What I need to do is to be able to > generate some test data on a PC, and send it to the FPGA, simulating data > flow through the system under test. Similarly, the PC needs to be able to > receive test data from the FPGA. Because of the design of the board, I need > to use a synchronous, hardware-based protocol and interface to transfer the > data. > > However, there doesn't seem to be much hardware out there that will enable > me to do this, at least not at reasonable cost. All I need to do is dump > bitstreams in either direction, synchronously, but I have met with little > success. We made an abortive effort to use LabView together with their DIO- > 32HS, which seemed promising and (supposedly) offered a high-speed > synchronous protocol, but when we tried to use it, the protocol didn't > work, we couldn't make it work, and apparently nobody at National > Instruments had tried using that protocol and gotten it to work. Indeed, I > saw others posting on the Labview NG, running into the same problems! So > that's not an option. > > So, what would be the easiest way to create a test interface that lets us > transfer data using a synchronous protocol at reasonable speeds (at least > 10 MHz) between a PC and a device under test? Our prototype board has no > shortage of high-speed, MICTOR connectors that we can use to interface to. > We're willing to spend some dollars to do it, but if it starts escalating > into the thousands of dollars just to get a simple test interface, I think > that such a price is disproportionate relative to what we need to achieve. > So I think a fair budget limit is around $2000. Any suggestions? I had a National Intsruments HS32 board too. Even though it appears to offer half a dozend protocols, none worked for us. The protocols worked, but we were unable to use them to our hardware. The support of NI was (well they tried but to no avail) lacking. Their forums aren't that supportive and very slow. I'd suggest to use a second of your boards. You don't need its PCI interface, just reload some other firmware into the FPGA to let it act as pattern generator. If you don't happen to have a second board, you may let us know what FPGA with what interface you wish to use. One may have a spare board. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 64949
Hello Adam Thanks for ur reply in Google.com for my question about AFX Board.I have few more Doubts and it would be great if u would help me with that.Sorry more bothering you. 1.Now Once i download the configuration file to the fpga then i can use the area surrounding the Chip for reading out values in each pin through those area with logical analyzer.But why do we need the prototype area in the board on the left side.How can i use that. 2. Then to specify the I/O type.What is that.I am not clear.(your design must specify the I/O type to use(LVTTL, LVDS, etc)).If possible can u send me an simple code like showing this. Thanks Regards Bhadri "Adam" <unreal@rpi.edu> wrote in message news:<JrMKb.30153$Dq1.18725@twister.nyroc.rr.com>... > I just used this board for my project a few weeks ago but this is off the > top of my head so some things may be wrong. My goal was only a 30-40 cycle > test at 15MHz. You should have the protoboard datasheet and the XCV1000 > datasheet handy as you will reference them a lot when you constrain your > I/O. You will also need a 3.3v and 2.5v power supply in addition to a > download cable. I used a MultiLinx in slave-serial mode. There are jumpers > on the board to specify which download mode you are using. > The Virtex has 'banks' of I/O that can each run on its own supply voltage. > This is set by a row of jumpers on the left side of the AFX board. The > board I used already had all I/O banks jumpered to the 3.3 supply. The > VccINT post powers the chip core. For an XCV1000 this is 2.5v(****check the > datasheet to be sure****). You should be aware that your design must > specify the I/O type to use(LVTTL, LVDS, etc) > In the Virtex datasheet you will find the pinouts for the 560BGA package > labeled with two alphanumeric characters(such as AR or B4). These > correspond to the prototype area holes around the chip on the AFX board. > *Note* that some rows and columns are entirely ground. Since my I/O usage > was small(16-20 pins), I simply inserted the headers that come with the > board into a row that had a lot of consecutive general I/O pins. I then just > attached my logic analyzer cable to these headers. I discovered that they > don't make good contact unless slightly pressed against but other than that > worked fine. > There may or may nor be a clock chip already on your board. The four > sockets at each corner of the chip holder are for clock chips. If one is > populated make sure you don't attempt to use another external clock on the > same pin. Pin AL or AK I think is the lower left clock chip. > You won't be able to use Webpack because the XCV1000 is larger than the > V300E device, the largest Webpack supports. You will need the real ISE to > program. > > Adam > > "Bhadri" <bhadrig@yahoo.com> wrote in message > news:d574235a.0401061819.73186542@posting.google.com... > > Hello > > I am trying to use AFX BG560-100 board from > > > xilinx.(http://www.xilinx.com/xlnx/xebiz/board_detail.jsp?key=HW-AFX-BG560-1 > 00&category=) > > I have XCV 1000 fgpa chips to use with the board. > > I have never used this board before.I was using Dililentinc board till > > this. > > 1.Can anyone tell me how to start using this board for simple > > applications. > > 2.How to use the prototype area in the board. > > 3.can i use the same ISE webpack software 5.1i to program this chips > > with the board or is there any other software. > > > > Thanks in advance.It would be of great help. > > bhadri.
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