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On 04/27/2010 02:26 PM, Alex wrote: > I also wonder whether free software packages (such as FreePCB, > ExpressPCB) are good enough for PCB designs using FPGA chips? gEDA/PCB has had a number of success stories with high density FPGA designs. Despite being free, there are no limits on size, density, layers, or whatnot. There are some user-contributed scripts to turn pinout lists (i.e. from FPGA design software) into a "schematic" so you don't have to make those huge symbols, too. The only thing it doesn't do at the moment is blind and buried vias, although I've seen a patch to add that too...Article: 147451
On Apr 27, 6:28=A0am, Usama <usama...@gmail.com> wrote: > Hi, > > I am implementing BMD design as explained in xapp1052(v2.5). Have > implemented the design on AvnetV5LXT/SXT PCIe Development Board using > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using > only x1 lane of PCIe in my application. on both the machines i am > facing different problems. > > Problem on S5000XVN > =A0 =A0 =A0 =A0 =A0 =A0 on this machine i have 2 x4 slots and 1 x16 slot.= wen i > plug in a card on the one of the x4 slot my application runs perfectly > fine but when i plug it on the other x4 slot the data which i get is > not a valid data there is some garbage value shown in the data. What > could b the problem over here? Any idea ? > > Problem on S3210SHLC > =A0 =A0 =A0 =A0 =A0 =A0on this machine i am facing the problem that when = i plug in > one of Avnet V5LXT/SXT PCIe Development Board the computer detects the > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the > system is unable to detect it. i don't understand this strange > behavior why is it showing such a behavior. dose anyone know the > solution to this problem The PCIe link is not working, (probably) because the lane aggregation isn't happening properly. Until you know enough about PCIe, and especially how lanes become links, no one will be able to help you. RKArticle: 147452
On Apr 27, 5:34=A0pm, DJ Delorie <d...@delorie.com> wrote: > On 04/27/2010 02:26 PM, Alex wrote: > > > I also wonder whether free software packages (such as FreePCB, > > ExpressPCB) are good enough for PCB designs using FPGA chips? > > gEDA/PCB has had a number of success stories with high density FPGA > designs. =A0Despite being free, there are no limits on size, density, > layers, or whatnot. =A0There are some user-contributed scripts to turn > pinout lists (i.e. from FPGA design software) into a "schematic" so you > don't have to make those huge symbols, too. > > The only thing it doesn't do at the moment is blind and buried vias, > although I've seen a patch to add that too... Unless you're dealing with severe board area restrictions I see no reason to get into blind and buried vias. You might need to up your layer count slightly without them, but overall manufacturing cost is still better with through via only. We've managed to avoid buried vias entirely here, and only used blind vias on a very small board that had no room for components except behind a BGA. That one also had back-filled via-in-pad so looking at the bare laminate you would think it wasn't drilled.Article: 147453
On Tue, 27 Apr 2010 11:26:15 -0700 (PDT), Alex <victous@gmail.com> wrote: >Hello, > >I am a beginner interested to learn what PCB design software is >suitable for designs using FPGA chips? > >I also wonder whether free software packages (such as FreePCB, >ExpressPCB) are good enough for PCB designs using FPGA chips? > >Thank you. FreePCB is definitely up to the job, but make sure you use a Gerber viewer and double-check the output; there may be some fiddling with settings required to meet your PCB fabricator's requirements. (This goes for paid-for PCB packages too!) Caveat: my project using FreePCB didn't actually get as far as fabrication, but it was looking good. My major gripe with FreePCB was that it was Windows only. - BrianArticle: 147454
On Tue, 27 Apr 2010 03:41:01 -0700 (PDT), dgreig wrote:
>Unfortunataly unsigned to signed requires zero padding, adding the
>extra bit inferres a 18*18 block rather than 9*9. In the case of 18
>bit inputs the unsigned to signed requires one more bit than the block
>actually has.
What about Kolja Sulimma's suggestion of a conditional adder
after a 17x18 multiply? This is only a sketch, but shows
that it is quite neat both in VHDL code and in hardware:
subtype S36 is signed(35 downto 0);
function U18xS18 (
U: unsigned(17 downto 0),
S: signed(17 downto 0)
) return S36 is
variable product: S36;
begin
product := signed'(U) * S;
if (U(17) = '1') then
product(35 downto 18) :=
product(35 downto 18) + signed'(U);
end if;
return product;
end;
Disclaimer: I haven't tried synthesising this, and I suspect you
may need to play with the code some more to get the best
synthesis results.
--
Jonathan Bromley
Article: 147455On Apr 27, 5:52=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 27 Apr 2010 11:26:15 -0700 (PDT), Alex <vict...@gmail.com> > wrote: > > >Hello, > > >I am a beginner interested to learn what PCB design software is > >suitable for designs using FPGA chips? > > >I also wonder whether free software packages (such as FreePCB, > >ExpressPCB) are good enough for PCB designs using FPGA chips? > > >Thank you. > > FreePCB is definitely up to the job, but make sure you use a Gerber > viewer and double-check the output; there may be some fiddling with > settings required to meet your PCB fabricator's requirements. > (This goes for paid-for PCB packages too!) > > Caveat: my project using FreePCB didn't actually get as far as > fabrication, but it was looking good. > > My major gripe with FreePCB was that it was Windows only. > > - Brian We do Gerber checks even on the files created by outside design services. You'd be surprised at how many "disconnects" there are between the design database and the Gerber output files. I use a Gerber view from PentaLogix that allows you to edit the Gerbers. This is useful for some things like removing thermal relief on vias, or adding odd openings over copper in the solder mask. If I recall correctly it cost less than $100, and the version that doesn't allow editing is free. Regards, GaborArticle: 147456
Am Tue, 27 Apr 2010 11:17:03 +0100 schrieb Brian Drummond <brian_drummond@btconnect.com>: > On Tue, 27 Apr 2010 10:03:34 +0200, Martin Brückner > <bj2spam@alice-dsl.net> wrote: > > >Am Mon, 26 Apr 2010 22:08:02 +0000 (UTC) > >schrieb glen herrmannsfeldt <gah@ugcs.caltech.edu>: > > > >> Martin Br?ckner <bj2spam@alice-dsl.net> wrote: > >> > >> > I'm writing a boot loader to start Linux on the PowerPC440 > >> > (Virtex5FXT). At first the program copies the kernel into the RAM > >> > at address 0x00400000 and afterwards it boots Linux with the > >> > following lines: > >> > >> > #define LINUX_START_ADDRESS 0x004002b4 > >> > >> (snip) > >> > >> > (*linux)(); > >> > >> With the assumption that data pointers can be properly > >> cast to function pointers, that line should jump to > >> location 0x4002b4 and start executing the code there. > > I haven't used the PPC since the V2Pro, but... > > Xilinx example code typically has boilerplate to do things like > invalidate caches and set up interrupt state before handing over to > "real" code. It is possible that using XMD to reset the CPU does that > for you. > > Have you covered these bases in your own code? When I started with this project I was sure that Linux invalidates caches and sets up the interrupt state and the comments in arch/powerpc/kernel/head_44x.S seems to confirm that (I am not deep enough into PowerPC Assembler to understand all of its code). Probably there might be a bug in this initializing code. Anyway, all I tried out yet was disabling the cache but that did not help. Do you know where to find more Xilinx-Commands to handle Cache and MMU? > > - Brian MartinArticle: 147457
Am Tue, 27 Apr 2010 18:23:11 +0000 (UTC) schrieb glen herrmannsfeldt <gah@ugcs.caltech.edu>: > Joe Chisolm <jchisolm6@earthlink.net> wrote: > > On Mon, 26 Apr 2010 22:50:19 +0200, Martin Br?ckner wrote: > > >> I'm writing a boot loader to start Linux on the PowerPC440 > >> (Virtex5FXT). At first the program copies the kernel into the RAM > >> at address 0x00400000 and afterwards it boots Linux with the > >> following lines: > > >> #define LINUX_START_ADDRESS 0x004002b4 > (snip) > >> (*linux)(); > > > Did you setup the stack pointer? The above is going to try and push > > the return address on the stack. Compile with -S and look at the > > resulting asm output. > > Not knowing at all about the linux boot process, I would have > assumed that one of the first thing that the booting kernel does > would be to set up its own stack. > > It might, though, depend on a previous level of boot program > to have set up a stack for it. I wouldn't expect the boot > ROM to have done it, but often there are multiple levels of > boot programs. > > -- glen As I wrote before (answering Brian), I also assumed that Linux would manage that. What I found out this day is, that the Linux syslog-buffer is empty. MartinArticle: 147458
On Apr 27, 8:59=A0am, Eric <eric.lafor...@gmail.com> wrote: > > You mentioned earlier that you had implemented this at some point in > the past. Could you tell me more about where you heard about this > (domain, application, etc...) or did you come up with it yourself? I'm > just trying to suss out the common origin of the multiple XOR > suggestions I've received. This was original development. It started from flag management between two asynchronous domains. Then it moved to data manipulation between two async domains. Extending it to larger memories just flowed.Article: 147459
On Apr 27, 6:05=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 26 Apr 2010 18:26:25 -0700 (PDT), Patrick Maupin > > > > <pmau...@gmail.com> wrote: > >On Apr 26, 7:15=A0pm, Andy <jonesa...@comcast.net> wrote: > >> Cliff's paper is about avoiding race conditions. However, in vhdl > >> "blocking assignements" (to unshared variables) are limited to local > >> process/subprogram scope anyway, so you never have problems with race > >> conditions with them. That is why it is safe and even beneficial to > >> use blocking assignments (to unshared variables) in VHDL clocked > >> processes. > > >Yes, the two process model probably isn't nearly as useful in VHDL. > > >As others have been quick to point out, you don't need a combinatorial > >process in verilog either, but then you have to be careful about > >blocking vs. non-blocking, not using variables which have blocking > >assignments to them from other processes, etc. =A0The two process model > >is simply an organizing principle that provides a separation of > >concerns and simplifies the rules a bit, making it easier to reason > >about the code. =A0Extremely simple code doesn't gain anything from > >using this model, but a lot of real-world code does. > > I have to wonder if *that* is the reason the two-process model refuses > to die in VHDL textbooks, tutorials, and example designs worldwide. > > Perhaps too many educators focus on comparing the languages, showing how > the same thing is done *the same way* in both languages. > > I would prefer to see each language shown off at its best. > > Then VHDL could be illustrated with the (much less verbose) single > process model, functions and procedures to raise the abstraction level > and simplify the main process, and proper use of the type system to help > rather than frustrate the user. > > (e.g. recently here, there was an example where someone frustrated > himself by using a type with integer semantics when he really wanted a > type with modular semantics, so he had to code all the wrap-arounds by > hand. Easy pitfall for someone used to C which doesn't have any types > with integer semantics.) > > Likewise best practice in Verilog could be illustrated. > (I have no idea what that is; hearsay suggests it would include avoiding > races, avoiding problems with signed arithmetic, implicit declarations > and so on. But Verilog must have real strengths too) > > - Brian I don't agree that the two process model is inherently less desirable. Or maybe I should say that I don't think describing combinatorial logic outside of clocked processes is inherently less desirable. I seldom put a lot of combinatorial logic in processes, clocked or unclocked, mainly because the structures in processes and combinatorial logic are rather weighty (a synonym for verbose I guess). But it always depends on the logic. Lacking the conditional expression, VHDL concurrent logic can be a PITB to write complex expressions in a clear manner. This means sometimes I put combinatorial in unclocked processes because it is more clear. Simple logic goes in with the clocked process, but when possible, I put combinatorial logic in concurrent statements. A foolish consistency is the hobgoblin of little minds, but there are times when consistency is a good thing in engineering, other times not. I guess I'm consistently inconsistent. RickArticle: 147460
On Apr 27, 6:32=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > This was original development. A little clarification: Many things that are "good" but not immediately obvious have already been done. After I'd been using the technique for async transfers and talked about it on this newsgroup applied to multiport memories a couple years back, I found the technique was already used. Like the rhombic dodecahedron and triacontahedron I "invented" in high school (the Greeks beat me to it by far) those shapes and the XOR technique are unique to those who haven't been exposed to them.Article: 147461
>hi, > >recently I read a quote about VHDL vs Verilog, >along the lines of "VHDL is made by SW people who >don't understand HW and vice versa"... > >Does anybody know the exact wording and origin ? > >yg >-- >http://ygdes.com / http://yasep.org > One can see example between VHDL and verilog in the following example. I developed sparse memory model in each language. While I could do it easily in VHDL in verilog I needed VPI (c - interface). The work was posted on : h===://bknpk.no-ip.biz/my_web/MiscellaneousHW//memory_hdl_models.html --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147462
This issue is frequently discussed on this board. I made a comparison and tested on VHDL and verilog using free simulators (GHDL and icaus). The test case was "to use a sparse memory model to reduce memory consumption. The idea is that a memory of large address (18 bits) of 16 bits data word consumes, only that much that is written, to the memory model, during simulation." VHDL is rich enough so the it was written completely in VHDL. For verilog I needed to use VPI to simply write it in C. The work was posted at http://bknpk.no-ip.biz/my_web/MiscellaneousHW//memory_hdl_models.html Please send comments on this work. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147463
On Apr 28, 2:41=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Apr 27, 6:28=A0am, Usama <usama...@gmail.com> wrote: > > > > > > > Hi, > > > I am implementing BMD design as explained in xapp1052(v2.5). Have > > implemented the design on AvnetV5LXT/SXT PCIe Development Board using > > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE > > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using > > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using > > only x1 lane of PCIe in my application. on both the machines i am > > facing different problems. > > > Problem on S5000XVN > > =A0 =A0 =A0 =A0 =A0 =A0 on this machine i have 2 x4 slots and 1 x16 slo= t. wen i > > plug in a card on the one of the x4 slot my application runs perfectly > > fine but when i plug it on the other x4 slot the data which i get is > > not a valid data there is some garbage value shown in the data. What > > could b the problem over here? Any idea ? > > > Problem on S3210SHLC > > =A0 =A0 =A0 =A0 =A0 =A0on this machine i am facing the problem that whe= n i plug in > > one of Avnet V5LXT/SXT PCIe Development Board the computer detects the > > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the > > system is unable to detect it. i don't understand this strange > > behavior why is it showing such a behavior. dose anyone know the > > solution to this problem > > The PCIe link is not working, (probably) because the lane aggregation > isn't happening properly. > > Until you know enough about PCIe, and especially how lanes become > links, no one will be able to help you. > > RK Thanks for the reply RK, I guess I was not very clear in the problem description. Let me try to put more details and may be it will help others out to help me solve this problem. I have three motherboards. 1. D945GCCR (reference motherboard) 2. S5000XVN 3. S3210SHLC Th FPGA board that I have supports x8 mechanical connector. The Xilinx BMD design that I have implemented just uses single lane so actually it is configured to operate in x1 mode. The S5000XVN motherboard has three PCIe slots. Two are with x8 mechanical slots supporting x4 mode and the one is with x16 mechanical slot supporting upto x16 mode. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D Total Mechanical Mode =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D 2 x8 x4 1 x16 x16 The x16 slot houses NVidia VGA card on the motherboard. So we are left with the remaining two slots. Theoretically, my BMD design should work on all these slots as it is supported both mechanically and mode wise as well (only implemented x1 mode on the FPGA board). However, the problems that I have mentioned remain the same. On this particular motherboard, I get garbage data mixed with actual data. So I am able to get expected data but there are few locations read out as garbage values. Interestingly, when I use the same FPGA board on reference machine with intel motherboard (D945GCCR) with x16 mechanical connector supporting upto x16 mode, the same FPGA board behaves as expected with NO garbage values. Now lets have a look at the second mother board which is S3210SHLC. This particular motherboard has the following PCIe slots with mechanical slots and lane modes supported. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D Total Mechanical Mode =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D 1 x8 x4 1 x8 x8 1 x16 x8 On this particular motherboard, the behavior is totally different. I have four identical Avnet FPGA boards, all loaded with the same bitstreams. All these boards are successfully detected on S5000XVN motherboard and on a reference motherboard but the strange thing about the subject motherboard (S3210SHLC) is, there is only one FPGA board out of those four FPGA boards which gets detected on this motherboard, the rest of the FPGA boards are not detected on OS bootup. The other problem which is common in this motherboard and the previous motherboard is, when the same FPGA board is plugged into the x8 mechanical slot supporting x4 lanes, I get garbage values coming out of the FPGA along with actual data. But when plugged in x8 and x16 mechanical slots supporting x8 modes on both the slots, the data is read out perfectly. I have been able to establish one common thing in all these tests. All those PCIe slots which mechanically support x8 PCIe cards but downgraded to support upto x4 lanes create problems. All those slots which mechanically support x8 connector FPGA card and support x8 lane mode works fine. The other FPGAs not getting detected and only one getting detected is still confusing. I hope I am very clear this time in adding details and I am hopeful to get more help on this. Thanks UBAArticle: 147464
On Apr 28, 11:24=A0am, Usama <usama...@gmail.com> wrote: > On Apr 28, 2:41=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > > > > > > > On Apr 27, 6:28=A0am, Usama <usama...@gmail.com> wrote: > > > > Hi, > > > > I am implementing BMD design as explained in xapp1052(v2.5). Have > > > implemented the design on AvnetV5LXT/SXT PCIe Development Board using > > > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using IS= E > > > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using > > > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using > > > only x1 lane of PCIe in my application. on both the machines i am > > > facing different problems. > > > > Problem on S5000XVN > > > =A0 =A0 =A0 =A0 =A0 =A0 on this machine i have 2 x4 slots and 1 x16 s= lot. wen i > > > plug in a card on the one of the x4 slot my application runs perfectl= y > > > fine but when i plug it on the other x4 slot the data which i get is > > > not a valid data there is some garbage value shown in the data. What > > > could b the problem over here? Any idea ? > > > > Problem on S3210SHLC > > > =A0 =A0 =A0 =A0 =A0 =A0on this machine i am facing the problem that w= hen i plug in > > > one of Avnet V5LXT/SXT PCIe Development Board the computer detects th= e > > > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board the > > > system is unable to detect it. i don't understand this strange > > > behavior why is it showing such a behavior. dose anyone know the > > > solution to this problem > > > The PCIe link is not working, (probably) because the lane aggregation > > isn't happening properly. > > > Until you know enough about PCIe, and especially how lanes become > > links, no one will be able to help you. > > > RK > > Thanks for the reply RK, > I guess I was not very clear in the problem description. Let me try to > put more details and may be it will help others out to help me solve > this problem. > =A0I have three motherboards. > 1. D945GCCR =A0 (reference motherboard) > 2. S5000XVN > 3. S3210SHLC > > Th FPGA board that I have supports x8 mechanical connector. The Xilinx > BMD design that I have implemented just uses single lane so actually > it is configured to operate in x1 mode. > > The S5000XVN motherboard has three PCIe slots. Two are with x8 > mechanical slots supporting x4 mode and the one is with x16 mechanical > slot supporting upto x16 mode. > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mode > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > 2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 x4 > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0x16 > > The x16 slot houses NVidia VGA card on the motherboard. So we are left > with the remaining two slots. Theoretically, my BMD design should work > on all these slots as it is supported both mechanically and mode wise > as well (only implemented x1 mode on the FPGA board). However, the > problems that I have mentioned remain the same. On this particular > motherboard, I get garbage data mixed with actual data. So I am able > to get expected data but there are few locations read out as garbage > values. Interestingly, when I use the same FPGA board on reference > machine with intel motherboard (D945GCCR) with x16 mechanical > connector supporting upto x16 mode, the same FPGA board behaves as > expected with NO garbage values. > > Now lets have a look at the second mother board which is S3210SHLC. > This particular motherboard has the following PCIe slots with > mechanical slots and lane modes supported. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mode > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 x4 > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 x8 > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 x8 > > On this particular motherboard, the behavior is totally different. I > have four identical Avnet FPGA boards, all loaded with the same > bitstreams. All these boards are successfully detected on S5000XVN > motherboard and on a reference motherboard but the strange thing about > the subject motherboard (S3210SHLC) is, there is only one FPGA board > out of those four FPGA boards which gets detected on this motherboard, > the rest of the FPGA boards are not detected on OS bootup. The other > problem which is common in this motherboard and the previous > motherboard is, when the same FPGA board is plugged into the x8 > mechanical slot supporting x4 lanes, I get garbage values coming out > of the FPGA along with actual data. But when plugged in x8 and x16 > mechanical slots supporting x8 modes on both the slots, the data is > read out perfectly. > > I have been able to establish one common thing in all these tests. All > those PCIe slots which mechanically support x8 PCIe cards but > downgraded to support upto x4 lanes create problems. All those slots > which mechanically support x8 connector FPGA card and support x8 lane > mode works fine. The other FPGAs not getting detected and only one > getting detected is still confusing. > > I hope I am very clear this time in adding details and I am hopeful to > get more help on this. > > Thanks > UBA- Hide quoted text - > > - Show quoted text - So if I summarize your motherboard problem having spitting garbage values and map it on the same table you provided, is this how it will look like? S5000XVN motherboard =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Total Mechanical Mode Test Rsults =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 2 x8 x4 FAIL(garbage values) 1 x16 x16 couldnot test, slot not available S3210SHLC motherboard =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Total Mechanical Mode Test Rsults =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 1 x8 x4 FAIL(garbage values) 1 x8 x8 PASS 1 x16 x8 PASS D945GCCR (reference motherboard) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Total Mechanical Mode Test Rsults =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 1 x16 x16 PASS maverickArticle: 147465
On Apr 28, 11:48=A0am, maverick <sheikh.m.far...@gmail.com> wrote: > On Apr 28, 11:24=A0am, Usama <usama...@gmail.com> wrote: > > > > > > > On Apr 28, 2:41=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > > > > On Apr 27, 6:28=A0am, Usama <usama...@gmail.com> wrote: > > > > > Hi, > > > > > I am implementing BMD design as explained in xapp1052(v2.5). Have > > > > implemented the design on AvnetV5LXT/SXT PCIe Development Board usi= ng > > > > the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using = ISE > > > > 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am usin= g > > > > to run two machine of INTEL i.e S5000XVN and S3210SHLC. I am using > > > > only x1 lane of PCIe in my application. on both the machines i am > > > > facing different problems. > > > > > Problem on S5000XVN > > > > =A0 =A0 =A0 =A0 =A0 =A0 on this machine i have 2 x4 slots and 1 x16= slot. wen i > > > > plug in a card on the one of the x4 slot my application runs perfec= tly > > > > fine but when i plug it on the other x4 slot the data which i get i= s > > > > not a valid data there is some garbage value shown in the data. Wha= t > > > > could b the problem over here? Any idea ? > > > > > Problem on S3210SHLC > > > > =A0 =A0 =A0 =A0 =A0 =A0on this machine i am facing the problem that= when i plug in > > > > one of Avnet V5LXT/SXT PCIe Development Board the computer detects = the > > > > cards. but i put any other Avnet V5LXT/SXT PCIe Development Board t= he > > > > system is unable to detect it. i don't understand this strange > > > > behavior why is it showing such a behavior. dose anyone know the > > > > solution to this problem > > > > The PCIe link is not working, (probably) because the lane aggregation > > > isn't happening properly. > > > > Until you know enough about PCIe, and especially how lanes become > > > links, no one will be able to help you. > > > > RK > > > Thanks for the reply RK, > > I guess I was not very clear in the problem description. Let me try to > > put more details and may be it will help others out to help me solve > > this problem. > > =A0I have three motherboards. > > 1. D945GCCR =A0 (reference motherboard) > > 2. S5000XVN > > 3. S3210SHLC > > > Th FPGA board that I have supports x8 mechanical connector. The Xilinx > > BMD design that I have implemented just uses single lane so actually > > it is configured to operate in x1 mode. > > > The S5000XVN motherboard has three PCIe slots. Two are with x8 > > mechanical slots supporting x4 mode and the one is with x16 mechanical > > slot supporting upto x16 mode. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mode > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > 2 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 x4 > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0x16 > > > The x16 slot houses NVidia VGA card on the motherboard. So we are left > > with the remaining two slots. Theoretically, my BMD design should work > > on all these slots as it is supported both mechanically and mode wise > > as well (only implemented x1 mode on the FPGA board). However, the > > problems that I have mentioned remain the same. On this particular > > motherboard, I get garbage data mixed with actual data. So I am able > > to get expected data but there are few locations read out as garbage > > values. Interestingly, when I use the same FPGA board on reference > > machine with intel motherboard (D945GCCR) with x16 mechanical > > connector supporting upto x16 mode, the same FPGA board behaves as > > expected with NO garbage values. > > > Now lets have a look at the second mother board which is S3210SHLC. > > This particular motherboard has the following PCIe slots with > > mechanical slots and lane modes supported. > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0 =A0 =A0Mode > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 x4 > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 x8 > > 1 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 x8 > > > On this particular motherboard, the behavior is totally different. I > > have four identical Avnet FPGA boards, all loaded with the same > > bitstreams. All these boards are successfully detected on S5000XVN > > motherboard and on a reference motherboard but the strange thing about > > the subject motherboard (S3210SHLC) is, there is only one FPGA board > > out of those four FPGA boards which gets detected on this motherboard, > > the rest of the FPGA boards are not detected on OS bootup. The other > > problem which is common in this motherboard and the previous > > motherboard is, when the same FPGA board is plugged into the x8 > > mechanical slot supporting x4 lanes, I get garbage values coming out > > of the FPGA along with actual data. But when plugged in x8 and x16 > > mechanical slots supporting x8 modes on both the slots, the data is > > read out perfectly. > > > I have been able to establish one common thing in all these tests. All > > those PCIe slots which mechanically support x8 PCIe cards but > > downgraded to support upto x4 lanes create problems. All those slots > > which mechanically support x8 connector FPGA card and support x8 lane > > mode works fine. The other FPGAs not getting detected and only one > > getting detected is still confusing. > > > I hope I am very clear this time in adding details and I am hopeful to > > get more help on this. > > > Thanks > > UBA- Hide quoted text - > > > - Show quoted text - > > So if I summarize your motherboard problem having spitting garbage > values and map it on the same table you provided, is this how it will > look like? > > S5000XVN motherboard > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =A0Total =A0 =A0 =A0=A0 Mechanical =A0 =A0Mode =A0 =A0 =A0 Test Rsults > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =A02 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 x4 FAIL(g= arbage values) > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0=A0x16 =A0=A0 s= lot not available > > S3210SHLC motherboard > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =A0Total =A0 =A0 =A0 Mechanical =A0 =A0 =A0Mode =A0 =A0 =A0Test Rsults > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =A01 =A0 =A0 =A0 =A0 =A0=A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 =A0 =A0=A0 x4 = FAIL(garbage values) > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 =A0 x8 =A0 =A0 =A0 PA= SS > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0=A0 x8 =A0 =A0 =A0 PA= SS > > D945GCCR =A0 (reference motherboard) > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =A0Total =A0 =A0 =A0 =A0 =A0 Mechanical =A0 =A0 =A0 =A0 =A0Mode =A0 =A0 = =A0 =A0Test Rsults > > =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =A01 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 x16 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0x16 =A0 =A0 =A0 =A0 =A0 PASS > > maverick Thats absolutely right. The other problem is the unsuccessful detection of few Avnet FPGA boards. UBAArticle: 147466
http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1418796&highlight= years and years of talk, now going public :) AnttiArticle: 147467
On Apr 27, 11:05=A0pm, Jonathan Bromley <s...@oxfordbromley.plus.com> wrote: > On Tue, 27 Apr 2010 03:41:01 -0700 (PDT), dgreig wrote: > >Unfortunataly unsigned to signed requires zero padding, adding the > >extra bit inferres a 18*18 block rather than 9*9. In the case of 18 > >bit inputs the unsigned to signed requires one more bit than the block > >actually has. > > What about Kolja Sulimma's suggestion of a conditional adder > after a =A017x18 multiply? =A0This is only a sketch, but shows > that it is quite neat both in VHDL code and in hardware: > > subtype S36 is signed(35 downto 0); > > function U18xS18 ( > =A0 U: unsigned(17 downto 0), > =A0 S: signed(17 downto 0) > ) return S36 is > =A0 variable product: S36; > begin > =A0 product :=3D signed'(U) * S; > =A0 if (U(17) =3D '1') then > =A0 =A0 product(35 downto 18) :=3D > =A0 =A0 =A0 product(35 downto 18) + signed'(U); > =A0 end if; > =A0 return product; > end; > > Disclaimer: I haven't tried synthesising this, and I suspect you > may need to play with the code some more to get the best > synthesis results. > -- > Jonathan Bromley Problem is more logic + routing + clock cycle latency. The dirty method altmult_accum at least makes best use of the resources and the 2 cycle latency is key to system throughput. System uses 282.5 out of 288 18*18 multipliers, 91% block ram and ~70% of logic elements. Still achieving a 25% timing margin on a mid speed device (slowest max is ~200MHz) and I am reluctant to push the boat out. The niggle is that apart from pll's and DDR2 specifics, the code would be otherwise transportable.Article: 147468
On 27 Nisan, 17:31, Bryan <bryan.fletc...@avnet.com> wrote: > Although based on an older version of ISE and MIG, you may find the > MIG designs posted by Avnet to be helpful. > > www.em.avnet.com/spartan3a-dsp--> Support Files & Downloads. > > Bryan Thanks for the responses guys. I have come across very interesting problems. @Gabor: I checked the pad report and I saw that wrong pins were being assigned for use. (ie: In the UCF file, NET "N5" is used, but the pad report uses a different pin and not N5) I don't know why this happens. Is there something wrong with timing constraints, etc? I have no idea! @RCIngham: I don't have any of the software mentioned on that thread. I am just trying to use, Xilinx ISIM (ISE Simulator), but I'm having trouble because it doesn't launch. @Bryan: I checked those designs, keeping in mind that I could use the UCF file. However, those designs use DCM and differential clock, so the UCF files are different. I tried using the UCF file from the Avnet design on my project, but as I mentioned before, in the pad report different pins are being used! Overall, I think the problem is with the UCF file.Article: 147469
On 26/04/2010 23:09, Wastrel wrote: > On Apr 25, 11:54 pm, David Brown<da...@westcontrol.removethisbit.com> > wrote: >> On 23/04/2010 21:39, Rich Webb wrote: >> >> >> >> >> >>> On Fri, 23 Apr 2010 10:19:07 -0700 (PDT), Wastrel >>> <stephensdigi...@gmail.com> wrote: >> >>>> On Apr 21, 1:08 pm, Jon Beniston<j...@beniston.com> wrote: >>>>> It's running ok for me on Windows 7 64-bit. >> >>>>> What particular part of the software are you having problems with? >> >>>>> Jon >> >>>> Well it installs alright, but Altium Designer 6 can't find it - >>>> whereas it did on my XP box. One problem is that Windows 7 likes to >>>> put 32 bit legacy programs under Program FIles(x86), but Quartus won't >>>> install there because it can't handle spaces or special characters in >>>> it's filenames. >> >>> Tell it to use the 8.3 name for the directory (one way of seeing this is >>> to do a "dir /X" from a command prompt). For the directory above, the >>> name would be "c:\progra~2\". >> >> Alternatively, avoid "Program Files" or "Program Files (x86)" like the >> plague - these are seriously stupid path names MS has chosen. >> >> When installing almost any new software, you have a free choice of the >> installation path - if you think you might ever want to refer to the >> program or its files by path name (such as the command line), use >> something like "c:\Progs\" as the base instead of "c:\Program Files". >> >> I have no idea whether this will help you here or not, but it will avoid >> the awkward installation path.- Hide quoted text - >> >> - Show quoted text - > > Well Altium support got back to me and said basically the same thing > you guys are: "It works OK for me" > > They told me to verify that the system environment variable > "QUARTUS_ROOTDIR" pointed to the right folder - it did. I upgraded the > OS to Windows 7 Professional from "Home Premium" still no joy. When I > run Windows' compatibility troubleshooter it comes back with > "Incompatible Application" so there's something funky going on. I'm > wasting way to much time on this stupid problem, but it's not so easy > finding an XP box anymore so I'm not just sure what my next move is. I know you've already found the answer, but this is just for completeness sake... There are some suppliers that still produce systems with XP installed - Dell being perhaps the best known. They refer to it as "Win 7 Pro downgraded to XP", and charge extra for it. I think of it as "Win 7 /upgraded/ to XP", and think it is worth the money. There are many tools in the embedded development world that don't play well with anything other than XP. Win 7 64-bit works better than XP 64-bit, so if you need more than 3.5 GB memory, Win 7 is a good choice. But other than that I have seen no reason to pick Win 7 over XP, and XP is always faster on the same hardware. As has been suggested, an alternative is to use virtual machines. I recommend Virtual Box - it's perhaps not quite as integrated as the "XP mode" of Win 7 Pro, but it is much more flexible. It's also free and cross-platform, and you can move the virtual machines between different hosts.Article: 147470
Am Tue, 27 Apr 2010 04:07:41 -0700 (PDT) schrieb Marc Jet <jetmarc@hotmail.com>: > Martin Br=FCckner wrote: > > void (*linux)(); > > ... > > (*linux)(); >=20 > Wouldn't the last line have to be just this? >=20 > linux(); The result of (*linux)() and linux() is the same.Article: 147471
Martin Br=FCckner wrote: > When I started with this project I was sure that Linux invalidates > caches Whatever Linux does, it doesn't matter unless the CPU is able to see and execute it.Article: 147472
On Tue, 27 Apr 2010 15:56:57 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >On Apr 27, 6:05 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >I don't agree that the two process model is inherently less >desirable. Or maybe I should say that I don't think describing >combinatorial logic outside of clocked processes is inherently less >desirable. Where there are combinatorial outputs to be described, I agree, I'll describe them outside the main process. But I can't remember the last time I had one so complex it needed a process of its own. > I seldom put a lot of combinatorial logic in processes, >clocked or unclocked, mainly because the structures in processes and >combinatorial logic are rather weighty (a synonym for verbose I >guess). But it always depends on the logic. Lacking the conditional >expression, VHDL concurrent logic can be a PITB to write complex >expressions in a clear manner. This means sometimes I put >combinatorial in unclocked processes because it is more clear. Simple >logic goes in with the clocked process, but when possible, I put >combinatorial logic in concurrent statements. I think you are referring to the ?: conditional operator inherited from C? I just use VHDL's conditional signal assignments for that purpose. As it's purely combinational, I have never found the need for an equivalent that I can use inside a process. I eventually figured out what I heartily detest about that (?:) - it's the ONE construct across all the languages I've encountered that expects the list of choices in descending order. (And does so implicitly as opposed to explicitly, with a "downto" or "step -1" or "when true else..." or some visible indication that it's doing something quaint) If VHDL is to adopt a conditional operator I hope it can do better than that! Something less surprising, and generalisable to other discrete types or at least other enums. If you are going to allow --------------------------------- Signal Flag : Boolean := True; Signal Int_val : Integer; Int_val <= Flag?1:0; --------------------------------- then you must surely allow similar expressions with other enumerations, for instance: --------------------------------- Type NTSC_Color is (red, green, blue); Signal Channel_Color : NTSC_Color; Signal Channel_Gain : real; Channel_Gain <= Channel_Color ? 0.11 : 0.55 : 0.34; -- nice and compact, but descending order to remain compatible with Boolean --------------------------------- Now I believe that ascending order, like every other positional list in the language (port lists, argument lists, etc), would be less surprising: Channel_Gain <= Channel_Color ? 0.34 : 0.55 : 0.11; There would of course be an associative form of the expression Channel_Gain <= Channel_Color ? red =>0.34 : green =>0.55 : blue=>0.11; to make the bugs harder to bury. In this context, is anyone still happy with the C-compatible version? However... in today's VHDL, if I ever needed ?: I would resort to a trivial function, and replace Int_val <= Flag?1:0; with Int_val <= cond(Flag,1,0); or even Int_val <= cond( test=>Flag, T=>1, F=>0 ); YMMV but for the sake of keeping the language relatively free of warts, I don't mind typing six extra characters. It's precisely that wart-free-ness that lets you extend it (e.g. by adding functions) in simple ways that actually work, instead of frustrating you. And it's precisely the remaining warts that limit the ability to extend it further. For example, the closed set of operators (a wart shared with most not-quite-object-oriented languages like C++) stops you naming the above function "?:" and writing Int_val <= "?:"( Flag,1, 0 ); to look that little bit more like Verilog or C. Or a better example: if you allowed types as generics, as Ada does, you could write the "?:" function once and use it to return different types. (Newer versions of C++ have this, as the template). >A foolish consistency is the hobgoblin of little minds, but there are >times when consistency is a good thing in engineering, other times >not. I guess I'm consistently inconsistent. Oh I'm inconsistent too, just not consistently so. I like "consistently inconsistent" - I suspect it would make the best description of the underlying design principles of C. (I don't know Verilog at all well, so won't extend the same courtesy to it!) - BrianArticle: 147473
On Wed, 28 Apr 2010 00:12:05 +0200, Martin Brückner <bj2spam@alice-dsl.net> wrote: >Am Tue, 27 Apr 2010 11:17:03 +0100 >schrieb Brian Drummond <brian_drummond@btconnect.com>: > >> On Tue, 27 Apr 2010 10:03:34 +0200, Martin Brückner >> <bj2spam@alice-dsl.net> wrote: >> >> > (*linux)(); >> >> >> >> With the assumption that data pointers can be properly >> >> cast to function pointers, that line should jump to >> >> location 0x4002b4 and start executing the code there. >> Xilinx example code typically has boilerplate to do things like >> invalidate caches and set up interrupt state before handing over to >> "real" code. >> Have you covered these bases in your own code? > >When I started with this project I was sure that Linux invalidates >caches and sets up the interrupt state a You are probably correct on interrupts, but on caches... >Anyway, all I tried out yet was disabling the cache but that did not >help. That would do it. Lets Linux invalidate, then enable them when safe. If that's not your problem, then I can't help further. The only other gotchas I remember are: (1) the interrupt vector table has to be on a 64k boundary. The tools let you put it anywhere but the bottom 16 address bits are chopped by the PPC! (2) Downloading a bitfile via Impact, there was one (probably V2Pro-specific) tick box that had to be set to reset the PPC correctly. The only reason I mention this was that starting via XMD worked correctly. - BrianArticle: 147474
On 28/04/2010 11:56, Brian Drummond wrote: > On Tue, 27 Apr 2010 15:56:57 -0700 (PDT), rickman<gnuarm@gmail.com> wrote: > >> On Apr 27, 6:05 am, Brian Drummond<brian_drumm...@btconnect.com> >> wrote: > <snip> > > I think you are referring to the ?: conditional operator inherited from C? > > I just use VHDL's conditional signal assignments for that purpose. As it's > purely combinational, I have never found the need for an equivalent that I can > use inside a process. > Hi Brian, just a little note - conditional signal assignment is allowed as a sequential statement in VHDL 2008 <snip> > > If VHDL is to adopt a conditional operator I hope it can do better than that! > Something less surprising, and generalisable to other discrete types or at least > other enums. And VHDL 2008 provides various matching operators that allow std_logic, bit and so on to be interpreted as Boolean - see http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/ If you're interested in VHDL 2008, I recommend the book "VHDL 2008 - Just the New Stuff" by Peter Ashenden and Jim Lewis. Now if only the tools supported ... regards Alan <snip> -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated.
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