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On Thu, 03 Nov 2016 08:29:33 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote: > >https://wattsupwiththat.com/2016/11/03/study-reveals-how-particles-that-seed-clouds-in-the-amazon-are-produced/ > >Not all science research is true (roughly half) but this one is great. >Trees dump gaseous organics into the air (presumably at some expense) >and those things go high, become nanoparticles, get swept down by >turbulence, and become raindrop seeds. > >So all the climate models up to now have been wrong. They will again. > >Nice planet. I meant to post that to another group, but you might find it interesting anyhow. -- John Larkin Highland Technology, Inc lunatic fringe electronicsArticle: 159426
> Again, why do you need four BRAMs? >=20 > Gene I need 4 ports (2 wr, 2 rd). Your 2-BRAM solution allows for 2 wr ports, b= ut only 1 rd port. In your solution you read A and B and the semaphore, th= en mux either A or B to your read data output based on the semaphore. But = I need a second read port, so I have to have a second copy of the system yo= u describe. I drew up a nice diagram with a good solution for doing the semaphores, but= I don't know how to post it here.Article: 159427
On 04.11.2016 3:35, Kevin Neilson wrote: >> Again, why do you need four BRAMs? >> >> Gene > > I need 4 ports (2 wr, 2 rd). Your 2-BRAM solution allows for 2 wr ports, but only 1 rd port. In your solution you read A and B and the semaphore, then mux either A or B to your read data output based on the semaphore. But I need a second read port, so I have to have a second copy of the system you describe. > > I drew up a nice diagram with a good solution for doing the semaphores, but I don't know how to post it here. > Thanks for explaining the rationale for using 4 BRAMs. Your solution would be surely interesting to look at. To post an image, you can just upload it to any image-hosting website like http://imgur.com and post here the link to your image. My best idea to remove logic from the design would be to append a timestamp to each writing operation (instead of switching a semaphore). During the read operation, the data word with the newest timestamp would be selected. But it would only work for the limited time, until the data field with the timestamp overflows. GeneArticle: 159428
On Friday, October 23, 2015 at 2:40:46 PM UTC-5, Kevin Neilson wrote: > I think I need a quad-port blockRAM in a Xilinx V7. Having multiple read= ports is no problem, but I need two read ports and two write ports. The t= wo write ports is the problem. I can't double the clock speed. To be clea= r, I need to be able to do two reads and two writes per cycle. (Not writes= to the same address.) >=20 > The only idea I could come up with is to have four dual-port BRAMs and a = semaphore array. Let's call the BRAMs AC, AD, BC, and BD. Writer A writes= the same value to address x in AC and AD and simultaneously sets the semap= hore of address x to point to 'A'. Now when reader C wants to read address= x, it reads AC and BC and the semaphore, sees that semaphore points toward= the A side, and uses the value from AC and discards BC. If writer B write= s to address x, it writes the value to both BC and BD and sets the semaphor= e x to point to side B. Reader D reads AD and BD and picks one based on th= e semaphore bit. >=20 > The semaphore itself is complicated. I think it would consists of 2 quad= -port RAMs, one bit wide and the depth of AC, each one having 1 write and 3= read ports. This could be distributed RAM. Writer A would read the side = B semaphore bit and set its own to the same, and writer B would read the si= de A bit and set its own to the opposite. Now when reader C or D read thei= r two copies (A/B) of the semaphore bits using their read ports, they check= if they are the same (use side A) or opposite (use side B). >=20 > It's a big mess and uses 4x the BRAMs as a dual-port. Maybe I need a dif= ferent solution. There is a literature on this subject: http://fpgacpu.ca/multiport/TRETS2014-LaForest-Article.pdfArticle: 159429
> Your solution would be surely interesting to look at. To post an image, > you can just upload it to any image-hosting website like > > http://imgur.com > > and post here the link to your image. > > My best idea to remove logic from the design would be to append a > timestamp to each writing operation (instead of switching a semaphore). > During the read operation, the data word with the newest timestamp would > be selected. But it would only work for the limited time, until the data > field with the timestamp overflows. > > Gene Thanks. Here's my sketch: http://imgur.com/a/NhNr0 The timestamp is a nice idea, but, like you said, it would overflow quickly. And you'd have a long carry chain to do the timestamp comparison.Article: 159430
> There is a literature on this subject: > http://fpgacpu.ca/multiport/TRETS2014-LaForest-Article.pdf Yes, I did actually find this yesterday when searching again. The design I= ended up using (http://imgur.com/a/NhNr0 ) looks like what they have in Fi= g. 3(a), except I implemented the "live value table" in BRAMs so it's much = faster. They have a faster solution in Fig. 4(c), which uses their "XOR-ba= sed" design. However, it requires a lot more RAM because you need 6 full d= ata storage units. I used only 4, and then two much smaller RAMs for semap= hores (aka Live Value Table), and I also store semaphore copies in the 4 da= ta RAMs.Article: 159431
I find this thread very interesting, it discusses quite some approaches I w= ould not have thought of in first place... Maybe a different view-point: As most modern FPGAs support true dual port R= AM, with double clock rate you could write to two ports in the first cycle = and read from both ports in the second cycle. This would only require 1 BRA= M compared to 4 BRAMs (assuming your content fits into 1 BRAM, of course...= ). However, you wrote that you cannot double the clock rate (out of curiosity:= which clock rates are we talking about?). But, maybe you could increase it= by 50%? Then you could make a 2/3 clock scheme with 2 BRAMs, with all the = writes going to both BRAMs (taking two of the 3 cycles), but the reads for = these two transactions (4 in total) are done in the 3rd cycle from both BRA= Ms. Of course this makes only sense if you can find a simple clock-domain-c= rossing-solution on system level... Regards, Thomas www.entner-electronics.com - Home of EEBlaster and JPEG-CodecArticle: 159432
On 05.11.2016 3:00, Kevin Neilson wrote: > >> Your solution would be surely interesting to look at. To post an image, >> you can just upload it to any image-hosting website like >> >> http://imgur.com >> >> and post here the link to your image. >> >> My best idea to remove logic from the design would be to append a >> timestamp to each writing operation (instead of switching a semaphore). >> During the read operation, the data word with the newest timestamp would >> be selected. But it would only work for the limited time, until the data >> field with the timestamp overflows. >> >> Gene > > Thanks. Here's my sketch: > > http://imgur.com/a/NhNr0 > > The timestamp is a nice idea, but, like you said, it would overflow quickly. And you'd have a long carry chain to do the timestamp comparison. > Great design! In terms of the referenced article, it combines the good features of both the LVT/semaphore approach (requires little memory to store semaphores), and the XOR-based approach (no need for multiport memory to store semaphores). I would only suggest, that like discussed at pp. 6-7 of LaForest article, it's possible to give user the impression there's no writing delay by adding some forwarding circuitry. GeneArticle: 159433
> I would only suggest, that like discussed at pp. 6-7 of LaForest=20 > article, it's possible to give user the impression there's no writing=20 > delay by adding some forwarding circuitry. >=20 > Gene I realized that since I'm doing read-modify-writes, I don't even need the e= xtra semaphore RAMs. Since I'm reading each address two cycles before writ= ing, I can get the semaphores from the data RAMs. When I'm doing a write o= nly, I can precede it by a dummy read to get the semaphores. The Xilinx BRAMs operate at the same speed for write-first and read-first m= odes, so I probably wouldn't need the forwarding logic. (The setup time is= a lot bigger for write-first mode, though.) However, I do need a short "l= ocal cache" for when I try to read-modify-write the same location on succes= sive cycles. Because of the read latency, the second read would be of stal= e data so I have to read from the local cache instead.Article: 159434
There is a paper that describes your approach, published by my Ph.D. student Ameer Abdelhadi at FPGA2014. He has also extended it to include switched ports, where some ports can dynamically switch between read and write mode at FCCM2016. http://ece.ubc.ca/~ameer/publications.html He has released the designs on GitHub under a permissive open source license. https://github.com/AmeerAbdelhadi/Switched-Multiported-RAM GuyArticle: 159435
My Ph.D. Ameer added forwarding paths to his version, available on GitHub. See papers at FPGA2014 and FCCM2016. http://ece.ubc.ca/~ameer/publications.html https://github.com/AmeerAbdelhadi/Multiported-RAMArticle: 159436
> Maybe a different view-point: As most modern FPGAs support true dual port= RAM, with double clock=20 > However, you wrote that you cannot double the clock rate (out of curiosit= y: which clock rates are we talking about?). But, maybe you could increase = it by 50%? Then you could make a 2/3 clock scheme with 2 BRAMs, with all th= e writes going to both BRAMs (taking two of the 3 cycles), but the reads fo= r these two transactions (4 in total) are done in the 3rd cycle from both B= RAMs. Of course this makes only sense if you can find a simple clock-domain= -crossing-solution on system level... >=20 > Regards, >=20 > Thomas > www.entner-electronics.com - Home of EEBlaster and JPEG-Codec That's a great idea. It took me a few minutes to work through this but tha= t seems like it would work. The clock I'm using now is 360MHz so a 1.5x cl= ock would be 540MHz. That's pushing the edge, but Xilinx says the BRAM wil= l run at 543MHz in a -2 part. The clock-domain crossing shouldn't be a pro= blem. The clocks are "periodic-synchronous" so you have a known setup time= . (Assuming you use DLLs to keep them phase-locked.) Xilinx does have an old app note ( https://www.xilinx.com/support/documenta= tion/application_notes/xapp228.pdf ) on using a 2x clock to make a quad-por= t. In my case the 2x clock would be 720MHzArticle: 159437
> I realized that since I'm doing read-modify-writes, I don't even need the= extra semaphore RAMs. Since I'm reading each address two cycles before wr= iting, I can get the semaphores from the data RAMs. When I'm doing a write= only, I can precede it by a dummy read to get the semaphores. >=20 I added a diagram of the simplified R-M-W quad-port to that link. http://i= mgur.com/a/NhNr0Article: 159438
On Saturday, November 5, 2016 at 11:35:20 AM UTC-6, Guy Lemieux wrote:
> There is a paper that describes your approach, published by my Ph.D. stud=
ent Ameer Abdelhadi at FPGA2014. He has also extended it to include switche=
d ports, where some ports can dynamically switch between read and write mod=
e at FCCM2016.
>=20
> http://ece.ubc.ca/~ameer/publications.html
>=20
> He has released the designs on GitHub under a permissive open source lice=
nse.=20
>=20
> https://github.com/AmeerAbdelhadi/Switched-Multiported-RAM
>=20
> Guy
Thanks; I enjoyed looking through the papers. The idea of dynamically swit=
ching the write ports to reads is one I might need to use at some point.
The main difference in my diagram is that I implemented part of the I-LVT i=
n the data RAMs. For example, for a 2W/2R memory, you show the I-LVT RAMs =
as being 1 write, 3 reads. My I-LVTs are 1 write, 1 read, with the rest of=
the I-LVT done in the data RAMs. In my case, I need 69-wide BRAMs, and th=
e BRAMs are 72 bits wide, so I have an extra 3 bits. I use one of those bi=
ts as the I-LVT ("semaphore") bit. When I do a read, I don't have to acces=
s a separate I-LVT RAM.
Article: 159439I having issue with compiling from centos for ARM processor I made change t= o Cmakelist and toolchain file so far not luck. I can compile and run on ce= ntos but cross compile does not work. Can someone provide me cmakelist file= and toolchain.cmake file. I don't understand the cmake I preffered make fi= le. thanksArticle: 159440
Hi, I should have probably sent this question to the VHDL newsgrp but since it = has low activity, I've decided to send it here. It is well documented that processes should be used to code sequential syst= ems. The texbook gives an example of a D latch/flip flip. With FPGA tools, = i have to use a process so the tool makes use of the available on-chip flip= flops. But i wonder what if I describe a D latch and flip flop without the= use of process: e.g.=20 1- latch: Q<=3DD when Clk=3D'1'; (will this be triggered each time clk cha= nges to 1 even if D does not change?) 2- flip flop: Q<=3DD when rising_edge(Clk); (the same question as above) Is anything wrong with the above code? Thank youArticle: 159441
On Thursday, November 10, 2016 at 9:50:38 AM UTC-5, Karl wrote: > Hi, > I should have probably sent this question to the VHDL newsgrp but since i= t has low activity, I've decided to send it here. >=20 > It is well documented that processes should be used to code sequential sy= stems. The texbook gives an example of a D latch/flip flip. With FPGA tools= , i have to use a process so the tool makes use of the available on-chip fl= ip flops. But i wonder what if I describe a D latch and flip flop without t= he use of process: > e.g.=20 > 1- latch: Q<=3DD when Clk=3D'1'; (will this be triggered each time clk c= hanges to 1 even if D does not change?) > 2- flip flop: Q<=3DD when rising_edge(Clk); (the same question as above) >=20 #1 will work as a latch; #2 will work as a flip flop. Both lines of code w= ill be triggered upon any change on either D or Clk. But just because the = code gets triggered and executed does not imply that Q gets updated. #1 wi= ll only update if Clk=3D1; #2 will only update when rising_edge(Clk) is tru= e. At any other time there is no update to Q simply because there is no 'e= lse ...' clause (which there shouldn't be for either a latch or flip flop). > Is anything wrong with the above code? >=20 The code is fine, your apparent desire to use a latch in an FPGA design wil= l cause you problems if you implement. Kevin JenningsArticle: 159442
On 11/10/2016 9:50 AM, Karl wrote: > Hi, > I should have probably sent this question to the VHDL newsgrp but since it has low activity, I've decided to send it here. > > It is well documented that processes should be used to code sequential systems. The texbook gives an example of a D latch/flip flip. With FPGA tools, i have to use a process so the tool makes use of the available on-chip flip flops. But i wonder what if I describe a D latch and flip flop without the use of process: > e.g. > 1- latch: Q<=D when Clk='1'; (will this be triggered each time clk changes to 1 even if D does not change?) > 2- flip flop: Q<=D when rising_edge(Clk); (the same question as above) > > Is anything wrong with the above code? From what you wrote, the issue you fail to understand is that every concurrent statement is a process. That is why they are concurrent, each concurrent statement runs as a separate process. In fact, what makes a process statement a process is that it is a concurrent statement. What the process statement does is to tell the tool to stop treating the following lines as processes, rather treat them as sequential statements within the current process. So why do you not want to use a process statement to define a FF? To answer your question, as KJ wrote, each of your examples define a type of register. When a signal level is used as the trigger it defines a latch. When a signal edge is used as the trigger it defines an edge sensitive FF. Seems rather obvious, no? -- Rick CArticle: 159443
Thank you KJ and Rickman for your answers. I wanted to confirm that the cod= es are correct because in the notes I am reading it stated that flip flops = /latches are coded in VHDL using a process...given your answer, it is one w= ay to do it but not the only oneArticle: 159444
On Sunday, October 30, 2016 at 11:58:56 AM UTC-4, Svenn Are Bjerkem wrote: > > I would appreciate your opinions and comments. > > What immediately comes to my mind is getting the absolute file path of the .tim file to be able to use the location of that file as storage for output from python scripts. > > I use your tool quite often to build vhdl testbenches. So far I use the cpp c-pre-processor to be able to include the vhdl output of the python script into the testbench vhdl. > > -- > Svenn Ok. I will add that function to the python api. I'm glad to hear you use it for vhdl test vectors. Thanks for your feedback, DanArticle: 159445
For those that haven't seen it: https://www.bloomberg.com/news/articles/2016-11-14/siemens-to-buy-mentor-graphics-of-the-u-s-for-4-5-billion Never thought Siemens would be interested in an EDA company. Hans www.ht-lab.comArticle: 159446
On 11/14/2016 8:00 AM, HT-Lab wrote: > For those that haven't seen it: > > https://www.bloomberg.com/news/articles/2016-11-14/siemens-to-buy-mentor-graphics-of-the-u-s-for-4-5-billion > > > Never thought Siemens would be interested in an EDA company. Personally, I'm not too worried about what happens with Mentor. I saw their products when they were just getting started and have never used any of them since. I guess I just don't have much need for expensive commercial tools when I can use free tools from the chip vendors. But then I don't work on large projects with multiple designers. -- Rick CArticle: 159447
I have version 11.6 running on my laptop with Windows 8. For a workshop tomorrow I need to update to version 11.7 service pack 2. I downloaded the software and started to install it, but I can't get past the initial directory creation. It actually makes the directory just fine, but the tool then complains this is not a valid directory. I've tried using different locations and changed the directory name to remove any special characters with no success. Any ideas? -- Rick CArticle: 159448
On Mon, 14 Nov 2016 23:14:20 -0500, rickman wrote: > I have version 11.6 running on my laptop with Windows 8. For a workshop > tomorrow I need to update to version 11.7 service pack 2. I downloaded > the software and started to install it, but I can't get past the initial > directory creation. It actually makes the directory just fine, but the > tool then complains this is not a valid directory. > > I've tried using different locations and changed the directory name to > remove any special characters with no success. > > Any ideas? Dunno Windows much -- are you logged in as an administrator? Can't help you much more than that: my IT brain is at choir practice right now. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.comArticle: 159449
Tim Wescott <tim@seemywebsite.com> Wrote in message: > On Mon, 14 Nov 2016 23:14:20 -0500, rickman wrote: > >> I have version 11.6 running on my laptop with Windows 8. For a workshop >> tomorrow I need to update to version 11.7 service pack 2. I downloaded >> the software and started to install it, but I can't get past the initial >> directory creation. It actually makes the directory just fine, but the >> tool then complains this is not a valid directory. >> >> I've tried using different locations and changed the directory name to >> remove any special characters with no success. >> >> Any ideas? > > Dunno Windows much -- are you logged in as an administrator? Can't help > you much more than that: my IT brain is at choir practice right now. > > -- > Tim Wescott > Control systems, embedded software and circuit design > I'm looking for work! See my website if you're interested > http://www.wescottdesign.com > #1 son says you can right-click an executable, get a menu, and run as administrator, but had nothing else in the way of stunning cleverness. -- www.wescottdesign.com
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Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z