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Hi Govind,
I don't get this error message.
I get two warnings about (mini_test.hcc Ln 232, Col 72-83: Passing
Handel-C type through '...' - cannot automatically check types
) but it builds fine.
What version of DK1 are you using? The latest is 1.1 SP1.
Ashley
govind.kharbanda@sli-institute.ac.uk (Govind Kharbanda) wrote in message news:<2f5db38d.0209180713.503b2f62@posting.google.com>...
> I've discovered that if I try and call a macro proc within a
> complicated loop I get the following error (compiling for Debug):
>
> mini_test.hcc
> 0 errors, 0 warnings
>
> mini mdct
> NAND gates after compilation : 5764272 (17062 FFs, 10752 memory bits)
> [Bomb icon] C:\Development\Tools\Compiler\hccompile\main\main.cpp(232)
> : Unhandled exception
> [Bomb icon] uncaught exception in compiler [CCompilerDll::Compile,
> D:\Tools\ide\esl\vhc\CompilerDll.cpp]
>
> Ignoring the mammoth gate count for now (will need to optimise
> somehow), here is the offending snippet of code:
>
> /*
> * Following lines are a little tricky:
> * originally stated:
> *
> * for (i=1; --stages>0; i++){
> * for (j=0; j<(1<<i);j++)
> * mdct_butterfly_generic(T,x+(points>>i)*j),points>>i,4<<i);
> * }
> */
>
> i = 2;
> k = points >> 1; /* points = 128, so k = 64 */
>
> #ifdef SIMULATE
> printf("mdct_butterflies: k = points >> 1 = %d",k);
> /* prints 64 correctly */
> #endif
>
> do{
> par
> {
> j=0;
> do{
> par
> {
> /* params are T [w=9], x [w=8], points [w=8], trigint [w=9]*/
>
> /*
> * call macro proc
> */
> mdct_butterfly_generic(T,x+(k*j),k,0 @ (4*i) );
> j++;
> }
> }while(j < i);
>
> stages--;
> i = i << 1;
> k = k >> 1;
> } /* end of par */
>
> }while(stages>1);
>
> Now if I comment out the call to mdct_butterfly_generic the uncaught
> exception is not generated and the code works as it ought to.
> mdct_butterfly_generic expects four parameters T, x, points, trigint
> of the widths shown, and i, j and k are all unsigned 8
>
> In case anyone would like to play with the full code it is at
>
> http://www.sli-institute.ac.uk/~gk/mdct.zip
> (the project is mini mdct and the hcc file is mini_test.hcc)
>
> Cheers,
> Govind
Article: 47476You might also look at http://www.tech-forge.com for a PCI interface option using Altera parts. For a USB option there was a general purpose IO USB1.0 solution kit advertized in Circuit Cellar (www.circuitcellar.com) for about $50. However then you need to interface the FPGA to it and suffer the lower bandwidth (<12MHz) of USB1.0. USB2.0 supports up to 480MHz, but I have not seen any FPGA kits using it. Another option is to put USB IP in your FPGA, possibly using something like www.opencores.org. Best luck, -Steen newb <n/a@ee.net> wrote in message news:<ee791fd.-1@WebX.sUN8CHnE>... > Hello, > > I am interested in integrating a virtual cpu that can take instructions from a pc and then compute them within the fpga, then return the computed result back to the computer. I would like to know if anyone could suggest a fpga evaluation kit that would be ideal for this situation. Thank you.Article: 47477
nagaraj@accord-soft.com (Nagaraj) wrote in news:9c782518.0209260147.31279e0c@posting.google.com: > Dear group members, > I am using Dual Port BlockRAM (of CoreGen IP)in my design (Xilinx > Virtex device). Now my system requirement is such that the DPRAM > should reside outside the FPGA. > I am searching for a Dual Port SRAM IC which is similar to the Dual > Port Block RAM (of CoreGen IP). Except for the functionality > (enable,reset etc.), other things like memory size, physical > size,cost,timing doesn't matter for me. > Could somebody please help in knowing the availability of an IC > atleast close to my requirement? > > Regards, > Nagaraj CS IDT (www.idt.com ) has got that sort of thing. Never used it though, so I can't give further advice. They come in asynchronous and isochronous flavors. hth Sylvain YonArticle: 47478
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3D924286.1F3F4A5@andraka.com... > It sounds like his image is too big to do a corner turn in on-chip memory. > Without doing clever things he pretty much is stuck with single word writes. How about this? Split the image into small areas that can be rotated inside the FPGA (lets say 8x8 pixel). So on the first run, you store the image inside the SDRAM using a normal line by line access doing nice fast bursts. Then you read the small sub-images, and when you write them back you rotate and relocate them. After this, you can read back the image rotated. Yes, this requires one additional complete read and one additional write access for the whole picture, but since you can do this with bursts, it may be faster. -- MfG FalkArticle: 47479
Kon-nichi-wa, Talking about clock period, -4 (slowest) grade is enough, I think. In my case, I met some timing errors at SLR16 primitive module in a 250MHz DDR design with -4 grade. -5 was OK. Good Luck! -- ------------------------- DOHI, Yutaka mailto: y_dohi@hotmail.com http://www4.justnet.ne.jp/~dohi/ "Martin E." <0_0_0_0_@pacbell.net> wrote in message news:LXEk9.3622$fy1.71553159@newssvr14.news.prodigy.com... > I have a design that will interface an XC2V1000 to a block of SDRAM running > at 133MHz as well as a DVI (Digital Video Interface) chip requiring a 24 bit > bus at up to 165MHz. I'm looking for guidance as to what speed grade > VirtexII device should work for such a design. > > I can always start with the fastest and then try lower speed grades and see. > I'm just wondering if anyone with experience in similar designs might have a > bit of advise to offer. > > Thank, > > > -- > Martin E. > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 47480
"Valentin Tihomirov" <valentin@abelectron.com> ha scritto nel messaggio news:3d92f432_1@news.estpak.ee... > stimulate the device > manually resetting the boundry scan controller (TRST > sequence) and capturing > (all 1s) instruction as described in Xilinx > Troubleshooting guide > (http://toolbox.xilinx.com/docsan/3_1i/data/common/jtg/dpp > c/appc.htm#BHAICAB > I). And now the chip is consuming so much power that LED > on the power supply > stops ligting. It should be a latch-up problem. Have you tied some signals to Vcc? Have you left unconnected some Vio, Vcore or GND pins? -- LorenzoArticle: 47481
--------------C84614F4BFF24E2DF773448F Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit David, Any type of input primitve (IBUFs or some pins on the GT primitives in the Virtex-II Pro) that is instantiated with its input left unconnected will get grounded by XST and cause the error that you mentioned. Solution 13206 should have some hints. If you find that your problem is not described in this solution open a case with our hotline. http://support.xilinx.com/support/clearexpress/websupport.htm Steve David R Brooks wrote: > Running the Xilinx ISE 4.2i tools, I get a warning > ERROR:NgdBuild:455 - logical net 'N812' has multiple drivers > > Now the meaning is obvious enough, but the problem is, how to locate > this net (it is a synthesiser-generated name) in the hierarchy. The > tools don't give any indication where it is located. It is a large > project, with over 40 VHDL design elements in a deep hierarchy. > > A search of the output files shows none of them contain this string, > except the NGD log, which only contains the error as above. > > This error causes no post-synthesis VHDL file to be generated, else > one could search that file for the net. > > Any ideas?Article: 47482
What you gonna do with the dead virtex? I have some dead pentium here, but xilinx...Article: 47483
Wow! Learned a lot today.
1. First off my speed numbers aren't real: my speed files are
considerably
out of date (1.85 from 7-24-01).
2. I worked through XAPP636 and implemented the VHDL versions of
MULT16x16
and MULT16x16S in a test module. For my obsolete speedfiles I get
6.375ns for MULT16x16
3.595ns for MULT16x16S
(7.656ns previous best)
Only problem is that using MULT16x16(S)_PLUS.vhd from the AppNote, I
can't get the functional simulation to behave: simulation works if I
change the inputs
every 2nd clock or slower, but if the input holds for just 1 clock,
the outputs
aren't updated :-( I read the answers about VHDL pulse-swallowing in
VHDL simulation, and tried slowing down my simulation clock, but to no
avail. And I don't have this problem with LogiCore multipliers, it
seems to be something with
the MULT16x16(S)_PLUS.vhd...
3. So I went back to my LogiCore multiplier (16x16, input register,
output
register) and regenerated it with create_RPM=OFF. I floorplanned the
I/O registers just like in xapp636, and got my 6.375ns just like with
MULT16x16_PLUS.vhd. And it simulates fine.
So here's my questions...
Q.1. Any idea what my problem with the MULT16x16(S)_PLUS simulation
might be ?
Q.2. How come the LogiCore multiplier RPM doesn't do a better job
locating the
FFs ? Do newer versions of LogiCore do a better job... or can one
make them do
a better job by adding, say, a simple RLOC_ORIGIN constraint ?
Q.3. What's with the slowing down of multiplier delays in the newer
speed files ? Does this reflect (a) better knowledge of mfg process
variations (b)
loosening of the process tolerances over time (c) other ?
Thanks in advance,
-rajeev-
--------------------
Yenni Totong <yenni.totong@xilinx.com> wrote in message news:<3D924750.2CF315D8@xilinx.com>...
> Reference :
> http://www.xilinx.com/xapp/xapp636.pdf
>
>
> Ray Andraka wrote:
>
> > YOu get a bit more by carefully placing the flip-flops around the multiplier so
> > that each gets a direct connect to the multiplier rather than having to go
> > through extra pips to get there. You'll have to go into the FPGA editor to
> > figure out where those need to go. THere may be an app note on the xilinx
> > website detailing that placement for max performance, I know it had been talked
> > about.
> >
> > Rajeev wrote:
> >
> > > I'm dealing with timing on a 300-slice design with 2 block RAM and 2 block
> > > Multipliers. I'm looking at the Post-Place-and-Route Static Timing Analyzer.
> > >
> > > I added output registers on the block RAMs to bring the Min Period down from
> > > 9.6ns to 7.8ns, now my slowest paths are internal to the Block Multipliers
> > > (Tmult=4.121ns plus 2 nets plus FFin/outs).
> > >
> > > Is this it, or is there anything I can do to make it faster in this speed
> > > grade ? I don't want to increase the multiplier latency, as I'm working with
> > > an iterative algorithm and the multiplier output gets fed back to the input.
> > >
> > > Also, I've seen variations on the _internal_ path delays from 7.827 to 8.041
> > > ns. How is this possible ?
> > >
> > > Thanks,
> > > -rajeev-
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
Article: 47484Wakarimasu. Arigato. -Martin "dohi" <y_dohi@hotmail.com> wrote in message news:amvj60$2trd$1@news.rim.or.jp... > Kon-nichi-wa, > > Talking about clock period, -4 (slowest) grade is enough, I think. > In my case, I met some timing errors at SLR16 primitive module > in a 250MHz DDR design with -4 grade. -5 was OK. > > Good Luck! > > > -- > ------------------------- > DOHI, Yutaka > mailto: y_dohi@hotmail.com > http://www4.justnet.ne.jp/~dohi/ > > > "Martin E." <0_0_0_0_@pacbell.net> wrote in message > news:LXEk9.3622$fy1.71553159@newssvr14.news.prodigy.com... > > I have a design that will interface an XC2V1000 to a block of SDRAM > running > > at 133MHz as well as a DVI (Digital Video Interface) chip requiring a 24 > bit > > bus at up to 165MHz. I'm looking for guidance as to what speed grade > > VirtexII device should work for such a design. > > > > I can always start with the fastest and then try lower speed grades and > see. > > I'm just wondering if anyone with experience in similar designs might have > a > > bit of advise to offer. > > > > Thank, > > > > > > -- > > Martin E. > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu" > > > > >Article: 47485
Does anyone have the ISR switch and release times for Nios? Ideally for Nios 2.1? -- PeteArticle: 47486
Lorenzo Lutti wrote: > "Christopher Saunter" <christopher.saunter@durham.ac.uk> ha scritto nel > messaggio news:ampepb$773$1@sirius.dur.ac.uk... > > > I have also been learning (to tolerate ;-) VHDL recently. > > I'm going to hate it. I thought I never saw again that horrible Pascal > syntax... :) > > There are some C-oriented syntesis languages (ABEL, for example), but I > think it's more useful to obey the most known and supported standard, > which is VHDL (if I'm not wrong - please, tell me I am! :-)). What about Verilog ? Much easier to learn, no bad memories of Pascal (which I also shudder to remember). IIRC the Verilog/VHDL overall useage ratio is 45/55 with Verilog being much more commonly used in the US and VHDL more common in Europe.Article: 47487
Hi, The website of the CPCNG project (a new computer based on eZ80) has been updated. It is available in english, french and german. There is a forum where you can meet the team and discuss about CPCNG. We search actually FPGA dev, don't hesitate to join us ! Our adress : www.cpcng.org Regards, ChrisArticle: 47488
I intend to implement adaptive FIR(LMS) with 100~600 inputs. I need to update within every 100ms, number of filter tap is 10, input precision is 8bits, and coef. precision is 8bits. Is it hard to implement with ALTERA(especially updating coef.)? How about with Stratix? Is it same? donghoArticle: 47489
Jarmo <jarmoma@REMTHIS.mail.student.oulu.fi> wrote in message news:<Pine.GSO.4.44.0209251113310.11071-100000@paju.oulu.fi>... > Hey > > I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. > Problem is that I don't find any datasheet telling me how to do the > powering for the Altera. Should I add decoupling capasitors and what > values they should be? > Just generally speaking for board layout FPGAs will be similar to more specialized chips. You may find good general PCB guidelines in app notes from the major silicon vendors (they want you to be successfull in order to buy more of their silicon). Decoupling caps are certainly a good idea. Generally put a larger bulk cap >100uF someplace on the board to remove slow voltage variations. Put smaller .1uF caps close to the chip power/gnd signals to remove high frequency oscillations. If you are doing the board, put as many pads as you easily can, and you can populate appropriately later on based on oscilloscope readings. > Is there internal clock in Altera or should I add a crystall to my PCB? > Unless you have an external clock source or doing a design that is totally asynchronous, you will need either a crystal or clock driver. > If you are wondering why I want to use OLD Altera Flex 8000, because I > want to add only 2 layers to my PCB. I think that new Alteras need > separate power and ground layers, so 2 layers is not enough. > I am finishing a PCI 33MHz board (www.tech-forge.com) with two layers and have not seen much of a power decoupling problem. (Plenty of design problems though!) > is there some websites/tutorials how to do PCBs for FPGAs? > I would look at how other boards with FPGAs are done, such as www.optimagic.com Good luck, -SteenArticle: 47490
Rajeev wrote: > Wow! Learned a lot today. > > 1. First off my speed numbers aren't real: my speed files are > considerably > out of date (1.85 from 7-24-01). > > 2. I worked through XAPP636 and implemented the VHDL versions of > MULT16x16 > and MULT16x16S in a test module. For my obsolete speedfiles I get > 6.375ns for MULT16x16 > 3.595ns for MULT16x16S > (7.656ns previous best) > Only problem is that using MULT16x16(S)_PLUS.vhd from the AppNote, I > can't get the functional simulation to behave: simulation works if I > change the inputs > every 2nd clock or slower, but if the input holds for just 1 clock, > the outputs > aren't updated :-( I read the answers about VHDL pulse-swallowing in > VHDL simulation, and tried slowing down my simulation clock, but to no > avail. And I don't have this problem with LogiCore multipliers, it > seems to be something with > the MULT16x16(S)_PLUS.vhd... > > 3. So I went back to my LogiCore multiplier (16x16, input register, > output > register) and regenerated it with create_RPM=OFF. I floorplanned the > I/O registers just like in xapp636, and got my 6.375ns just like with > MULT16x16_PLUS.vhd. And it simulates fine. > > So here's my questions... > > Q.1. Any idea what my problem with the MULT16x16(S)_PLUS simulation > might be ? > I'm not sure , but I would refer you to Xilinx hotline. You can open a webcase at http://support.xilinx.com, and describe the issue. An engineer will be assigned to look into this. > > Q.2. How come the LogiCore multiplier RPM doesn't do a better job > locating the > FFs ? Do newer versions of LogiCore do a better job... or can one > make them do > a better job by adding, say, a simple RLOC_ORIGIN constraint ? > Thanks for the feedback. I'll forward it to Logicore group. > > Q.3. What's with the slowing down of multiplier delays in the newer > speed files ? Does this reflect (a) better knowledge of mfg process > variations (b) > loosening of the process tolerances over time (c) other ? If the delays change, it will be by a better knowledge over PVT. I'm not sure which speed you are referring to. Some device correspond with stepping level 0 and some with stepping level 1. The latest delay in speed file should correspond with the number in our datasheet. http://support.xilinx.com/partinfo/databook.htm We also have an answer record describing the stepping level, try search for 'stepping' in answer database. I would also refer to Xilinx hotline for more info on this. 'Hope this helps. Regards, Yenni > > > Thanks in advance, > -rajeev- > -------------------- > > Yenni Totong <yenni.totong@xilinx.com> wrote in message news:<3D924750.2CF315D8@xilinx.com>... > > Reference : > > http://www.xilinx.com/xapp/xapp636.pdf > > > > > > Ray Andraka wrote: > > > > > YOu get a bit more by carefully placing the flip-flops around the multiplier so > > > that each gets a direct connect to the multiplier rather than having to go > > > through extra pips to get there. You'll have to go into the FPGA editor to > > > figure out where those need to go. THere may be an app note on the xilinx > > > website detailing that placement for max performance, I know it had been talked > > > about. > > > > > > Rajeev wrote: > > > > > > > I'm dealing with timing on a 300-slice design with 2 block RAM and 2 block > > > > Multipliers. I'm looking at the Post-Place-and-Route Static Timing Analyzer. > > > > > > > > I added output registers on the block RAMs to bring the Min Period down from > > > > 9.6ns to 7.8ns, now my slowest paths are internal to the Block Multipliers > > > > (Tmult=4.121ns plus 2 nets plus FFin/outs). > > > > > > > > Is this it, or is there anything I can do to make it faster in this speed > > > > grade ? I don't want to increase the multiplier latency, as I'm working with > > > > an iterative algorithm and the multiplier output gets fed back to the input. > > > > > > > > Also, I've seen variations on the _internal_ path delays from 7.827 to 8.041 > > > > ns. How is this possible ? > > > > > > > > Thanks, > > > > -rajeev- > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759Article: 47491
ChristopheGuelff wrote: > > Hi, > > The website of the CPCNG project (a new computer based on eZ80) has been > updated. It is available in english, french and german. > > There is a forum where you can meet the team and discuss about CPCNG. > > We search actually FPGA dev, don't hesitate to join us ! You should perhaps clarify WHAT you seek to develop in fpga, and a little about the 'new computer' target. ( there was activity to emulate Sinclair ZX81 .. ? ) > Our adress : www.cpcng.org this seems to not work ? -jgArticle: 47492
kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0209250740.5b7e7614@posting.google.com>... > The package is a really a small part of the cost of these chips. [... snip rest ...] I guess it all depends on what you consider to be "small." To get more LUTs than is in an XC2V3000, the only package offered is a flip-chip. That's a 20% price hike (I just verified this). Add that to the fact it takes up 70% more area, and you have the reason that I can't make that move. Have fun, MarcArticle: 47493
Allow me to add my two cents worth. I have been designing PCBs with all sorts of chips for a long time and I have not found any compelling reasons to change the way I do decoupling on any but the most speciallized designs. For an Altera 8000 series part I would recommend that you use one 0.1 uF ceramic cap in the 0603 package for each power pin on the chip. The cap should be situated so that the loop from the power pin through the trace, cap, trace and to the ground pin (and of course the path inside the chip which you can't see but can approximate with a straight line) has the minimum area. For SOIC and QFPs this means finding power and ground pins close to one another for each cap. On fancier packages like BGAs and chip scale packaging it is often required that you put the chip on one side of the board and the caps on the other. You will have some added inductance from the vias, but this will be small compared to the long path to get outside the chip footprint working on the same side of the board. Some designers like to use a combination of 0.1, 0.01 and even 0.001 ceramic caps since they have different resonant frequencies and conceptually can provide a very low ESR over a wider freq range. But they can also interact in unpredictable ways and produce anti-resonances where you might not expect. So I avoid this practice. Then add a single tantalum or electrolytic bulk cap for the entire board. I can't say how large as that will depend on the rest of your circuit. But a 100 uF will normally do. Some designers like to scatter around bulk caps, but that is pointless since they have high inductance and ESR at the higher frequencies. At the lower frequencies (<1 MHz) they have lower ESR and the circuit board path is of no (or very little) consequence. So one larger one is as good a several smaller ones unless you are trying to lower the internal ESR of the cap by using parallel bulk caps. Normally is is cheaper to use a single low ESR part than several higher ESR caps and you can save board space. So unless you are running GHz designs or are switching high voltage or high current (and I am not talking about the 50 to 100 mA from switching bus signals) you will be well served by the outline above. Just keep the loops small for your 0.1 uF ceramics and you will have working boards. Steen Larsen wrote: > > Jarmo <jarmoma@REMTHIS.mail.student.oulu.fi> wrote in message news:<Pine.GSO.4.44.0209251113310.11071-100000@paju.oulu.fi>... > > Hey > > > > I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. > > Problem is that I don't find any datasheet telling me how to do the > > powering for the Altera. Should I add decoupling capasitors and what > > values they should be? > > > Just generally speaking for board layout FPGAs will be similar to more > specialized chips. You may find good general PCB guidelines in app > notes from the major silicon vendors (they want you to be successfull > in order to buy more of their silicon). Decoupling caps are certainly > a good idea. Generally put a larger bulk cap >100uF someplace on the > board to remove slow voltage variations. Put smaller .1uF caps close > to the chip power/gnd signals to remove high frequency oscillations. > If you are doing the board, put as many pads as you easily can, and > you can populate appropriately later on based on oscilloscope > readings. > > > Is there internal clock in Altera or should I add a crystall to my PCB? > > > Unless you have an external clock source or doing a design that is > totally asynchronous, you will need either a crystal or clock driver. > > > If you are wondering why I want to use OLD Altera Flex 8000, because I > > want to add only 2 layers to my PCB. I think that new Alteras need > > separate power and ground layers, so 2 layers is not enough. > > > > I am finishing a PCI 33MHz board (www.tech-forge.com) with two layers > and have not seen much of a power decoupling problem. (Plenty of > design problems though!) > > > is there some websites/tutorials how to do PCBs for FPGAs? > > > I would look at how other boards with FPGAs are done, such as > www.optimagic.com > > Good luck, > -Steen -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47494
If www.cpcng.org doesn't work, please try http://cpcng.kriga.net or http://www.cpcng.com Concerning the FPGA job : We don't know how FPGA(s) we must put on the board : this depends on the type of FPGA chosen and how many I/O pins and gates the FPGA requires. Ideally we need someone able to design and debug the FPGA and able to give some idea of how many FPGA's will likely be required. My feeling is that we need quite a few FPGA I/O lines, a large number relative to the amount of logic gates required - to avoid going for an expensive FPGA or one a very high density e.g. BGA package, we should perhaps choose 2 FPGA's. We need someone able to program the FPGA and choose as soon as possible how FPGA we need. What the FPGA must contains is described on our prototype's webpage http://www.arnold6.com or http://www.hanssummers.com/computers/cpcng Concerning the project : Our aim is to build a free sucessor of the Amstrad464/6128 computer range by using ez80 and with somes enhanced video and sound capabilities, a new OS etc. Regards, Chris www.cpcng.orgArticle: 47495
Not free, but cheap and dead unless you reball 'em: http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=1771334936 David wrote: > Hello, > > I'm looking for a really dead virtex. Is anybody have one or several > dead virtex to give to me ? > > Thanks in advance. > > DavidArticle: 47496
I should correct myself.... I was very tired when I made my original post. The _synthesis_ tool is passing constraints it comes up with onto the Xilinx P&R tool. These constraints are making the timing fail. It was inferring constraints that may not have been real. I believe I unchecked a box in the Xilinx Gui that stopped the synthesis tool from writing a .ncf file and I deleted the one that was existing. I learned that the .ncf file is "sticky" and each time the synthesis tool runs, it just appends more and more constraints to the file, making the design harder to P&R. I ended up with a .ucf file that nailed down my block rams, specified some 10 MHz clocks (unnecessary in my mind, but recommended by the apps guy) and a few constraints dealing with crossing clock domains. Lastly, I unchecked a box that was really weird, in the Xilinx Gui, which was passed on to the synthesis tool, about pushing tristate busses across entity boundaries. The apps guy had come across a Xilinx app note saying to do this, even though I am not using internal tristate busses. Too strange... but the design meets timing now. What a long, strange, trip it has been. Clyde Dali wrote: > From previous experience with the xilinx tools at my compagny, if you > delete the files generated by the place&route tool when you want to > rerun the flow, it makes the P&R faster and gives better results. This > is due to the P&R tool taking old files as a "reference", just like > reentrant routing. > > I did not follow what Xilinx had to say about it but I would be curious > to know. > > Dali > > Clyde R. Shappee wrote: > > No, the design is only half empty (optimist!). > > > > What I have learned today is that the place and route tool is passing constraints onto the Xilinx flow, > > and this has been probably constraining the design where it should not be so stringent. > > > > I had some help today from a resource that is getting me on my way to properly constraining the design. > > > > It does appear that the varying number of logic levels is coming from the Xilinx P/R and not the > > synthesis tool. > > > > Clyde > > > > Marc Randolph wrote: > > > > > >>"Clyde R. Shappee" <clydes@world.std.com> wrote in message news:<3D910893.3ACBCF64@world.std.com>... > >> > >>>Hello, all, > >>> > >>>I am working a design with the Xilinx Spartan IIe, using ISE 4.2 sp3, > >>>Sinplicity 7.1 for synthesis. > >>> > >>>My design is relatively minimally constrained and meets static timing. > >>>In my report I see 8 levels of logic associated with my system clock. > >>> > >>>Today, I removed some unused logic, and reduced the length of some shift > >>>registers in my design, dropping about 32 flip-flops. > >>> > >>>Now the design fails to make static timing and the number of levels of > >>>logic associated with my clock has gone up to 12! > >>> > >>>What is at work here? > >>> > >>>Is the synthesis tool shooting me in the foot, or is it in the Xilinx > >>>tool, or my constraints. > >> > >>Howdy Cylde, > >> > >>Is this device pretty full? We've only run into this type of problem > >>when things are pretty packed. > >> > >>When this occurs, our typical mode of operation has been to do a > >>multi-pass place and route if it is close to meeting timing (say a > >>timing score of under 10000). One of the passes will usually hit on > >>an overnight session. > >> > >>If the timing is further out than that, we just continue improving the > >>code where we can (often times in areas completely unrelated), and the > >>next time around, it often meets timing, or gets very close (and will > >>meet with a multi-pass session). > >> > >>Good luck, > >> > >> Marc > > > >Article: 47497
lyqin@cti.com.cn (Leon Qin) writes: > I can't find it on Xilinx Web site . You're looking for the wrong thing. Alliance isn't free. Webpack is free.Article: 47498
I think Peter meant that Xilinx implements a Ring Oscillator in every part as part of the manufacturing testing and qualification. It is not a primitive that you can use inside the chip. Dali Karl wrote: > Peter, > > You mentioned the chip has already a ring oscillator on it, but how can I > find it? How can I make > use of it? Is it something like the DLL which I can instantiate in my vhdl > code? Let's say my chip is > Spartan2 200K...My app is for a clock of 100Hz...maybe I can divide a > mega-herts ring oscillator... > > > ---------------------------------------------------- > > "Peter Alfke" <palfke@earthlink.net> wrote in message > news:3D93CE70.26C00B44@earthlink.net... > >>Every Xilinx FPGA you buy has already had a ring oscillator running in >>it, since that is part of the test routine. Works like a champ, but can >>be very fast if you make the loop too small. >>You can also use it to measure chip temperature, and even temperature >>gradients across the chip. >>(Remember, frequency can easily be measured with one part per million >>accuracy). >>You can also use it as a controllable heater and make a thermostat out of >>it. >> >>Peter Alfke >> >> >>"Cool Morning ..." wrote: >> >> >>>Is it possible to build a Ring Oscillator in an FPGA chip? Any kind of >>>tricks may do, but is it possible? >>> >>>Kelvin. >> > >Article: 47499
"Xanatos" <fpsbb98@yahoo.com> writes: > IIRC, the Altera-Xilinx deal that allowed cross-patents means Altera can use > the term FPGA instead of CPLD. Why would Altera not have been allowed to use the term FPGA previously? Does Xilinx have a trademark on it?
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