Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Is anyone aware of current development boards and software packages available for the Virtex II Pro series with the embedded power pc processor (namely one or two). I'm not having much luck finding them. I know it's a very recent product, and I think this is one of my problems. Thanks, DanArticle: 47401
Petter Gustad <newsmailcomp1@gustad.com> wrote in message news:<m3k7mbz4ks.fsf@scimul.dolphinics.no>... > Is ISE 5.1 a native Linux port or does it run under Wine like 4.2? > > Petter How well does ISE work under linux ? I am considering using it in the WINE environment, but I'm hesitant that it might be unstable or slower due to the extra software layer due to WINE. Does anyone have experience with this ? Thanks, DanArticle: 47402
Thie discharge is apllied on external connector of the bord. By changing some things on the board ( ground connected to box, power decoupled, ... ) I make the system more stable but it arrives some times that it chrashes. And my problem is when it crash. I can accept that the system is completely lost ( Xilinx definitively out of order for example ) but not that the system get in an unknown state ! Effectively I do not see any physical damage. I think that power decoupling is pretty good but I will re-check. I will also check PROG Pin. Thanks Jérémie "Peter Alfke" <peter@xilinx.com> a écrit dans le message de news: 3D90ACBE.B65A9903@xilinx.com... > Jeremy, what is the nature of the discharge? > I suppose you do not see physical damage, "only" data corruption. > How good is your Vcc decoupling? > How stable is the PROG pin? Add a pull-up resistor or capacitor to ground? > Just wild ideas... > Peter Alfke > ===================== > "Jérémie WEBER" wrote: > > > I have a problem with a design ( 200k spartan II E ) that fail when an > > Electrostatic discharge occurs. > > > > I presume that some flip-flop are reseted but not all. That means that my > > design fail and is unstable. > > > > I have set some hardware things to avoid a large part of this problems but > > when it occurs I always fail. > > > > Have you got any Idea to secure the FPGA design itself ? > > > > Regards. > > > > Jérémie WEBER >Article: 47403
I've always wanted to, but never had a job doing (IC) layout, so I wouldn't know about the big bucks you "back end" folks make. Yessiree, I just get them vectors made and toss it over the fence. I wouldn't mind working for a company that pays the big bucks (I'm getting laid off on Thursday, yippee). In any case, the quantities are high because the design is for arc detector, which NEC has mandated to be in every bedroom of every new home in the USA. Leviton and TI are highly interested (quietly), and so is Boeing, Eaton, FAA and Navy in the aerospace (400 Hz) field. Hendry's stealth project I worked on had the best working technology in the world, bar none, but ran out of money (probably not because I make the big bucks). It's frustrating as hell to see that happen. For more details about arc detection, see UL1699. In any case, my personal belief is that certain things in design can't be avoidable, such as multiple clock domains caused by the necessity to have different frequency bases for different communications interfaces (some freq for RS232, some other freq for system, some other freq for audio codec, etc). But there are design techniques to avoid problems there. And what I don't agree with is that we should nilly willy create extra clocks by inserting clock delays so that some ripple counter output can be latched, nor creating clock dividers using toggle flops. Maybe it's OK if you _never_ plan on going to ASIC, though. That point has been a very well driven nail by the previous comments of others to this thread. And this has been a very long and delightful thread, I must say. BB ========================================= > bulletdog7 wrote: > > > Blackie, you are exactly right! (Please don't think I'm flaming you, > > its not intended) The ASICs I make though don't fit that category. To > > justify the cost, they are 4 to 10 clock domains, fully synchronous > > within each domain, but very asynchronous, dissimilar.Article: 47404
> You need to determine if this is Config stream corruption, or > Logic-state engine corruption - it sounds like the latter. No, it is the logic state. All state machine are not a problem because all states are checked and it always come back to a known state. But I use a ram block wher all my datas are stored and this one seems to be corrupted. A reset ( of my design, not of the chip itself ) could make the system working but it not occurs. > The design needs to have recovery schemes for this. Any advice on it ? > As ESD levels ramp, there will be a range where corruption occurs, > but damage does not. Ramp it more, and damage starts... Honestly, the Spartan IIE is quite robust to ESD. Our test has been made with 5kV ESD and with a kind of home made ESD Generator ( a piezzo gas lighter ;-) ) wich seems to be higher than 5kV because the board does not crash anymore at 5kV and crash with our home made ESD Generator ! Regards. Jérémie > > Also check the energy flows from the static discharge > - from where, to where.. > > State engine corruption with ESD is not uncommon > ( and also with relay-contact-noise ) - modern devices can 'see' > very narrow pulses : The design needs to have recovery schemes for this. > > As ESD levels ramp, there will be a range where corruption occurs, > but damage does not. Ramp it more, and damage starts... > > - jgArticle: 47405
I thank you two for your responses. I do have one last follow up question that you could possibly answer. Is it possible that once the fpga is programmed to connect it to a usb interface, rather then pci interface? Thanks.Article: 47406
Hello Jim, Tnx for youre replay. I do have examples from possibilities where these device were and are used in but these examples couldn't mention any company names so are these maybe examples of what the vendor thinks these devices could be used in??? To come to SIDSA: They have 13 employees; don't know if you can make, develop & distributate those devices in a good way with 'so many' people. Further more I already contacted them a few times by mail without getting any replay. So i think you're right when you say they've paused :-) Well like always to hear some experiences of remarks of users from these devices Best Regards, Dennis Sneijers Jim Granville wrote: > > Dennis Sneijers wrote: > > > > Hello, > > > > Looking to the market we see an upcoming trend in programmable analogue > > fpga based devices. At this moment i'm researching these devices. > > Devices like the FPAA - Anadigm, Trac - Zetex, ispPAC - Lattice, PSoC - > > Cypress and the FIPSOC - SIDSA are good examples of these. > > > > I wanna know if anyone knows something more about other devices fitting > > in this category? And maybe there is someone who got more experience > > with applications where these devices are used. Tell me please more > > about that i'm very interested in it. And does anyone knows something > > more about the FIPSOC? It seems a very unknow device to me... > > We put a link to this on our web site, but the PDF for FIPSOC1 is dated > June 99, and nothing more recent shows in the press info, so I would say > it > is 'paused' :) > > On "Analog FPGA" generally, their biggest drawback is the very poor > and narrow-use analog performance - besides being single-sourced > in the worst sense, they cannot compete with the leading edge > analog companies, which are leaving them behind in specs. > Dynamic range, distortion and noise are commonly so mediocre, they > are left off the 'Overview' promo materials entirely (eg ispPAC) > > They look nice to play with, and look good in press releases, but > do you know anyone who has actually used one in a real product ? > > -jgArticle: 47407
>Do you happen to know if there's a 32.??Khz xtal osc. that uses sufficiently >little power that it can run off a 3V coin cell ? or with some power-down mode ? >The reason I ask is that I'd dearly like to replace the PIIX4 southbridge + >CombiIO functions in an FPGA/CPLD and about the only thing that's hard is the real Look at Dallas/Maxim. Probably others too. (Maxim bought Dallas) In the old days, the RTC was a separate chip. Dallas was one of the main suppliers. They still make them. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 47408
>But: Whenever you press and whenever you release the button, the contact >will bounce, which means you seem to make multiple switch closures and >openings. Be aware of this bounce. A toggle switch can avoid this, if you What's magic about a toggle switch? I thought they all bounced too. Are you thinking of SPDT kicking an R-S type FF? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 47409
Jeremie WEBER wrote: > > > You need to determine if this is Config stream corruption, or > > Logic-state engine corruption - it sounds like the latter. > > No, it is the logic state. All state machine are not a problem because all > states are checked and it always come back to a known state. But I use a ram > block wher all my datas are stored and this one seems to be corrupted. > A reset ( of my design, not of the chip itself ) could make the system > working but it not occurs. If you do not have a manual reset, I would add one, to confirm the system can re-init ( ie FPGA config latches, and logic state engines are all intact ) > > > The design needs to have recovery schemes for this. > > Any advice on it ? If you are confidant your state engines recover, then once data corruption occurs, you will need to 're-init', rather like a uC WDOG. Of course, recognising the data is corrupt is not trivial in itself :) In a FPGA, if you have RAM to spare, you could try parity, or Error Correcting storage. ECC can flag a fix, so you can track errors under test. If the data is corrupted outside the ECC realm ( eg at 'instant of read' ) then you cannot so easily error detect. > > As ESD levels ramp, there will be a range where corruption occurs, > > but damage does not. Ramp it more, and damage starts... > > Honestly, the Spartan IIE is quite robust to ESD. Our test has been made > with 5kV ESD and with a kind of home made ESD Generator ( a piezzo gas > lighter ;-) ) wich seems to be higher than 5kV because the board does not > crash anymore at 5kV and crash with our home made ESD Generator ! This is quite an aggressive ESD test, so it's no surprise to see some effect. The ESD ratings on chips are damage only, no-one promises to keep the device operational as well :) - jgArticle: 47410
Hey I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. Problem is that I don't find any datasheet telling me how to do the powering for the Altera. Should I add decoupling capasitors and what values they should be? Is there internal clock in Altera or should I add a crystall to my PCB? If you are wondering why I want to use OLD Altera Flex 8000, because I want to add only 2 layers to my PCB. I think that new Alteras need separate power and ground layers, so 2 layers is not enough. is there some websites/tutorials how to do PCBs for FPGAs? - Jarmo jarmoma@mail.student.oulu.fiArticle: 47411
I have implemented a DDR SDRAM controller in a VIRTEX II but I have problems
balancing the clock / not clock to the DDR Sdram. The design work with no
errors, but the switching where the clk and not clk intersect is outside the
DDR Sdram specification (MICRON specify that the intersction between the two
clock should always lie within the 1.05-1.45 voltage range. This is observed
using a ocsilloscope with active probes.
The two clock are generated be dual-data rate FFDs as follow (the CLK and
nCLKcomes from a DCM with duty-cycle correction set):
---------------------------------------------------------------------------
--
--------------------------------------------------------------------------
---
-- SDRAM clock generation
--------------------------------------------------------------------------
---
--------------------------------------------------------------------------
---
clk_gen :
FDDRRSE port map (
Q => ddr_clk,
D0 => '1',
D1 => '0',
C0 => clk,
C1 => nCLK,
CE => '1',
S => '0',
R => '0');
nCLK_gen :
FDDRRSE port map (
Q => ddr_CLK180,
D0 => '0',
D1 => '1',
C0 => clk,
C1 => nCLK,
CE => '1',
S => '0',
R => '0');
----------------------------------------------------------------------------
----------------
Using 1.25V as a reference, the lag between the two clocks seen on the PCB
is as follow:
128 ps using SSTL2_II
327 ps using SSTL2_II_dci
618 ps using SSTL2_I
1364 ps using SSTL2_I_dci
Obviously the latter standards have lower drive capability and thus slower
slopes and thereby more lag between the clocks.
But I think there must be a lag between the clocks before the actual drivers
which I cannot account for. I have inspected the FDDRRSE in the FPGA Editor
a find that there is no delay difference between the clocks into the clock
pins. So WHAT causes the difference?
ANY IDEAS ANYONE?
Thanks
John
Article: 47412I have to mount a spartan II fpga ( 3.3 volt ) with an 5 volt interface pci 32 bit. How is it possible? Thanks, JArticle: 47413
I've just implemented an fpdp tm interface to an externally supplied board. The nrdy line coming from the rm board appears to pulse and not maintain a steady level. Is this correct behaviour? Can anyone supply me with a timing diagram?Article: 47414
Such a comparison is meaningless as it changes every other month by new families and/or devices being added. Because the tools are far from simple to operate, even though reduced versions can be downloaded for free, you stick to one manufacturer. You just cannot keep yourself updated on all families and tools. I'd choose the tools upon who can help me when I have a problem. Best if you had colleague. Rene Matthew E Rosenthal wrote: > I'm looking for a comparison of sizes and speeds for fpga's of all > different companies. > > Can someone point me towards this informations.Article: 47415
I do Altera ACEX1k, Max7000 and Max3000 on twosided boards. No problems. I place the decoupling caps on the backside, a selection amongst 10 and 100nF 1206. The backside is split between Vcc and GND in the vicinity of the Altera. It did work up too 100MHz till now. I didn't have higher clocked designs yet. As clock I use clockgenerators, not just crystals. Rene Jarmo wrote: > Hey > > I want to make Printed Circuit Board (PCB) for Altera Flex 8000 family. > Problem is that I don't find any datasheet telling me how to do the > powering for the Altera. Should I add decoupling capasitors and what > values they should be? > > Is there internal clock in Altera or should I add a crystall to my PCB? > > If you are wondering why I want to use OLD Altera Flex 8000, because I > want to add only 2 layers to my PCB. I think that new Alteras need > separate power and ground layers, so 2 layers is not enough. > > is there some websites/tutorials how to do PCBs for FPGAs?Article: 47416
thank you so much, blackie. "Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> wrote in message news:<Kw8j9.6962$7i2.1472@nwrddc02.gnilink.net>... > Try Palmchip. > They do SoC, but will also just sell the cores. > Then you can just hardcode and use squencer > to bypass the usual embedded processor. > > "frank" <maddog@etang.com> wrote in message > news:2b32768a.0209201200.70d86885@posting.google.com... > > Hi, > > I want make a hard disk drive from SDRAMs,which use IDE interface to > > connect to pc.and have a battery to keep the data when power off. > > is there any logic core for FPGA-IDE interfaceing?? > > any one have try that before?? > > please give me some suggestion, thank a lot!!!Article: 47417
This is a multi-part message in MIME format. --------------F26277DF2A14F27888284710 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Jamba, Here is some information about designing universal cards using our cores. This applies to older XC4000 based designs, in addition to Virtex and Spartan-II. A suggestion is to use the TL712 differential comparator on the add-in board you are designing. This chip is from Texas Instruments. This comparator has complementary outputs and an output enable. You tie Vio (from the PCI bus, which is the I/O signal voltage -- either 3.3v or 5.0v, depending on what kind of slot you are plugged into) to one of the comparator inputs, and then create a reference voltage around 4.1 volts using a resistive divider for the other input. You would generate this from any fixed supply voltage that is available (5.0v, 3.3v, 12v). The comparator will then be detecting which bus voltage is in use by comparing Vio to 4.1 volts. With the complementary outputs, interfacing to SPROM devices is easy; each output of the comparator goes to a different SPROM output enable pin so that only one SPROM is enabled based on the bus voltage. This assumes you have the enable of the comparator permanently asserted. You tie the data outputs of the SPROMs together, which is okay since only one will actively drive at any time. What is really nice about this comparator is its output enable function. If you put pullups on its outputs, and have the enable run to a jumper, you can disable both SPROMs at the same time. If you then take the same output enable signal from the jumper and run it to the FPGA to select between slave serial and master serial modes (on the M0, M1, and M2 pins) you can have one jumper which disables the SPROMs and puts the FPGA in slave serial mode -- this allows you to easily put on another header to connect a download cable (Xilinx Parallel Cable or MultiLINX) for debugging purposes. Hope this helps, Stephan Jamba wrote: > I have to mount a spartan II fpga ( 3.3 volt ) with an 5 volt interface pci > 32 bit. > How is it possible? > > Thanks, JArticle: 47419
Ah, I forgot the genesis of this thread. We weren't advocating ripple
counters in all FPGA designs, in fact most of the time they are not
appropriate. However, they are yet another tool in the toolbox that
can be veryuseful when properly applied. There isn't anything
preventing their use in ASICs as far as I know either. Fact is that
they use less logic than a synchronous counter and because there is
no clock tree, they can be run much faster than synchronous counters
in any technology. This is handy for things like high clock rate
prescalers and certain very low power applications.
One shouldn't use clock delays to get at the outputs of a ripple count. In
most cases, you use only one bit of the output and resynchronize that to
your clock. If you need to use more than one bit, you need to be
careful about how you use it. This doesn't mean delay lines, rather it
means disabling the count (by stopping the toggling of the LSB) long
enough to allow the ripple to complete before sampling the outputs.
Sorry to hear about your job. Good luck in the search for a new one.
Blackie Beard wrote:
> I've always wanted to, but never had a job doing (IC) layout,
> so I wouldn't know about the big bucks you "back end" folks
> make. Yessiree, I just get them vectors made and toss it over
> the fence. I wouldn't mind working for a company that pays
> the big bucks (I'm getting laid off on Thursday, yippee). In
> any case, the quantities are high because the design is for
> arc detector, which NEC has mandated to be in every
> bedroom of every new home in the USA. Leviton and TI are
> highly interested (quietly), and so is Boeing, Eaton, FAA and
> Navy in the aerospace (400 Hz) field. Hendry's stealth
> project I worked on had the best working technology in the
> world, bar none, but ran out of money (probably not
> because I make the big bucks). It's frustrating as hell to
> see that happen. For more details about arc detection,
> see UL1699.
>
> In any case, my personal belief is that certain things in
> design can't be avoidable, such as multiple clock domains
> caused by the necessity to have different frequency bases
> for different communications interfaces (some freq for
> RS232, some other freq for system, some other freq for
> audio codec, etc). But there are design techniques to
> avoid problems there. And what I don't agree with is that
> we should nilly willy create extra clocks by inserting clock
> delays so that some ripple counter output can be latched,
> nor creating clock dividers using toggle flops. Maybe it's
> OK if you _never_ plan on going to ASIC, though. That
> point has been a very well driven nail by the previous
> comments of others to this thread. And this has been a
> very long and delightful thread, I must say.
>
> BB
> =========================================
> > bulletdog7 wrote:
> >
> > > Blackie, you are exactly right! (Please don't think I'm flaming you,
> > > its not intended) The ASICs I make though don't fit that category. To
> > > justify the cost, they are 4 to 10 clock domains, fully synchronous
> > > within each domain, but very asynchronous, dissimilar.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47420pierrotlafouine@hotmail.com (Pierre Lafrance) wrote in message news:<d77de4d1.0209191324.56cdb1ac@posting.google.com>... > I currently try to convert a real time software C algorytme I > develloped (Bayer images to RGB) to Handle C, but yet far from > routing. I do VHDL, C, and C++ fluently, so I was the chosen one to > evaluate Celoxica. > > Handle C is a nice language, but is not done to devellope hardware > interface like DDR, or PCI-X interface. > Hardware extracted from such tools is far from optimized. I could find it useful only to obtain a behavioral VHDL model from my C code. There are several alternatives in C-like languages that support event handling, parallel processes and stuff capable of describing hardware. HardwareC is very similar in syntax to C, extended by data types and other useful options. Etherdesign 2 years ago released the SeaHDL tool. It generates C, Verilog and FPGA configuration files (for some Xilinx process) from an initial description in HardwareC. I'm not aware of the current status. It's nice try, useful in early level evaluations, but not sure what it can do for large design. Uncle NoahArticle: 47421
"Clyde R. Shappee" <clydes@world.std.com> wrote in message news:<3D910893.3ACBCF64@world.std.com>... > Hello, all, > > I am working a design with the Xilinx Spartan IIe, using ISE 4.2 sp3, > Sinplicity 7.1 for synthesis. > > My design is relatively minimally constrained and meets static timing. > In my report I see 8 levels of logic associated with my system clock. > > Today, I removed some unused logic, and reduced the length of some shift > registers in my design, dropping about 32 flip-flops. > > Now the design fails to make static timing and the number of levels of > logic associated with my clock has gone up to 12! > > What is at work here? > > Is the synthesis tool shooting me in the foot, or is it in the Xilinx > tool, or my constraints. Howdy Cylde, Is this device pretty full? We've only run into this type of problem when things are pretty packed. When this occurs, our typical mode of operation has been to do a multi-pass place and route if it is close to meeting timing (say a timing score of under 10000). One of the passes will usually hit on an overnight session. If the timing is further out than that, we just continue improving the code where we can (often times in areas completely unrelated), and the next time around, it often meets timing, or gets very close (and will meet with a multi-pass session). Good luck, MarcArticle: 47422
Dan, In the August 2002 issue of Linux Journal there is an article with a picture of Virtex-II Pro board. It is made by Xilinx and called ML300, I don't know when will it be available, asking your Xilinx FAE might provide some answers! jakab Dan <hombecker1962@hotmail.com> wrote in message news:f6989659.0209242140.845a696@posting.google.com... > Is anyone aware of current development boards and software packages > available for the Virtex II Pro series with the embedded power pc > processor (namely one or two). I'm not having much luck finding them. > I know it's a very recent product, and I think this is one of my > problems. > > Thanks, > DanArticle: 47423
Sounds like you're being defensive, Austin. Announcing product before it is available? Xilinx does this all the time. When did you first start talking about Virtex-II Pro? I think I saw articles about two years ago. I don't think this is a bad thing, necessarily. It is nice to know what is coming in advance; design cycles are shorter in FPGAs but they still aren't instantaneous. However, what about the 2V1500 I was told would be available by June (2001)? I think it just came out this August (2002). This is a little more design time than was necessary, don't you think? -Especially if you were counting on that June'01 delivery. I believe this was also the case with the 2V2000. http://www.xilinx.com/prs_rls/vtx2ship.htm "The first members of the Virtex-II family... are sampling now with the rest the family sampling by mid 2001." Jack Austin Lesea wrote: > I will reiterate something Peter has said once before: Altera has announced that they will have (note use of the future tense) .......Article: 47424
Jim Granville wrote: > > Package alone is not likely to be a dominant cost factor : > Far more relevent, will be die area, yield, testing times, FAB run > volumes, > ( mask amortise) plus the M Squared fudge factor ( M^2 = Marketing > Margin ) > > ( see also other thread on higher end CPLD price-kick ) No, of course the package is not the only cost determining factor. But smaller designs are often IO limited and a larger die must be purchased in order to get the higher IO count. > That said, it makes sound sense to offer a broad range of die in > a common package - designs NEVER get smaller as they mature :) Unfortunately in the low cost series of chips, the range of die in a package is often limited. It seems the manufacturers incur costs based on the number of line items on their price list. So they keep that to a minimum on the low cost devices. Personally, I don't see that. I view it more like the car manufacturers do. Each factory needs to make a given number of units a year and can make many different models. The cost of handling the models is low compared to the cost of running the factory, so have lots of variations on the theme as long as you can produce it on the same line. > A good example, that proves this can be done, is the Actel ProASIC > - they offer ALL die, from 75K to 1000K, in a PQFP208 package ( 7 steps > ). > > If you really need IO, they also have a FBGA1152 on the biggest device. Ah yes, but that is buying a lot of logic (or is it routing and the logic is free?) to get the IOs. Another poster was saying he didn't want to buy the IO to get the logic :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z