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Thanks for the reply and confirmation that it is a bug. > Hopefully, EDK 8.2i is an option available to you. Unfortunately not, other companies on the project insist on 7.1 I'm just going to have to improve my own test code to be a reliable tool for burning flash. (Further communication from Xilinx regarding the webcase has only produced more conflicting information. *SIGH*)Article: 111926
Hi, your FPGA usually has serveral bus lines. Your synthesis tool will use them. Bye Helmut Al wrote: > Hi, > is there anyone who have a clue on how a synthesizer will do the RTL for > bidirectional bus inside your logic? As far as I know high impedence are > not synthesizable in the internal logic, only on I/O. Is this correct > for all the FPGA? > Are there any schematic example on how these bidirectional busses are > implemented? > > Thanks > > Al > > > -- > Alessandro Basili > CERN, PH/UGC > Hardware DesignerArticle: 111927
ruben.gue@gmail.com wrote:
> TYPE inhibitory_weights_array IS array(0 to 23) of std_logic_vector(15
> downto 0);
>
> Synthesis do not show any error, but when I try to check his behavioral
> simulation, the following error happen:
Consider posting the testbench code to comp.lang.vhdl
-- Mike Treseler
Article: 111928Mike Treseler wrote: > ruben.gue@gmail.com wrote: > > > TYPE inhibitory_weights_array IS array(0 to 23) of std_logic_vector(15 > > downto 0); > > > > Synthesis do not show any error, but when I try to check his behavioral > > simulation, the following error happen: > > Consider posting the testbench code to comp.lang.vhdl > > -- Mike Treseler Ok, I will do it right now, thanks, RubenArticle: 111929
[Commercial announcement follows] FPGAXpose is a debug tool that works in conjunction with ChipScope Pro and provides much greater visibility. FPGAXpose allows you to select and view signals at runtime without the need to rerun place and route or even reconfigure the FPGA. You can start using FPGAXpose today, without adding any additional cores to your design. Including the optional FPGAXpose core will provide even greater visibility. More information about FPGAXpose can be found at: http://www.sandbyte.com/products.html Full featured 30 day evaluation versions can be downloaded from: http://www.sandbyte.com/download.php Vivian Bessler -- SandbyteArticle: 111930
KJ wrote: > "pete o." <portisi@comcast.net> wrote in message > news:1163343998.901642.121850@m7g2000cwm.googlegroups.com... > >I am new to FPGA design so I'm sure this is a very basic question. > > Is there a rule of thumb when using these constraints? > Yes, the rule of thumb is to thumb through the data sheets for the device(s) > to which your FPGA will be communicating. If a device requires a 5 ns setup > time of one signal relative to some other signal than the clock to output > delay of those two signals coming out of your FPGA must meet that > requirement. Repeat this for every signal that enters or exits your FPGA > design. Most of these constraints can be directly coded as constraints to > your FPGA synthesis tool Ones that can not must still be guaranteed to be > met by your design and you must verify that they are. > > As a general guideline setup times of an external device will translate into > clock to output delay requirement for the FPGA. Clock to output delays of > an external device will translate into input setup time requirements for the > FPGA. Both of these will translate in roughly the following manner: > > Tsu (requirement) = Clock Period - Tco (specification) - Clock Skew - PCB > prop delays differences > That assumes that hold requirements are guaranteed by design. Often that assumption is corrrect but sometimes it isn't. In later case you have to specify hold conditions too: Th(requirement) = Tmin_tco (specification) - Clock Skew; Tmin_tco(requirement) = Th(specification) - Clock Skew;Article: 111931
"Vivian Bessler" <vivian.bessler.nospam@sandbyte.com> schrieb im Newsbeitrag news:zZ%5h.15960$j7.333710@news.indigo.ie... > [Commercial announcement follows] > > FPGAXpose is a debug tool that works in conjunction with ChipScope Pro > and provides much greater visibility. FPGAXpose allows you to select > and view signals at runtime without the need to rerun place and route or > even reconfigure the FPGA. > > You can start using FPGAXpose today, without adding any additional cores > to your design. Including the optional FPGAXpose core will provide even > greater visibility. > > More information about FPGAXpose can be found at: > http://www.sandbyte.com/products.html > > Full featured 30 day evaluation versions can be downloaded from: > http://www.sandbyte.com/download.php > > Vivian Bessler > -- > Sandbyte I tried it didnt work :( AnttiArticle: 111932
Hi Antti, I tried it and it works like a treat. Makes the debugging our boards a lot easier. btw did you get an eval license from sandbyte, because it will not work without this license. cheers Darren On Nov 13, 3:31 pm, "Antti Lukats" <a...@openchip.org> wrote: > "Vivian Bessler" <vivian.bessler.nos...@sandbyte.com> schrieb im Newsbeitragnews:zZ%5h.15960$j7.333710@news.indigo.ie... > > > > > [Commercial announcement follows] > > > FPGAXpose is a debug tool that works in conjunction with ChipScope Pro > > and provides much greater visibility. FPGAXpose allows you to select > > and view signals at runtime without the need to rerun place and route or > > even reconfigure the FPGA. > > > You can start using FPGAXpose today, without adding any additional cores > > to your design. Including the optional FPGAXpose core will provide even > > greater visibility. > > > More information about FPGAXpose can be found at: > >http://www.sandbyte.com/products.html > > > Full featured 30 day evaluation versions can be downloaded from: > >http://www.sandbyte.com/download.php > > > Vivian Bessler > > -- > > SandbyteI tried it didnt work :( > > AnttiArticle: 111933
Antti Lukats wrote: > "Vivian Bessler" <vivian.bessler.nospam@sandbyte.com> schrieb im Newsbeitrag > news:zZ%5h.15960$j7.333710@news.indigo.ie... > > [Commercial announcement follows] > > > > FPGAXpose is a debug tool that works in conjunction with ChipScope Pro > > and provides much greater visibility. FPGAXpose allows you to select > > and view signals at runtime without the need to rerun place and route or > > even reconfigure the FPGA. > > > > You can start using FPGAXpose today, without adding any additional cores > > to your design. Including the optional FPGAXpose core will provide even > > greater visibility. > > > > More information about FPGAXpose can be found at: > > http://www.sandbyte.com/products.html > > > > Full featured 30 day evaluation versions can be downloaded from: > > http://www.sandbyte.com/download.php > > > > Vivian Bessler > > -- > > Sandbyte > > I tried it didnt work :( > > Antti Worked fine for me. Found it to be quite useful.... Rob.Article: 111934
KJ wrote: > "Josep Duran" <j.duran@teleline.es> wrote in message > news:1163364369.744466.26760@b28g2000cwb.googlegroups.com... > > > > On a (hopefully) related issue, how do you handle the Tco jitter > > between different IO pads. > If there is a timing requirement between these two outputs that must be met > then generally you must not allow them to change on the same edge of the > same clock cycle. Two methods of doing this are: > - Take an extra clock cycle, say set one of the outputs on clock cycle 1, > the other signal on the next clock cycle holding the first one constant on > this clock cycle. This is generally the preferred approach and would be an > example of preventing the signals from changing on 'the same clock cycle' > - Clock the two signals on opposite edges of the clock. On paper it seems > to give you a built-in half a clock cycle skew between the two but when you > account for duty cycle variation (clocks are never 50%) and the fact that > sometimes you have no control over the clock (like if it comes from an > external part) this method loses some of it's luster. This would be an > example of not allowing them to change on 'the same edge'. > > KJ Or use built-in PLLs in order to provide phase shift between the clocks at resolution finer than 180 degrees. Besides, newer FPGAs have programmable delay elements in the IO cells so sometimes you could drive the strobe and data signals on the same clock edge. Just specify Tco(min) requirements for data signals and Tco(max) for a strobe in way that meets Th spec of the device you are talking to. The fitter is supposed to do the rest. Of course, for that to work both strobe and data have to be driven by good low-scew clock and hold time requirements of external device should be rather liberal - around (-1.5) ns.Article: 111935
Give us a clue here. Are you working in VHDL or Verilog? Xilinx, Altera, or other? Most systems that support LVDS have a technology dependent component that will support LVDS transmissions. Unless we know what you are working with, we can't help. Brad Smallridge aivision <ekavirsrikanth@gmail.com> wrote in message news:1163413947.064149.16520@f16g2000cwb.googlegroups.com... > > > hi all, > > i have serial data out in my design and i need to convert it to LVDS > signal how can i covert it to LVDS . my end system needs differential > data as input so i need to convert to LVDS. i have written code in vhdl > and data out is ready which is serial data . i am using spartan 3e > fpga..... > > can any one please explain how to change to LVDS. > > > regards > srikanth >Article: 111936
<darren.redmond@gmail.com> wrote in message news:1163434137.763366.9340@e3g2000cwe.googlegroups.com... > > Hi Antti, > > I tried it and it works like a treat. Makes the debugging our boards a > lot easier. But working on the same computer as the person who posted the original advert might give you a head start. Advert:Article: 111937
Vivian Bessler wrote: > [Commercial announcement follows] > > FPGAXpose is a debug tool that works in conjunction with ChipScope Pro > and provides much greater visibility. FPGAXpose allows you to select > and view signals at runtime without the need to rerun place and route or > even reconfigure the FPGA. > > You can start using FPGAXpose today, without adding any additional cores > to your design. Including the optional FPGAXpose core will provide even > greater visibility. > > More information about FPGAXpose can be found at: > http://www.sandbyte.com/products.html > > Full featured 30 day evaluation versions can be downloaded from: > http://www.sandbyte.com/download.php > > Vivian Bessler > -- > Sandbyte Do I need to install ISE (or ChipScope Pro) before playing with FPGAXpose?Article: 111938
> If you're meaning that you want to have it automatically associate > with a given UCF file, depending upon what part you select when you > begin a *new* project.... as far as I know, no. Just out of > curiousity, what's your application that makes this behavior > desireable? In my experience UCF files tend to be fairly application > specific..... Multiple projects with the same pinout I take it? I have two development boards on my desk, a Xilinx ml402 and a ml403. They are very similar but also have some slight differences in the UCF files. When I switch from one board to another I go into the part properties and switch fx12 to sx35, remove a ucf file, and add the other ucf file. Seems like there should be a better way. So far the UCF files are different in only that the ml403 has some missing pins. Later there may be some placement constraints that would also change. Brad Smallridge AiVision > > Brad Smallridge wrote: >> Is there any way to switch from a ucf file for >> an ML402 dev board to a ucf file for a ML403 >> board without having to delete one file from >> the project and copy the source from another >> ucf file? Can it automatically know what ucf >> file to use based on the FX12 or SX35 part? >> >> Brad Smallridge >> aivision >> dot >> com >Article: 111939
Not sure what you're trying to do in your labs... I know when I was in undergrad we certainly never got to anything so complicated in a single semester that we couldn't have done in a V4.... From your message, I can't tell if you already have V5 hardware or not... But, if not, digilent makes what looks like a pretty powerful eval board based on a V4 FX12 chip - it sells for only $299 - with is pretty good, considering the Spartan 3E board is 150! There's also a virtex2 board that has an academic price of 299 (vs. a commerical price of over a grand)... but the virtex2's are gettin to be pretty outdated it seems. But yea... I'd be willing to bet the licensing for ISE through the university program is pretty reasonably priced. At least if xilinx is smart it is, I know that when I'm comparing equivalent xilinx/altera chips I look at which tools I know already. John_H wrote: > jonas@mit.edu wrote: > > Hello! For a long time my lab purchased the lower-cost ISE Base-X kit, > > which was recently discontinued and its functionality was rolled into > > WebPack (which is available for free!) Base-X always seemed to contain > > support for the two smallest of Xilinx's high-end devices. The latest > > WebPack, however, does not contain support for the V5s. Is there a plan > > to have V5 support in WebPack in the future? > > > > I know the standard Xilinx line on this is "If you're doing high-end > > development, ISE tools are not going to be a big part of your cost" but > > in our environment where we have a bunch of students doing development > > on prototype boards, the license costs can add up quickly. > > > > Thanks, > > ...Eric > > If you're a university environment, contact Xilinx about their > University Program. While you might not get hotline support, you can > get significantly greater tool access without paying full commercial > license costs. The FPGA vendors *are* interested in getting new FPGA > designers into the field with solid tool experience. Preferably their > tools.Article: 111940
Hi Annti, I don't see your name among our evaluation or full license users. If you need any assistance our support team will be happy to help you out. Vivian Antti Lukats wrote: > "Vivian Bessler" <vivian.bessler.nospam@sandbyte.com> schrieb im Newsbeitrag > news:zZ%5h.15960$j7.333710@news.indigo.ie... > >>[Commercial announcement follows] >> >>FPGAXpose is a debug tool that works in conjunction with ChipScope Pro >>and provides much greater visibility. FPGAXpose allows you to select >>and view signals at runtime without the need to rerun place and route or >>even reconfigure the FPGA. >> >>You can start using FPGAXpose today, without adding any additional cores >>to your design. Including the optional FPGAXpose core will provide even >>greater visibility. >> >>More information about FPGAXpose can be found at: >>http://www.sandbyte.com/products.html >> >>Full featured 30 day evaluation versions can be downloaded from: >>http://www.sandbyte.com/download.php >> >>Vivian Bessler >>-- >>Sandbyte > > > I tried it didnt work :( > > Antti > >Article: 111941
Oops. Belay that last message. I'm not reading well this morning. Here are some code snips from my Virtex4 platform which should be about the same for your Spartan3s: top level VHDL: my_serial_to_cam2_OBUFDS : OBUFDS port map ( O => cam2_serial_out_p, -- to cam2 OB => cam2_serial_out_n, -- to cam2 I => serial_to_cam2 ); serial_from_cam2_IBUFDS : IBUFDS port map ( O => serial_from_cam2, I => cam2_serial_in_p, -- from cam2 IB => cam2_serial_in_n ); -- from cam2 Underneath the top level I have a code module that deals with only non-differential signals. I never did find out a way to simulate differential signals. In your UCF file: # Serial Port from and to CAM2 NET "cam2_serial_out_n" LOC = AF22; # HDR2_42 NET "cam2_serial_out_p" LOC = AF21; # HDR2_44 NET "cam2_serial_in_n" LOC = AF20; # HDR2_30 NET "cam2_serial_in_p" LOC = AF19; # HDR2_32 # differential termination applied to input IBUFD INST serial_from_cam2_IBUFDS DIFF_TERM = TRUE; # must match top Hope this helps. Brad Smallridge aivision <ekavirsrikanth@gmail.com> wrote in message news:1163413947.064149.16520@f16g2000cwb.googlegroups.com... > > > hi all, > > i have serial data out in my design and i need to convert it to LVDS > signal how can i covert it to LVDS . my end system needs differential > data as input so i need to convert to LVDS. i have written code in vhdl > and data out is ready which is serial data . i am using spartan 3e > fpga..... > > can any one please explain how to change to LVDS. > > > regards > srikanth >Article: 111942
And another oops. INST my_serial_from_cam2_IBUFDS DIFF_TERM = TRUE; # must match top BradArticle: 111943
Hello AMONTEC, Both ISE and ChipScope Pro are required. Vivian -- Sandbyte AMONTEC wrote: > Vivian Bessler wrote: > >> [Commercial announcement follows] >> >> FPGAXpose is a debug tool that works in conjunction with ChipScope Pro >> and provides much greater visibility. FPGAXpose allows you to select >> and view signals at runtime without the need to rerun place and route or >> even reconfigure the FPGA. >> >> You can start using FPGAXpose today, without adding any additional cores >> to your design. Including the optional FPGAXpose core will provide even >> greater visibility. >> >> More information about FPGAXpose can be found at: >> http://www.sandbyte.com/products.html >> >> Full featured 30 day evaluation versions can be downloaded from: >> http://www.sandbyte.com/download.php >> >> Vivian Bessler >> -- >> Sandbyte > > Do I need to install ISE (or ChipScope Pro) before playing with FPGAXpose? >Article: 111944
I have simulated the delays on Xilinx OSERDES using both the ISE simulator and ModelSimXE and find that the delay in serial output does not match the specifications in the user guide. Has anyone had a similar experience? There is suppose to be at least a one framing clock delay and a variety of serial clocks delay depending on the data width. Moving the design to hardware I find a seemingly random delay by comparing the output of an OSERDES to a framing clock (CLKDIV) outputted by an ODDR. Only by outputting the CLKDIV signal by another OSERDES did I find any synchonization between CLKDIV and the data: cam_oserdes_xclk: cam_link_out_sdr_oserdes port map( clk => cam_clk_280, -- in clkdiv => clkdiv, -- in data => "1100011", -- in 7 bits q => xclk ); -- out This works great. Did anyone else have an issue using ODDR? Brad Smallridge aivisionArticle: 111945
Hi Will, I doubt that we are both sitting at the same machine considering the ip address is an eircom (irish broadband provider) host machine. Considering that Sandbyte are in the same Technological Office Complex as ourselves it is more likely that we have the same broadband provider, and that ip address is the local eircom exchange receiving news messages, amongst others. Also the reason Sandbyte might have a bit more traction in Dublin than elsewhere is because I was at a presentation delivered by Sandbyte in Dublin last friday week (10 days ago). I reckon the majority of people present were from Dublin. Not everything happens to be a conspiracy theory. regards Darren On Nov 13, 4:22 pm, "Will Dean" <w...@nospam.demon.co.uk> wrote: > <darren.redm...@gmail.com> wrote in messagenews:1163434137.763366.9340@e3g2000cwe.googlegroups.com... > > > > > Hi Antti, > > > I tried it and it works like a treat. Makes the debugging our boards a > > lot easier.But working on the same computer as the person who posted the original > advert might give you a head start. > > Advert: > > Message-ID: <zZ%5h.15960$j7.333710@news.indigo.ie> > NNTP-Posting-Host: 83.70.72.77 > > Supportive reply: > > Message-ID: <1163434137.763366.9340@e3g2000cwe.googlegroups.com> > NNTP-Posting-Host: 83.70.72.77 > > (The other supportive reply is from an IP address in Dublin, too) > > It does certainly seems to be a popular bit of software in Dublin. Has > anyone outside Dublin and not closely related to the authors found it > useful? > > "I love the smell of sock-puppets in the morning" > > WillArticle: 111946
Will Dean schrieb: > <darren.redmond@gmail.com> wrote in message > news:1163434137.763366.9340@e3g2000cwe.googlegroups.com... > > > > Hi Antti, > > > > I tried it and it works like a treat. Makes the debugging our boards a > > lot easier. > > But working on the same computer as the person who posted the original > advert might give you a head start. > > Advert: > > Message-ID: <zZ%5h.15960$j7.333710@news.indigo.ie> > NNTP-Posting-Host: 83.70.72.77 > > Supportive reply: > > Message-ID: <1163434137.763366.9340@e3g2000cwe.googlegroups.com> > NNTP-Posting-Host: 83.70.72.77 > > (The other supportive reply is from an IP address in Dublin, too) > > It does certainly seems to be a popular bit of software in Dublin. Has > anyone outside Dublin and not closely related to the authors found it > useful? > > "I love the smell of sock-puppets in the morning" > > Will Hi Will I tried the tool, it was really slow parsing the LL file and did not communicate with Cable III nor Platform USB cable so I gave up. the readback thing isnt complicated I have done that myself with some custom software myself. anttiArticle: 111947
Arash wrote: > Hello and thanks for your cooperation. > Sorry, since I copied this script from another place, during the copy, > the last question was not pasted correctly. Anyhow, my two questions > were as follows: > > 1- As I have seen in different vendors pages, most of the SERDES > devices are placed after a protocol device. For transmitting SDH > telecombus data is it necessary to implement a protocol on it or not. > (Why protocol specification is required?). > 2- Has anyone seen any SERDES chip which supports the mentioned rates > (19.44 > MHz and 77.76MHz) on its parallel side or not? > > John_H wrote: > > Since STM4 is only 622 Mb/s and you're posting on the FPGA board, you can > > apply a SerDes from just about any FPGA to get to your rate Many families > > will also support 622 Mb/s in the standard I/Os. The STM-4 rate is a target > > for most FPGA vendors so they'll shoot at this as an achievable maximum on > > standard I/O and a minimum on the SerDes as well. > > > First of all, SERDES is not available in any FPGA, and for example in > Xilinx FPGA's, it is available in VIRTEX-II pro and the VIRTEX-4 and > VIRTEX-5 familes. do you know any low price small FPGA which supports > the SERDES feature as we want. (In our current design the telecombuses > from the tributary cards are directly connected from the tributary > cards to the FPGA on the OIU card). > Meanwhile, if we don't want to have SERDES, and just use the ordinary > I/O's for communication, we would need a (233.28MHz=19.44Mhz*12) 233.28 > MHz clock in each of the E1 tributary cards and a 933.12 MHz clock on > the data card to transmit the 12-bit telecombuses serially. Meanwhile > we should also transmit the 233.28 MHz and 933.12MHz clock on the > backplane. Am I right? have you any other idea about this? > > > The SerDes are often used after the protocol layer but isn't needed in an > > application with protocol. The FPGAs have this functionality as a more > > generic function than you might perceive. > > > > Two cautions for your application: > > > > First, the clocks must be supplies separately for your links; the FPGA logic > > doesn't deal well with plesiochronous signals alone though some SerDes > > blocks might support some form of clock recovery. If you have the local > > clock available and can communicate that clock with the 622 Mb/s data, you > > should be in good shape. > > > > Second, these signals can *not* be used for timing. The jitter requirements > > for the SDH signals are sincerely more strict that what you should expect > > from the FPGAs. As with most SDH designs, you should only introduce signals > > onto the line that are within the ITU-T jitter limits. > > > They won't surely be used for timing. > > As long as all your data shuffling is internal to your system and you're > > retimed for all your transmitters with the appropriate low-jitter circuitry, > > today's FPGAs can really carry you well. > > > But we should be sure that neither of theses 12 bits are shuffled. > Because the SDH chip needs these 12 signals in its correct timing > position. > > Oh - and did you have two questions? > > > > - John_H > > > > > > "Arash" <arash.majd@gmail.com> wrote in message > > news:1163175421.380944.121850@h48g2000cwc.googlegroups.com... > > > Hello > > > I have got a problem in SERDES chip selection that I would be grateful > > > if someone helps me in this regard. First, I explain the system that we > > > have. We want to design an STM-4 SDH system which has 5 tributary > > > cards and 1 optical STM-4 line card.The tributary cards are of two > > > types : E1 card and data card. The E1 tributary card which contains an > > > SDH E1 mapper, has a 12-pin telecombus in 19.44 MHz rate in each of > > > its transmit and receive directions (each card has 24 pins in > > > backplane). but the Data tributary card which contains an EoS device on > > > itself, has a 12-pin telecombus in 77.76MHz rate in each of the > > > transmit and receive directions.The pslot of the optical line card is > > > fixed but each of the tributary cards can sit in any position of the 5 > > > tributary slots. to reduce the number of the pins on the backplane we > > > want to serialize the telecombuses between the optical line card and > > > the tributary cards. Since we do not know which of the tributary cards > > > is inserted in in each slot we should select a SERDES which can > > > serialize the data from both of the rates of 19.44 and 77.76 MHz (But > > > during my searches in different vendors I haven't been able to find > > > such a chip). I have got 2 questions. > > > 1- As I have seen in different vendors pages, most of the SERDES > > > devices are placed after a protocol device. for transmitting SDH > > > http://www.pmc-sierra.com/products/details/pm5309/ Probably an overkill for your requirements but if the price is right why not? If you insist on solution based on low-cost FPGA I'd recommend a compromise - parallel DDR bus with 3 data lanes running at 311MT/s. Internally FPGA would run at 155.52MHz which is manageable even for cheap Cyclon2 or Spartan3.Article: 111948
Vivian Bessler schrieb: > Hi Annti, > I don't see your name among our evaluation or full license users. > > If you need any assistance our support team will be happy to help you out. > > Vivian hi Vivian 1 my name first name is Antti 2 to my understanding the usual policy of online licensing is that the information submitted is handled as confidential. So your public post about my name being or not being on the list of the people who have submitted data to your website is either violation of such common confidentiality policy or your company doesnt have such policy at all. ... There are tools that work. And there are tools that do not. Getting the JTAG communication to work with Cable III is something that is REALLY easy to handle. I was hoping to see some real results, but only witnessed cable communication faults. Not very promising. AnttiArticle: 111949
<darren.redmond@gmail.com> wrote in message news:1163437517.697967.262730@f16g2000cwb.googlegroups.com... > > Not everything happens to be a conspiracy theory. That's true, but then not everybody posting to Usenet is honest. Personally, I find it hard to believe that a machine called 83-70-72-77.b-ras1.srl.dublin.eircom.net is a news-server, especially when one person posting from that address is actually using a news-server called news.indigo.ie (194.125.133.14) and the other is using Google Groups and not a local news-server at all. But perhaps it is some kind of gateway machine that you all appear as though you're connecting from in your office block. I would respectfully suggest that if you're going to post to Usenet for the first time, in support of a commercial posting which is only a couple of hours old, and you're sharing the same IP address as the original commercial poster, that it would be a good idea to be as up-front about the relationship as possible. Otherwise cynics like me jump to conclusions, partly because I've seen it before. Will
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