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Messages from 124000

Article: 124000
Subject: 1/2 Convolutional Encoding of CNAV Data
From: mits130 <amitpatel130@gmail.com>
Date: Mon, 10 Sep 2007 10:25:05 -0700
Links: << >>  << T >>  << A >>
Does anyone know how to implement a 1/2 (1 binary bit in, 2 out,
message length of 7) convolutional encoder in HDL?  I am trying to
implement the encoding of CNAV data and am unclear of where the tap
points would be as well as the initial state of the shift register.


Article: 124001
Subject: Re: VHDL Synthesis Error
From: Andy <jonesandy@comcast.net>
Date: Mon, 10 Sep 2007 10:35:47 -0700
Links: << >>  << T >>  << A >>
On Sep 10, 11:28 am, Mike Treseler <mike_trese...@comcast.net> wrote:
> ray.delvecc...@gmail.com wrote:
> > I am new to VHDL, so I'm not quite sure why I'm getting this error or
> > how I should go about fixing it.
>
> Maybe load_prev <= load; should be inside the clocked IF.
>
> In general, to fix problems like this requires a vhdl simulator.
>
> You would get more responses by posting to comp.lang.vhdl
>
>        -- Mike Treseler

Not all synthesis tools allows signal assignments inside clocked
processes, but outside the clocked IF statement. I'm pretty sure those
that do will not allow the right hand side expression to contain
signals (must use variables, constants, etc.).

Andy


Article: 124002
Subject: Re: Is it possible to perform gate level simulation on a design without a reset?
From: Andy <jonesandy@comcast.net>
Date: Mon, 10 Sep 2007 10:51:29 -0700
Links: << >>  << T >>  << A >>
On Sep 8, 6:39 pm, John_H <newsgr...@johnhandwork.com> wrote:
> KJ wrote:
> > "John_H" <newsgr...@johnhandwork.com> wrote in message
> >news:13e07ln903ocg34@corp.supernews.com...
> >> <aclegg1...@googlemail.com> wrote in message
> >>news:1189090543.879764.76630@r29g2000hsg.googlegroups.com...
> >>> Hi,
> >> It's because of the simulation/synthesis mismatch that I've very dutifully
> >> added those pitifully unnecessary async resets throughout my recent
> >> designs except for the logic that I *know* will perform better (where
> >> performance is needed) without the constraints of an async reset.
>
> > Not following why you would do this and just what simulation/synthesis
> > mismatch you're talking about.  A flip flop that doesn't *need* to be reset
> > will be an unknown so if the simulation says that some output is an 'X', but
> > the design functionally performs what you want it to do in simulation even
> > with the 'X', then there is no mismatch that needs to be resolved...and
> > certainly not by adding an otherwise unneeded reset.
>
> > One such situation would be an output interface that has say a data bus and
> > an output data qualifier.  If the data bus is 'X' but the output data
> > qualifier is false then there should be no compelling reason to put resets
> > on the data bus outputs.  I realize there a bunch of other scenarios, but
> > there is generally no requirement for all storage elements in a design to
> > get into a known particular state at 'reset'.  If the simulation model for
> > the system works as intended and passes all testbench tests then you've
> > properly initialized all of the storage elements that are required.  This is
> > true whether doing a sim based on the original source code or the post-route
> > sim (assuming that you've also passed static timing analysis).
>
> > KJ
>
> If one designs with programmable logic, the simulation will not provide
> adequate results with all Xs.
>
> The flops that don't need reset that we're talking about are the ones
> that configure to known states and those known states are necessary for
> a starting point for synthesis to begin from.  A count incrementing from
> X to X doesn't provide the simulation results needed.
>
> It's not "all storage elements" that I want to have brought to a known
> state for simulation, it's the registers that have known power-up states
> that the simulation is unaware of.
>
> The discussion is about adding async reset to establish unequivocally
> what the power up state is for both simulation and synthesis.
>
> I'm looking forward to the day when I can assign my registers, SRLs, and
> simple ROMs and RAMs initial values by declaring my vectors with initial
> states.  My synthesis tool *still* doesn't support "reg [3:0] myFour =
> 4'h4;" style syntax, ignoring the construct.  XST has supported the
> construct but didn't do a great job with SRLs a while back, breaking the
> SRL at each binary 1 in the initialization.  Initial blocks and
> declaration initial statements would make life *so* much easier for me.
>   Assuming, that is, that the synthesizer doesn't implement gratuitous
> "optimizations" that are inefficient in the end.
>
> I just ask too much of my tools, sometimes.
>
> - John_H

Unless you also take steps to deal with the asynchronous transition
from configuration to operation (e.g. the first clock edge), relying
on initial values from the object declaration will not guarantee
reliable results in hardware.

There are methods of dealing with the clock side of this timing
relationship (e.g. delaying the clocks until "well after" end of
configuration), but otherwise, most methods look an awful lot like a
synchronous reset or clock enable anyway, and are often much harder to
review/audit.

Andy


Article: 124003
Subject: Re: VHDL Synthesis Error
From: "Ray D." <ray.delvecchio@gmail.com>
Date: Mon, 10 Sep 2007 18:05:01 -0000
Links: << >>  << T >>  << A >>
On Sep 10, 1:35 pm, Andy <jonesa...@comcast.net> wrote:
> On Sep 10, 11:28 am, Mike Treseler <mike_trese...@comcast.net> wrote:
>
> > ray.delvecc...@gmail.com wrote:
> > > I am new to VHDL, so I'm not quite sure why I'm getting this error or
> > > how I should go about fixing it.
>
> > Maybe load_prev <= load; should be inside the clocked IF.
>
> > In general, to fix problems like this requires a vhdl simulator.
>
> > You would get more responses by posting to comp.lang.vhdl
>
> >        -- Mike Treseler
>
> Not all synthesis tools allows signal assignments inside clocked
> processes, but outside the clocked IF statement. I'm pretty sure those
> that do will not allow the right hand side expression to contain
> signals (must use variables, constants, etc.).
>
> Andy

That's interesting, although the component I use to transmit this
packet assigns the input to the output within a clocked if-statement,
and I have tested this down to the board with another experiment.
Here is the transmit code.  The output from the packet generator
(packet_out) is connected to the input of the transmit block
(datatosend).  Any other ideas?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TX is
        port (  clkin : in  std_logic;
                reset : in std_logic;
                datatosend: in std_logic_vector (5 downto 0);
                din : out  std_logic_vector (5 downto 0));
end TX;

architecture behavioral of TX is
begin

        TX_proc: process (clkin, reset) is
        begin
                if reset = '0' then
                        din <= "000001";
                elsif (clkin'event and clkin = '1') then
                        din <= datatosend;
                end if;
        end process TX_proc;

end behavioral;



Article: 124004
Subject: Question about Virtex-4 DCM
From: ghelbig@lycos.com
Date: Mon, 10 Sep 2007 20:27:49 -0000
Links: << >>  << T >>  << A >>
I have an application where I need to model a circuit that has two
power rails.

A Vitrex-4 has only one internal power rail, so I was thinking about
disabling the DCM to simulate a power-down.

This would be done by taking the signal that is normally used to
enable power to the rest of the chip, and using it to remove the reset
from the DCM.

I'm not concerned with DCM weirdness during start-up; I have to deal
with similar issues when powering up a section of the chip at a time.

Any comments?  Has anyone actually tried this?

Thanks,
Gary.


Article: 124005
Subject: Re: What is called carry chain structure in FPGA is called in IC?
From: "John_H" <newsgroup@johnhandwork.com>
Date: Mon, 10 Sep 2007 13:57:14 -0700
Links: << >>  << T >>  << A >>
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:1189440832.554409.102540@g4g2000hsf.googlegroups.com...
> Hi,
> I want to know what is called carry chain structure in FPGA is called
> in IC?
>
> Thank you.
>
> Weng

Logic?

Depending on the library, you may have carry look-ahead structures 
implemented or other optimized structures.  It ends up as logic but with 
ASIC specific implementation brought on by the library optimizations. 



Article: 124006
Subject: Re: What is the name of Altera latest and most advanced chip serial that is compatible in technology with Virtex-5 in terms of system strucute(LUT6...)
From: "John_H" <newsgroup@johnhandwork.com>
Date: Mon, 10 Sep 2007 14:01:51 -0700
Links: << >>  << T >>  << A >>
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:1189440628.616782.132240@o80g2000hse.googlegroups.com...
> Hi,
> I would like to know what is the name of Altera latest and most
> advanced chip serial that is competable in technology with Xilinx
> Vertex V in terms of system strucute(LUT6..., not 65nm).
>
> Thank you.
>
> Weng

You won't have an identical mapping between manufacturers.

The Altera Stratix-II, Stratix-III, and Arria GX families should all 
implement their ALM structures which can provide full LUT6 results in a 
structure shared between two registers.  The Xilinx LUT6 is per-register for 
the Virtex-5.  Your serial speed or specific interface requirements may 
eliminate the Arria GX from consideration, but this very new family is 
cheaper for production than the more flexible Stratix series devices.

Do a little reading on the Altera families and get to know them on your own. 
It could be that your needs don't map to our assumptions on what you really 
need.  The family overviews shouldn't take a significant amount of your 
time.  FAEs may also provide you with pertinent data.

- John_H 



Article: 124007
Subject: Re: load/read/ commands assembly PowerPC. Help Needed!
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Mon, 10 Sep 2007 14:04:36 -0700
Links: << >>  << T >>  << A >>
Correct syntax for the assembly would be:
	lis r1, 0xa0008001@h
	ori r1,r1,0xa0008001@l
	lwz r1, 0(r1)

The first two lines load the address into r1. The third line reads the 
value at the address of r1 and stores it in r1 (overwriting the address 
in r1).

- Peter


xenix wrote:
> Hello all,
> 
> I am trying to load a 32bit data (word) from the PortB of a BRAM to a
> GPR (general purpose register) of the PowerPC.
> 
> Address Map for Processor ppc405_0
> (0b0000010000-0b0000010011) ppc405_0
> (0b0000100000-0b0000100011) ppc405_0
> (0xa0008000-0xa000ffff) docm_cntlr docm
> (0xffff8000-0xffffffff) iocm_cntlr iocm
> 
> i am using the LWZ command like LWZ r1, r1 (0xa0008001) but is not
> working. which is the right syntax for the specific adresses?
> 
> regards
> 

Article: 124008
Subject: Re: Is it possible to perform gate level simulation on a design without a reset?
From: "John_H" <newsgroup@johnhandwork.com>
Date: Mon, 10 Sep 2007 14:06:50 -0700
Links: << >>  << T >>  << A >>
"Andy" <jonesandy@comcast.net> wrote in message 
news:1189446689.577245.64490@22g2000hsm.googlegroups.com...
<snip>
>
> Unless you also take steps to deal with the asynchronous transition
> from configuration to operation (e.g. the first clock edge), relying
> on initial values from the object declaration will not guarantee
> reliable results in hardware.
>
> There are methods of dealing with the clock side of this timing
> relationship (e.g. delaying the clocks until "well after" end of
> configuration), but otherwise, most methods look an awful lot like a
> synchronous reset or clock enable anyway, and are often much harder to
> review/audit.
>
> Andy


I agree.  Part of designing a robust system with or without resets is making 
structures that come out of async reset conditions without confusion where 
an async reset caught by different flops on different sides of the clock 
edge work cleanly.  A synchronous (deassertion of) reset covered by timing 
constraints provides the best assurance of clean startup with no startup 
issues.

It is certainly difficult to review/audit both systems without reset or with 
deassertions of asynchronous resets.

- John_H 



Article: 124009
Subject: Re: How to simple convert a hex or mif file from Altera to Xilinx coe file?
From: Gabor <gabor@alacron.com>
Date: Mon, 10 Sep 2007 14:22:58 -0700
Links: << >>  << T >>  << A >>
On Sep 7, 9:12 am, Bernard Esteban
<esteban.bernard***spam...@wanadoo.fr> wrote:
> Hi,
>
> How to simple convert a hex or mif file from Altera to Xilinx coe file?
>
> Do you know any little software?
>
> Regards
>
> Bernard Esteban
> MAF Agrobotic


I'm not familiar with the Altera hex file format, but the Xilinx .coe
format is very simple.  Normally if you have your data as a comma-
separated
list of hex values (no quotes or other prefix/suffix on the values,
but
whitespace is allowed), you can just insert something like

memory_initialization_radix=16;
memory_initialization_vector=

at the beginning of the file, and end with a semicolon after the last
hex value, so the whole thing might look like:

memory_initialization_radix=16;
memory_initialization_vector=
00000000, 608edb80, 30476dc0, 50c9b640, 9823b6e0, f8ad6d60, a864db20,
c8ea00a0,
4c11db70, 2c9f00f0, 7c56b6b0, 1cd86d30, d4326d90, b4bcb610, e4750050,
84fbdbd0,
2608edb8, 46863638, 164f8078, 76c15bf8, be2b5b58, dea580d8, 8e6c3698,
eee2ed18,
 . . . more lines removed here . . .
52568b75, 32d850f5, 6211e6b5, 029f3d35, ca753d95, aafbe615, fa325055,
9abc8bd5,
384fbdbd, 58c1663d, 0808d07d, 68860bfd, a06c0b5d, c0e2d0dd, 902b669d,
f0a5bd1d,
745e66cd, 14d0bd4d, 44190b0d, 2497d08d, ec7dd02d, 8cf30bad, dc3abded,
bcb4666d;

The actual names for the radix and vector parameters may depend on
the core you're generating.

HTH,
Gabor


Article: 124010
Subject: Re: Free downloadable PDF graph paper.
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Mon, 10 Sep 2007 16:05:23 -0600
Links: << >>  << T >>  << A >>
Symon wrote:
> Dear All,
> I found this online and found it useful. Maybe you will too.
> http://incompetech.com/graphpaper/
> Cheers, Syms. 
> 
> 
Where are the Smith charts?  I worked with an RF engineer once who was 
still plotting Smith charts by hand and he said he had to order pads 
from Smith's widow, who apparently owned some patent on the pattern.
-Kevin

Article: 124011
Subject: Re: VHDL Synthesis Error
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 10 Sep 2007 16:21:08 -0700
Links: << >>  << T >>  << A >>
I'm not sure you're getting what Mike originally said.
You have:
end if;
load_prev <= load;
end process PG_proc;

and we gotta believe that it should be:
load_prev <= load;
end if;
end process;

Unfortunetley, I haven't been able to reproduce your
problem on my Xilinx platform, so I am guessing that
the sensitivity list allows Xilinx people to put that
load_prev after the clock end if statement without an
issue. I also waveform simulated the design with ModelSim.
All seems OK. If you are running Xilinx then I don't
know what the problem is. Not all synthesizers are the
same.

I would also suggest putting
load_prev <= (others=>'0'); in your reset if, rather than
initializing it in the signal declaration.

Brad Smallridge
Ai Vision




Article: 124012
Subject: Re: What is the name of Altera latest and most advanced chip serial that is compatible in technology with Virtex-5 in terms of system strucute(LUT6...)
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 10 Sep 2007 17:42:01 -0700
Links: << >>  << T >>  << A >>
On Sep 10, 2:01 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
> "Weng Tianxiang" <wtx...@gmail.com> wrote in message
>
> news:1189440628.616782.132240@o80g2000hse.googlegroups.com...
>
> > Hi,
> > I would like to know what is the name of Altera latest and most
> > advanced chip serial that is competable in technology with Xilinx
> > Vertex V in terms of system strucute(LUT6..., not 65nm).
>
> > Thank you.
>
> > Weng
>
> You won't have an identical mapping between manufacturers.
>
> The Altera Stratix-II, Stratix-III, and Arria GX families should all
> implement their ALM structures which can provide full LUT6 results in a
> structure shared between two registers.  The Xilinx LUT6 is per-register for
> the Virtex-5.  Your serial speed or specific interface requirements may
> eliminate the Arria GX from consideration, but this very new family is
> cheaper for production than the more flexible Stratix series devices.
>
> Do a little reading on the Altera families and get to know them on your own.
> It could be that your needs don't map to our assumptions on what you really
> need.  The family overviews shouldn't take a significant amount of your
> time.  FAEs may also provide you with pertinent data.
>
> - John_H

Hi John_H,
Based on your suggestion I thought it is Stratix-III I want.

"Your serial speed or specific interface requirements may
eliminate Arria GX from consideration, but this very new family is
cheaper for production than the more flexible Stratix series devices."

Thank you very much.

Weng


Article: 124013
Subject: Re: What is called carry chain structure in FPGA is called in IC?
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 10 Sep 2007 17:42:52 -0700
Links: << >>  << T >>  << A >>
On Sep 10, 1:57 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
> "Weng Tianxiang" <wtx...@gmail.com> wrote in message
>
> news:1189440832.554409.102540@g4g2000hsf.googlegroups.com...
>
> > Hi,
> > I want to know what is called carry chain structure in FPGA is called
> > in IC?
>
> > Thank you.
>
> > Weng
>
> Logic?
>
> Depending on the library, you may have carry look-ahead structures
> implemented or other optimized structures.  It ends up as logic but with
> ASIC specific implementation brought on by the library optimizations.

Hi John_H,
Is it called priority tree?

Weng


Article: 124014
Subject: Re: How to simple convert a hex or mif file from Altera to Xilinx
From: Mark McDougall <markm@vl.com.au>
Date: Tue, 11 Sep 2007 11:04:19 +1000
Links: << >>  << T >>  << A >>
Gabor wrote:

> I'm not familiar with the Altera hex file format, 

It's the standard Intel HEX format.

MIF is also absolutely trivial - a short ascii-text header and a list of
(decimal) addresses and hex values.

Sounds like 10 mins work to whip up a C program to convert between all 3
formats for someone with even basic C skills... when I was using MIF files
(I avoid them now) I did a bin2mif app in a handful of lines.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 124015
Subject: Re: LVDS pin placing on CYCLON II problem
From: "Rob" <robnstef@frontiernet.net>
Date: Tue, 11 Sep 2007 01:32:11 GMT
Links: << >>  << T >>  << A >>
Quartus will not allow a non-differential signals within I believe 4 pins of 
a differential signal.  The solution is to move the single-ended signal away 
from the differential pair.  The reason for this has to do with maintaining 
the integrity of the differential signal.  A single ended signal running 
next to either the positive or negative end of a diff pair could induce 
single ended noise; and diff signals are only good at rejecting common-mode 
noise.

Something else to beware of, depending on the device and whether the 
differential signals are inputs or outputs, is that the bank voltage where 
the differential signals reside may have to be powered by 2.5V.  This may 
negatively impact your single ended signal causing it not to meet the VINhi 
levels of the device it is tied to.




"Górski Adam" 
<gorskia@.................wp....................pl..................> wrote 
in message news:fc3jmt$4s8$1@atlantis.news.tpi.pl...
> Hi,
>
> I'm working on design with LVDS signals and when I'm trying to place LVDS 
> inputs at dedicated pins I got :
>
> Error: Non-differential I/O pin addr[8] in pin location 86 and pad 103 too 
> close to differential I/O pin clk_pll(n) in pin location 90 and pad 107 --  
> pins must be separated by a minimum of 4 pads
>
>
> And I don't know why ? How can it be too close ? Is any workaround for 
> this ? (CYCLON II 2C5)
>
> Adam 



Article: 124016
Subject: Re: What is called carry chain structure in FPGA is called in IC?
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 11 Sep 2007 03:18:47 GMT
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:
> On Sep 10, 1:57 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
>> "Weng Tianxiang" <wtx...@gmail.com> wrote in message
>>
>> news:1189440832.554409.102540@g4g2000hsf.googlegroups.com...
>>
>>> Hi,
>>> I want to know what is called carry chain structure in FPGA is called
>>> in IC?
>>> Thank you.
>>> Weng
>> Logic?
>>
>> Depending on the library, you may have carry look-ahead structures
>> implemented or other optimized structures.  It ends up as logic but with
>> ASIC specific implementation brought on by the library optimizations.
> 
> Hi John_H,
> Is it called priority tree?
> 
> Weng

It's possible - though unlikely - that a priority tree (often used for 
if/else blocks or case statements) would be used to implement the carry 
structure in ASIC-optimized netlists.

There is no single answer for your query.  It will be vendor-specific 
since different compilers will optimize the code to different optimized 
libraries.

Article: 124017
Subject: Re: What is called carry chain structure in FPGA is called in IC?
From: Peter Alfke <alfke@sbcglobal.net>
Date: Mon, 10 Sep 2007 21:22:43 -0700
Links: << >>  << T >>  << A >>
On Sep 10, 9:13 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I want to know what is called carry chain structure in FPGA is called
> in IC?
> Thank you.
> Weng

Weng, the objective of the carry chain is easily defined: It
facilitates binary addition and subtraction, where any bit position
can affect the next higher bit position with a binary carry or borrow
signal.

The physical implementation can vary a lot, using different
compromises between speed and complexity (and perhaps power
consumption). There is ripple carry, carry look-ahead, carry
anticipate, and even more exotic methods. The FPGAs I am familiar with
use carry-look-ahead over 2 or 4 bits, which is just one step ahead of
the simplest ripple-carry. But since the FPGA carry structure is hard-
wired, it usually is faster than any more exotic scheme, if ithat were
implemented in an FPGA. At least in the usual range below 32 bits...
ASIC trade-offs are different.
Peter Alfke


Article: 124018
Subject: Re: Minimize power consumption
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 10 Sep 2007 21:43:07 -0800
Links: << >>  << T >>  << A >>
drop669@gmail.com wrote:

> I have a special y=f(x) function. It takes 32 bit at input and it have
> something at output. Function is unrolled, it computes result alsmost
> "immediately", and it doesn't contain any memory cells and flip-flops,
> it is what called "combinatorial".
> I need to fill a table of all possible x's and function results. If x
> is 32-bit, I just make 32-bit counter connected to the block which
> compute the result and collect results.

> But I feel that by rewiring bus between counter and f(x) block, I can
> reduce the number of gates changed its state at each counter's
> iteration, and vice versa. Thus to reduce power consumption.
> (I may have x in any order, my task is just to have all possible
> values of x at some moment).
> So, is there any tool that can take my f(x) in form of Verilog or VHDL
> and tell me what is the most optimal wiring scheme?

In general, I would say no.  If the design is in structural
verilog (or the VHDL equivalent), directly instantiating gate
level primitives then it might be possible.  (Synthesis from
behavioral verilog is likely not unique.)

It might be that the design can't have any loops.
(They aren't necessarily excluded from combinatorial logic,
as long as they are guaranteed to resolve.)  Then iterate through
the design computing how many gate changes are caused by changes
in the inputs for a given set of other inputs.  It would seem
likely that gray code (one input changing at a time) is the best
choice, but that isn't guaranteed.

-- glen


Article: 124019
Subject: Uses of Gray code in digital design
From: richard.melikson@gmail.com
Date: Tue, 11 Sep 2007 05:55:24 -0000
Links: << >>  << T >>  << A >>
Hello,

Most books on digital design discuss Gray codes. However, most of the
focus is on generating these codes, rather than detailing their uses.

I read the Wikipedia article: http://en.wikipedia.org/wiki/Gray_code,
but it doesn't provide enough in-depth information of the uses of Gray
code in hardware.

I know Gray codes are used for:

1) Encoding state machine states. Why is it an advantage to use Gray
codes here ?
2) Async FIFO addressing between clock domains. Could anyone elaborate
on this ?
3) Error correction in digital communications. Again, I'd love to hear
some more details about this.

In general, what are the other uses of these codes? When was the last
time you needed Gray codes in your design and for what purpose ?

R


Article: 124020
Subject: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
From: Douglas <j.d.morrison@gmail.com>
Date: Tue, 11 Sep 2007 06:13:28 -0000
Links: << >>  << T >>  << A >>
On Sep 3, 7:59 pm, iko...@alumni.technion.ac.il wrote:
> It's about half of Xilinx Coolrunner-II
> consumption and a small fraction of Xilinx FPGAs (Spartan or Virtex)
> for same functionality.

Which Xilinx parts you used as a comparison point? I don't have
expertise on Actel parts, but they seem to have 'quite' optimistic
marketing gates readings, so comparing 250k part to 250k part might
not be fair.

On a related topic - does anyone have expertise about the trade-offs
of Actel's "Versa-Tiles" vs. 4/6-LUTs. It seems like obviously
wastefull configuration - how many thansistors they can really share
between 3-LUT and D-FF? Is there some benefit in this configuration,
or is this 'design choice' made just to avoid Altera and Xilinx
patents?

- Doug


Article: 124021
Subject: Re: Uses of Gray code in digital design
From: Peter Alfke <alfke@sbcglobal.net>
Date: Mon, 10 Sep 2007 23:16:48 -0700
Links: << >>  << T >>  << A >>
On Sep 10, 10:55 pm, richard.melik...@gmail.com wrote:
> Hello,
>
> Most books on digital design discuss Gray codes. However, most of the
> focus is on generating these codes, rather than detailing their uses.
>
> I read the Wikipedia article:http://en.wikipedia.org/wiki/Gray_code,
> but it doesn't provide enough in-depth information of the uses of Gray
> code in hardware.
>
Binary-coded counter sequences often change multiple bits on one count
transition. That can (will) lead to decoding glitches, especially when
counter values are compared for identity.
Gray-coded count sequences always change one, and only one, bit on
each transition. Comparing two such counters for identity will thus
never generate a decoding glitch.
That is the reason for Gray codes counters in FIFO addressing, where
FULL and EMPTYis established by comparing two asynchronously clocked
counters for identity. Gray code addressing is a must for asynchronous
FIFOs..

The "one bit change per transition" advantage occurs only in counters,
or under other very restrictive circumstances. I do not see an
advantage in general state machines, where sequences are not as
predictable.

Gray-coded counters use on average half the number of transitions,
compared to binary counters. That's a dynamic power advantage.

And yes, Gray is spelled with an a, since it is named for its
inventor.

Anybody else have any comments?
Peter Alfke

>


Article: 124022
Subject: Re: Question about Virtex-4 DCM
From: austin <austin@xilinx.com>
Date: Mon, 10 Sep 2007 23:27:01 -0700
Links: << >>  << T >>  << A >>
Gary,

There is the BUFGMUX, which will allow you to switch from a clock, to 
another.

Set it for asynchronous operation (allows a switch to a dead clock), 
,and then just switch over to a BUFG which has no clock on it (connected 
to a '0' or a '1').

I believe that RESET will also work, but as you say, there will be 
transitions that may occur, and if you just want everything to cease, 
the BUFGMUX may be a better test.

Austin (at RADECS 2007, in Deauville, Fr)

Austin

Article: 124023
Subject: Re: Uses of Gray code in digital design
From: Jonathan Kirwan <jkirwan@easystreet.com>
Date: Tue, 11 Sep 2007 06:41:13 GMT
Links: << >>  << T >>  << A >>
On Mon, 10 Sep 2007 23:16:48 -0700, Peter Alfke <alfke@sbcglobal.net>
wrote:

><snip>
>And yes, Gray is spelled with an a, since it is named for its
>inventor.
><snip>

Gray codes were discovered by the French engineer, Emile Baudot, but
named after Frank Gray, a Bell Labs researcher, who patented their
general application in 1953 (at a time when, I suspect, when Bell Labs
folks were busy patenting many other things they didn't invent.)

Jon

Article: 124024
Subject: Re: Uses of Gray code in digital design
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Tue, 11 Sep 2007 18:56:22 +1200
Links: << >>  << T >>  << A >>
richard.melikson@gmail.com wrote:

> Hello,
> 
> Most books on digital design discuss Gray codes. However, most of the
> focus is on generating these codes, rather than detailing their uses.
> 
> I read the Wikipedia article: http://en.wikipedia.org/wiki/Gray_code,
> but it doesn't provide enough in-depth information of the uses of Gray
> code in hardware.
> 
> I know Gray codes are used for:
> 
> 1) Encoding state machine states. Why is it an advantage to use Gray
> codes here ?

It depends on the state machine. One's with complex state-state jumps,
will find it hard to follow a Gray pattern, but if the state engine
is Spin-Phase-Sync in nature (ie simple circular states, with 'waits'
and decodes ), then Gray can work well.


<snip>
> In general, what are the other uses of these codes? When was the last
> time you needed Gray codes in your design and for what purpose ?

Gray codes are also common in Absolute Rotary encoders.
You could also argue that quadrature encoders, and Stepper Motor
drive, are special 2 bit cases of Gray counters.

-jg





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