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Messages from 124400

Article: 124400
Subject: Re: Comparing Adder synthesis techniques
From: David R Brooks <davebXXX@iinet.net.au>
Date: Fri, 21 Sep 2007 02:33:41 +0800
Links: << >>  << T >>  << A >>
Joseph wrote:
> Hi,
> 
> I am working on a study to copmpre the effiency of synthesied adders.
> I have built a ripple adder and a carry look ahead using VHDL for a
> Virtex FPGA. I know that the lookahead carry adder is much faster than
> the ripple carry adder but when I synthezied both fro a 16 bit adder
> i got only an improvement of 2ns using the lookahead carry adder.
> 
> For the lookahead adder i built a 1 bit adder which generates the
> P,G,Sum and Carry and than built the lookahead logic using standard
> techniques. The carry in was computed as :
> 
> C(i) <= G(i-1) or ( P(i-1) and C(i-1);
> 
> Finally i added the inputs and the Carries.
> 
> Can someone telle me if i did wrong implementation or give me some
> tips how to code it properly.
> 
> Thanks a lot
> 
If your ripple carry adder was just A <= B+C (or similar), XST will 
invoke Virtex' high-speed carry-chain hardware. This would not happen in 
the lookahead case. So it's not a straight comparison.

Article: 124401
Subject: Re: Gated Clock Problems
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Thu, 20 Sep 2007 13:38:49 -0500
Links: << >>  << T >>  << A >>
>If the clock to out can be arbitrary long, how would the above proposed
>solution with the extra synchronizer DFF solve the problem? If the setup
>of the synchronizer DFF is violated (which is inevitable as the D-input
>is an external signal), it's output may violate the input setup time
>of the synchronous system for the next clock edge.

You have to wait long enough.  Long "enough" has to be defined by
your application.

Metastability decays exponentially so waiting a little longer is a big help.
In many cases, waiting a clock cycle gives a probability of trouble
that is very very very low.  You see jokes about 1 event until the
sun goes nova, but numbers like that are reasonable.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 124402
Subject: Re: DMA scatter gather with PLB bus?
From: Jeff Cunningham <jcc@sover.net>
Date: Thu, 20 Sep 2007 14:44:22 -0400
Links: << >>  << T >>  << A >>
cesarp wrote:
> Hi everyone.
> I'm trying to transfer data from DDR memory to a custom PLB_IPIF
> peripheral in a Virtex II Pro XUP card. I have some questions:
> 1. In EDK is not possible to configure a scatter-gather DMA access
> with PLB in the Peripheral wizard. Why?
> 2. I'm trying to transfer data using simple DMA under linux 2.4
> compiled for PPC405, but the system crash when it is inicialized the
> DMA transfer. Totally dead. I'm keeping in mind the differences
> between physical and virtual addresses in source and destiny
> registers, in fact i have tried with a driver for kernel. In
> standalone mode the DMA transfer works fine. I'm working with EDK
> 8.2 .
> 
> I know there are many things can be wrong, but any help or suggestion
> is appreciated.

Do you have access to chipscope and some spare block rams? With that you 
could trace what the PLB is doing when it dies.

-Jeff

Article: 124403
Subject: Re: Comparing Adder synthesis techniques
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 20 Sep 2007 11:44:41 -0700
Links: << >>  << T >>  << A >>
Joseph wrote:

> I am working on a study to copmpre the effiency of synthesied adders.
> I have built a ripple adder and a carry look ahead using VHDL for a
> Virtex FPGA. I know that the lookahead carry adder is much faster than
> the ripple carry adder but when I synthezied both fro a 16 bit adder
> i got only an improvement of 2ns using the lookahead carry adder.

I expect that an unsigned or natural range adder
just using '+' would work just as well.
Synthesis is quite clever with the carries
for most adder descriptions.

> Can someone telle me if i did wrong implementation or give me some
> tips how to code it properly.

Maybe your expectations about synthesis were wrong.
Have a look at the RTL viewer.

        -- Mike Treseler

Article: 124404
Subject: Re: Clock boundary crossing
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Thu, 20 Sep 2007 13:47:54 -0500
Links: << >>  << T >>  << A >>
>I use at least two anyway to rule out duplication
>of the synchronizing register by synthesis
>(which could eliminate the synchronization effect).
>
>I could do the same thing with constraints,
>but these do not always follow the source
>code around.

Two good points.  Thanks.

What keeps the system from duplicating a pair of FFs?
(Isn't it great that FPGAs have so many FFs?  :)

Has anybody worked on putting constraints in the source code?
Maybe stylized comments with a script to extract them would work.

Assuming you could say what you wanted.  What would that be?
  1) Don't duplicate this FF.
  2) I need at least N ns of slack time on this signal.

Or would it be better to just mark the FF as a synchronizer
and let the script fill in the details.  You probably need
something like that anyway to avoid errors from clock
boundary crossings.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 124405
Subject: Re: Free downloadable PDF graph paper.
From: Guenter <OAONFBZBBGVC@spammotel.com>
Date: Thu, 20 Sep 2007 11:51:44 -0700
Links: << >>  << T >>  << A >>
On Sep 11, 12:05 am, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
>
> Where are theSmithcharts?

For TeX lover I found this link: http://tug.org/PSTricks/main.cgi?file=Examples/Charts/chart


Article: 124406
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Thu, 20 Sep 2007 11:54:11 -0700
Links: << >>  << T >>  << A >>
On Sep 19, 9:05 pm, John_H <newsgr...@johnhandwork.com> wrote:
> Weng Tianxiang wrote:
> > Hi Hal,
> > 8b/10b is perfect for scrambling function. PCI-e uses 8b/10b
> > technology.
>
> > Scramble technology still uses randomized serial and XOR now? After 8b/
> > 10b technology, I think other randomized XOR scramble technology is
> > dying out, is it right?
>
> > IBM got one patent for 8b/10b technology in 1981, Xilinx filed for 23
> > patents on 8b/10b implementation in FPGA on one day in 2004.
>
> > I think that IBM is really a technology leader in almost all respects
> > in computer industry. Xilinx is the leader of FPGA.
>
> > Weng
>
> 80B/10B is not a scrambler.  It's a coding mechanism used to balance the
> DC offset of the encoded stream.  It's a straight encode/decode.
>
> Don't be disappointed and frustrated for what you don't know.- Hide quoted text -
>
> - Show quoted text -
Hi John_H,
8b/10b does the same thing as a scambler does: to balance DC offset,
but does a better job than scambler with 20% bandwidth cost.

For higher data rare, 8b/10b is the only choice. It guarantees that DC
offset is balanced between +- 1 during transmission.

Historically, currently satellite communication stations use scambler
not because scambler saves 20% bandwidth, but when satellite station
standard was established, IBM had the patent on 8b/10b that would
expire in 2001, that is the reason why PCI-e uses 8b/10b technology.

I expect 8b/10b technology will be incooperated in any new data
communication standard, but it cannot replace old standards.

Hi Hal,
Scrambler cannot be counted as a state machine in any sense.

The most important factor for a circuit counted as a state machine is
that its states are mutually exclusive and only one state is active in
any cycle.

Scrambler cannot meet the requirements. If it were, every circuit
would be counted as a state machine.

Shift registers can be counted as a state machine only when only one
bit is set or reset among all its bits. Otherwise it cannot be counted
as a state machine.

Weng



Article: 124407
Subject: hardware software codesign
From: gks.1981@hotmail.com
Date: Thu, 20 Sep 2007 19:02:19 -0000
Links: << >>  << T >>  << A >>
Hi there
I am a newbie to FPGA based development. So I have a Xilinx II board.
What I need to do is basically implement an algorithm on the board and
then use a linux based application to give the inputs to the FPGA and
obtain the corresponding outputs .

So I am having trouble constructing the communication interface. The
Xilinx board has a JTAG and a RS232 port, which I think can be used
for data communication but I am not sure how to proceed. If someone
has any idea how to do this , could you please help me out.

Thanks
-Sid


Article: 124408
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Thu, 20 Sep 2007 12:12:56 -0700
Links: << >>  << T >>  << A >>
Hi JTW,
Your response is suggestive and I would like to see your coding to
determine if they are state machines.

I don't exclude RAM used as state machines.

If you can do it, it is better. Xilinx has an application note devoted
to the BRAM used as state machine and I read the note carefully. But I
never use their ideas to use BRAM . I don't have any idea to use the
BRAM as a tool for 10k state machines.

There are 10 millions bits of BRAM, you must also have a legitimate
reason to use so many state machines in a design. There is seldom a
design in FPGA world that would need 100k state machines for a reason.

My answer to my quiz is much larger than 100k state machines in a
finished design that is open to use for any one in the topic groups.

Weng


Article: 124409
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Shannon <sgomes@sbcglobal.net>
Date: Thu, 20 Sep 2007 19:50:17 -0000
Links: << >>  << T >>  << A >>
On Sep 20, 12:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi JTW,
> Your response is suggestive and I would like to see your coding to
> determine if they are state machines.
>
> I don't exclude RAM used as state machines.
>
> If you can do it, it is better. Xilinx has an application note devoted
> to the BRAM used as state machine and I read the note carefully. But I
> never use their ideas to use BRAM . I don't have any idea to use the
> BRAM as a tool for 10k state machines.
>
> There are 10 millions bits of BRAM, you must also have a legitimate
> reason to use so many state machines in a design. There is seldom a
> design in FPGA world that would need 100k state machines for a reason.
>
> My answer to my quiz is much larger than 100k state machines in a
> finished design that is open to use for any one in the topic groups.
>
> Weng

Thanks Weng.  I can sleep better now.

Shannon


Article: 124410
Subject: Re: Guess: what is the largest number of state machines in a current
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 20 Sep 2007 11:51:43 -0800
Links: << >>  << T >>  << A >>
John_H wrote:
(snip)

> 80B/10B is not a scrambler.  It's a coding mechanism used to balance the 
> DC offset of the encoded stream.  It's a straight encode/decode.

You could say it that way, but if you need a modulation method
for clock recovery it can be used in place of a scrambler and
simpler modulation method.

Modulation is used for different reasons:

1) Clock recovery
2a) Band limited channel
2b) AC coupled system

Considering those, 8B/10B is not so different from a scrambler.

-- glen


Article: 124411
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Thu, 20 Sep 2007 15:00:41 -0500
Links: << >>  << T >>  << A >>
>Hi Hal,
>Scrambler cannot be counted as a state machine in any sense.

Why not?  It has inputs, outputs, and internal state.
Sure looks like a state machine to me.


>The most important factor for a circuit counted as a state machine is
>that its states are mutually exclusive and only one state is active in
>any cycle.

Which part of that does a scrambler not meet?  Remember, I'm
talking about a LFSR type scrambler running in bit serial mode,
not a n 8b/10b encoder.


>Shift registers can be counted as a state machine only when only one
>bit is set or reset among all its bits. Otherwise it cannot be counted
>as a state machine.

Huh?  A shift register seems like an even simpler example of
a state machine that doesn't need a reset to do useful work.

I'm thinking of a simple serial-in, serial-out shift register,
a delay line.  It's "state" is the last N bits shifted in.


If I was explaining a shift register or scrambler to somebody,
I probably wouldn't start by calling it a state machine and drawing
the classic picture of states and transitions, but it might be
handy to use tricks from state machine theory, like if it has
N bits of internal state (aka FFs) it can only have 2^N distinct
states.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 124412
Subject: Re: hardware software codesign
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Thu, 20 Sep 2007 15:07:42 -0500
Links: << >>  << T >>  << A >>
>I am a newbie to FPGA based development. So I have a Xilinx II board.
>What I need to do is basically implement an algorithm on the board and
>then use a linux based application to give the inputs to the FPGA and
>obtain the corresponding outputs .
>
>So I am having trouble constructing the communication interface. The
>Xilinx board has a JTAG and a RS232 port, which I think can be used
>for data communication but I am not sure how to proceed. If someone
>has any idea how to do this , could you please help me out.

How much data to you need to send to/from the FPGA?

If it's only a few bits you may be able to do it with
the Xilinx debugging tools by driving the GUI.

If you want to crunch lots of data, I'd suggest RS-232.
I'd build a RS-232 receiver and transmitter to
do serial/parallel conversion.  Then I'd build a small
state machine to process the received data.

If your data is something like 32 bit words, then the
state machine only has to count to 4, kick off the logic,
and send back 4 bytes of answer.

Your state machine could also put the data into a RAM
and read it from the RAM.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 124413
Subject: Re: Comparing Adder synthesis techniques
From: "John_H" <newsgroup@johnhandwork.com>
Date: Thu, 20 Sep 2007 13:10:38 -0700
Links: << >>  << T >>  << A >>
"Joseph" <jozamm@gmail.com> wrote in message 
news:1190310086.682785.78140@w3g2000hsg.googlegroups.com...
> Hi,
>
> I am working on a study to copmpre the effiency of synthesied adders.
> I have built a ripple adder and a carry look ahead using VHDL for a
> Virtex FPGA. I know that the lookahead carry adder is much faster than
> the ripple carry adder but when I synthezied both fro a 16 bit adder
> i got only an improvement of 2ns using the lookahead carry adder.
>
> For the lookahead adder i built a 1 bit adder which generates the
> P,G,Sum and Carry and than built the lookahead logic using standard
> techniques. The carry in was computed as :
>
> C(i) <= G(i-1) or ( P(i-1) and C(i-1);
>
> Finally i added the inputs and the Carries.
>
> Can someone telle me if i did wrong implementation or give me some
> tips how to code it properly.
>
> Thanks a lot
>
> Joseph

Usually the lookahead adder has n bits of propagate and generate signals, 
not one.  That's where the efficiencies come in.  For bits 24-27, a sum of 
4'h15 is a propagate and the generate out is immediately available to bits 
28-31.  The longest path is the decision to propagate plus the time for the 
first stage generate to pass through the chain of propagate signals.

If you do this one bit at a time rather than several, there isn't much of a 
time savings.

Where are you reading up on what a lookahead architecture brings with it in 
advantages and disadvantages?

- John_H 



Article: 124414
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: "John_H" <newsgroup@johnhandwork.com>
Date: Thu, 20 Sep 2007 13:17:20 -0700
Links: << >>  << T >>  << A >>
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message 
news:8qydnY9KVevHXW_bnZ2dnUVZ_gednZ2d@comcast.com...
> John_H wrote:
> (snip)
>
>> 80B/10B is not a scrambler.  It's a coding mechanism used to balance the 
>> DC offset of the encoded stream.  It's a straight encode/decode.
>
> You could say it that way, but if you need a modulation method
> for clock recovery it can be used in place of a scrambler and
> simpler modulation method.
>
> Modulation is used for different reasons:
>
> 1) Clock recovery
> 2a) Band limited channel
> 2b) AC coupled system
>
> Considering those, 8B/10B is not so different from a scrambler.
>
> -- glen

It's not "so" different, but the advantages of each are different.  The 
items that strike me the most are that 8B/10B provides better DC balance and 
scramblers provide a smoother spread of power across a wider bandwidth. 



Article: 124415
Subject: Re: Clock boundary crossing
From: Alan Nishioka <alan@nishioka.com>
Date: Thu, 20 Sep 2007 13:34:15 -0700
Links: << >>  << T >>  << A >>
On Sep 20, 11:47 am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
> (Isn't it great that FPGAs have so many FFs?  :)

A pessimist would complain about paying for all those FF's he can't
use :-)

Alan Nishioka


Article: 124416
Subject: Re: hardware software codesign
From: "John Retta" <jretta@rtc-inc.com>
Date: Thu, 20 Sep 2007 15:28:34 -0600
Links: << >>  << T >>  << A >>
Okay .... the RS-232 is a serial interface with a uart
block dealing with the parallel (byte wide tx/rx) to serial
data conversion.

Take a look at the Xilinx coregen generator or opencores.org
for uart source code.  I will paste some of one of my own
designs at bottom.

The nice thing about using the RS-232 UART approach is
that with a three wire cable (GND, TX, RX) you can connect
to a serial port on a PC, open the windows utility hyperterm, and
be able to debug your interface.  A starting point might be to
wrap the rx serial data to tx serial data (skip the usarts ... your
just wrapping the tx and rx) and make sure every character you
type is received by hyperterm.  Then you can add the tx and rx usarts ...
and verify the same level of functionality.

If you are a newbie, make sure you get a copy of a simulator (Modelsim)
for debugging your FPGA code.  There is an upfront investment in
learning this tool, but the payback is huge.  Same thing for something
like chipscope, the Xilinx logic analyzer like function.

---------------------------------------------------------------------
    for the tx_uart the clk was approx 20 Mhz (19.91)
    for the rx_uart the sys_clk_100mhz was really 100 mhz.
    you will need to defparam (overide) at one level up where these
   are instantiated, or if you want to change within module that is fine
   also.  Change these values to align with your clk rate, and desired
   baud rate.
---------------------------------------------------------------------

module tx_uart (
  sys_clk_100mhz,
  cr_rst,
  tx_data_ld,
  tx_data_byte,
  tx_byte_done,
  tx_ser_dat_out
);

input        sys_clk_100mhz;
input        cr_rst;
input        tx_data_ld;
input  [7:0] tx_data_byte;
output       tx_byte_done;
output       tx_ser_dat_out;

parameter    TC_19200_VALUE_52p08_us   = 14'h040C;
// parameter    TC_19200_VALUE_52p08_us   = 14'h015B;  // 
TC_57600_VALUE_17p36_us
// parameter    TC_115200_VALUE_8p68_us   = 14'h00AD; // 
TC_115200_VALUE_8p68_us

reg          baud_19200_event, pending_tx_ld, tx_byte_done;
reg    [3:0] txbyte_bit_ctr;
reg    [7:0] txbyte_hold_reg;
reg   [13:0] baud_19200_rate_ctr;
reg   [10:0] sdo_shift_reg;

wire         baud_19200_rate_ctr_tc = (baud_19200_rate_ctr == 14'h0000);
wire         odd_parity = ^~(txbyte_hold_reg[7:0]);
wire         sdo_shift_reg_ld = pending_tx_ld & baud_19200_event;
assign       tx_ser_dat_out = sdo_shift_reg[0];

  always @ (posedge sys_clk_100mhz)
    begin
      baud_19200_event <= baud_19200_rate_ctr_tc;
      pending_tx_ld    <= pending_tx_ld & ~baud_19200_event | tx_data_ld;
      tx_byte_done     <= baud_19200_event & (txbyte_bit_ctr == 4'h1);
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (cr_rst)
        txbyte_bit_ctr  <= 4'h0;
      else if (sdo_shift_reg_ld)
        txbyte_bit_ctr  <= 4'hA;
      else if ((txbyte_bit_ctr != 4'h0) & baud_19200_event)
        txbyte_bit_ctr  <= txbyte_bit_ctr - 1'b1;
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (cr_rst)
        txbyte_hold_reg <= 8'h00;
      else if (tx_data_ld)
        txbyte_hold_reg <= tx_data_byte;
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (cr_rst)
        baud_19200_rate_ctr <= 14'h000A;
      else if (baud_19200_rate_ctr_tc)
        baud_19200_rate_ctr <= TC_19200_VALUE_52p08_us;
      else
        baud_19200_rate_ctr <= baud_19200_rate_ctr - 1'b1;
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (cr_rst)
        sdo_shift_reg <= 11'h7FF;
      else if (sdo_shift_reg_ld)
        sdo_shift_reg <= {1'b1, odd_parity, txbyte_hold_reg, 1'b0};
      else if (baud_19200_event)
        sdo_shift_reg <= {1'b1, sdo_shift_reg[10:1]};
    end


endmodule


module rx_uart (
  sys_clk_100mhz,
  cr_rst,
  sec_ser_dat_rx,
  rx_data_ld,
  rx_data_byte
);

input        sys_clk_100mhz;
input        cr_rst;
input        sec_ser_dat_rx;
output       rx_data_ld;
output [7:0] rx_data_byte;

parameter    START_BIT_DET_TC_VAL = 8'h80;
parameter    TC_19200_VALUE       = 14'h1458;

reg          ser_dat_rx_q;
reg          sample_rx_bit_q, sample_rx_bit_ctr_tc, last_bit_rx;
reg    [8:0] ser_dat_shift_in;
reg    [7:0] start_bit_det_ctr;
reg   [13:0] sample_rx_bit_ctr;
reg          idle_state;
reg    [3:0] rx_bit_ctr;
reg          rx_data_ld;
reg    [7:0] rx_data_byte;

wire         start_bit_det_ctr_tc     = (start_bit_det_ctr == 
START_BIT_DET_TC_VAL);
wire         start_bit_det_ctr_tc_nxt = (start_bit_det_ctr == 
START_BIT_DET_TC_VAL - 1'b1);

  always @ (posedge sys_clk_100mhz)
    begin
      ser_dat_rx_q         <= sec_ser_dat_rx;
      sample_rx_bit_q      <= (sample_rx_bit_ctr == TC_19200_VALUE/2 - 
8'h50);
      sample_rx_bit_ctr_tc <= (sample_rx_bit_ctr == TC_19200_VALUE);
      last_bit_rx          <= (sample_rx_bit_ctr == TC_19200_VALUE) & 
(rx_bit_ctr == 4'hA);
      rx_data_ld           <= last_bit_rx;
      rx_data_byte         <= ser_dat_shift_in[7:0];
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (cr_rst)
        ser_dat_shift_in <= 9'h000;
      else if (sample_rx_bit_q)
        ser_dat_shift_in <= {ser_dat_rx_q, ser_dat_shift_in[8:1]};
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (cr_rst | ser_dat_rx_q)
        start_bit_det_ctr <= 8'h00;
      else if (idle_state & ~ser_dat_rx_q & ~start_bit_det_ctr_tc)
        start_bit_det_ctr <= start_bit_det_ctr - 1'b1;
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (idle_state | sample_rx_bit_ctr_tc)
        sample_rx_bit_ctr <= 14'h0000;
      else
        sample_rx_bit_ctr <= sample_rx_bit_ctr + 1'b1;
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (idle_state)
        rx_bit_ctr <= 4'h0;
      else if (sample_rx_bit_q)
        rx_bit_ctr <= rx_bit_ctr + 1'b1;
    end

  always @ (posedge sys_clk_100mhz)
    begin
      if (cr_rst | last_bit_rx)
        idle_state <= 1'b1;
      else if (start_bit_det_ctr_tc)
        idle_state <= 1'b0;
    end

endmodule


---------------------------------------------------------------------------


-- 
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


<gks.1981@hotmail.com> wrote in message 
news:1190314939.369108.229970@57g2000hsv.googlegroups.com...
> Hi there
> I am a newbie to FPGA based development. So I have a Xilinx II board.
> What I need to do is basically implement an algorithm on the board and
> then use a linux based application to give the inputs to the FPGA and
> obtain the corresponding outputs .
>
> So I am having trouble constructing the communication interface. The
> Xilinx board has a JTAG and a RS232 port, which I think can be used
> for data communication but I am not sure how to proceed. If someone
> has any idea how to do this , could you please help me out.
>
> Thanks
> -Sid
> 



Article: 124417
Subject: Re: Is it possible to perform gate level simulation on a design without
From: Ray Andraka <ray@andraka.com>
Date: Thu, 20 Sep 2007 21:53:05 -0400
Links: << >>  << T >>  << A >>



There are some situations where you don't care about the starting state, 
but it has to be a valid state for the state machine to work (i.e. not 
'X's).  For example, if I have a counter that generates an enable pulse 
every 4th clock and all I need is that 4 clock enable with no need to 
know the phase of it relative to anything else.  That can be done with a 
simple counter with no reset and will work just fine in hardware because 
it starts off in some valid state, you just don't know which one.  If I 
tried to simulate that however, it will start off with all bits set to 
'U' which makes the next state all 'X's and it will never get into the 
operational sequence without some form of initialization.  In Xilinx, 
this can be taken care of using the ROC primitive to provide a 
simulation reset.  ROC gets taken out by the mapper, so there is nothing 
in the hardware (well, it does set the configuration bits for the 
initial value of the connected registers but no user hardware is used).

The situation I see most for this is a simple toggle flip-flop used in 
clock domain crossings.  An event toggles a flip-flop in the sending 
clock domain.  The output of the toggle FF is sent across the domain 
boundary, resynchronized to the receiving clock and then synchronously 
edge detected to produce a one clock wide pulse response to each time 
the toggle FF changes state.  I don't care what state the toggle FF is 
in, all I care about is when it transitions.  The hardware doesn't care, 
because it will always be either a 1 or 0 so it just flips state. 
Simulation does care because it can't invert an unknown state.

Article: 124418
Subject: Re: help! ACTEL PROASIC PLUS clock buffer
From: Thomas Stanka <usenet_10@stanka-web.de>
Date: Thu, 20 Sep 2007 22:19:52 -0700
Links: << >>  << T >>  << A >>
On 20 Sep., 11:36, merche <dora...@gmail.com> wrote:
> On Sep 20, 7:26 am, Thomas Stanka <usenet...@stanka-web.de> wrote:
>
> > On 19 Sep., 17:56, merche <dora...@gmail.com> wrote:
>
> > > Hi!, I have a big problem:
>
> > > I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 global
> > > pin (4 GL macro), I need put a clock in a global buffer but I can=B4t
> > > because I have  others signals with highest fanout. what can I do?
>
> > Explain your real problem. Do you need more global inputs or is it a
> > problem of synthesis? Then instantiate a GL Buffer for the clk in your
> > code
>
> thanks Thomas Stanka! But...
>
> In my code I have instantiated a GL Buffer (is a fast clock). But in
> the synthesis: the log say...
>
> Automatic dissolve during optimization of view:work.w_r9(w_r9) of
> GL2(GL)

There exist no GL2 in the APA library AFAIK. Try GL25 instead.
Instantiating the clk-Buffer in code should work for Synplify.

If nothing helps, you could edit the edif netlist to get a clk-buffer
for the clk input, but this should be done _very_ carefully.

bye Thomas


Article: 124419
Subject: how interfacing of cpld and cpu done?
From: nanaware_amit@rediffmail.com
Date: Fri, 21 Sep 2007 06:16:17 -0000
Links: << >>  << T >>  << A >>
please give me information about inerfacing of cpld xc9572 & cpu


Article: 124420
Subject: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 21 Sep 2007 07:09:13 -0000
Links: << >>  << T >>  << A >>
Hi

information from reliable source (but not verified by actual test-
purchases):

"Actel silicon with and without Cortex-M1 enable option cost exactly
the same, not a penny more"

I requested to verify and repeat that claim, and the source did stand
to it.

If this is really so - this can only be verified when buying Actel M1
silicon and non-M1 at same time from same vendor, then it means that
there really is no hidden fee any more in the ARM softcore.

let me remind that while Actel also claimed M7 to be "free" the actual
M7 enabled silicon cost 1 USD (qty 100k) or 100 USD (qty 1)  more then
silicon without M7 AES key.


Antti


Article: 124421
Subject: Re: how interfacing of cpld and cpu done?
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 21 Sep 2007 07:36:51 -0000
Links: << >>  << T >>  << A >>
On 21 Sep., 08:16, nanaware_a...@rediffmail.com wrote:
> please give me information about inerfacing of cpld xc9572 & cpu

http://code.google.com/p/nds-homebrew/wiki/Slot2_XC95_VQ44



Article: 124422
Subject: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
From: Manny <mloulah@hotmail.com>
Date: Fri, 21 Sep 2007 01:30:36 -0700
Links: << >>  << T >>  << A >>
> "Actel silicon with and without Cortex-M1 enable option cost exactly
> the same, not a penny more"

Great news. I'll give it a go with my Fusion kit once I have some
spare time to kill. Stay put for an update on this.

Regards,
Manny


Article: 124423
Subject: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 21 Sep 2007 08:36:45 -0000
Links: << >>  << T >>  << A >>
On 21 Sep., 10:30, Manny <mlou...@hotmail.com> wrote:
> > "Actel silicon with and without Cortex-M1 enable option cost exactly
> > the same, not a penny more"
>
> Great news. I'll give it a go with my Fusion kit once I have some
> spare time to kill. Stay put for an update on this.
>
> Regards,
> Manny

hm, as far as i understood the M1 enabled silicon is still sold as
separate M1 enable chip
so it is not possible to load non-M1 chips with cortex design :(

only that the M1-enable option doesnt cost any extra.

sure it would much nicer to just load the cortex design to any actel
chip, but will not be the case

Antti




Article: 124424
Subject: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
From: Manny <mloulah@hotmail.com>
Date: Fri, 21 Sep 2007 01:45:45 -0700
Links: << >>  << T >>  << A >>
> sure it would much nicer to just load the cortex design to any actel
> chip, but will not be the case

Damn it! I knew this was too good to be true.
Thanks for the clarification though Antti.

Manny




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