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Hi,
This is my first post to this group. I am an FPGA newbie trying to
learn this new and exciting stuff.
I have a set of 3 boards from an amateur radio project. Board #1 is a
back plane where board #2 and #3 plugs in.
Board #2 has a Cypress FX2 chip and a Altera Cyclone II FPGA. Board #3
has a Max-II based CPLD.
I would like to download Max-II configuration thru the FX2. For that I
am trying to use kawk's excellent usb-blaster emulation code:
http://www.ixo.de/info/usb_jtag/
I route the FX2 port B pins 0..3 which are emulating TDI, TDO, TCK and
TMS pins as shown in Variant-A in the above webpage. These pins go
into the FPGA (cyclone-II) on board #2. Inside the FPGA, these are
routed to some lines shared thru the backplane to the board #3, which
are routed to the CPLD JTAG pins.
To accomplish this, I load a simple code into the Cyclone II on board
#2, which simply 'assigns' the appriate input pins to the output (TDI,
TCK, TMS are taken as input from port B and output into relevant I/O
pins into board #3 thru the backplane, TDO is taken from board #3, and
simply assigned to the appropriate pin of port B). After loading this
FPGA configuration, I load the FX2 code built from the above webpage.
Windows recognize the FX2 at this point as USB-Blaster and I pointed
it to the right drivers. Quartus also recognize it as USB-Blaster. But
when it tries to scan for devices, it finds none! i.e. the routing of
JTAG pins thru the FPGA does not seem to be working fine.
Is there anything special I need to do inside the FPGA code? I am
pasting the FPGA routing code here.
// B0 - TDI
// B1 - TDO
// B2 - TCK
// B3 - TMS
// A23 - Atlas TMS - output
// A24 - Atlas TCK - output
// A27 - Atlas TDO - input
// A29 - Atlas TDI - output
module usb_blaster_emulation(
B0, B1, B2, B3,
A23, A24, A27, A29
);
input B0;
output B1;
input B2;
input B3;
output A23;
output A24;
input A27;
output A29;
assign A23 = B3;
assign A24 = B2;
assign B1 = A27;
assign A29 = B0;
endmodule
I haven't done too much of FPGA work. I would very much appreciate any
help in finding the mistake in the above setup. Thanks
Ramakrishnan
Article: 123126
Brad Smallridge wrote:
> if(up='1' and count_int/=max)then
> ...
> elsif( down='1'and count_int/=0) then
> ...
> got rid of the warnings
> and a considerable numbers of slices.
I saw a reduction from 28 to 27 ALUTs with /=
for limits of 1 and -1+2**16 using quartus.
No warnings and 17 registers in either case.
I might keep the original description
as clearer and very slightly safer.
Interesting example.
-- Mike Treseler
Article: 123127On Aug 16, 1:29 pm, "MikeJ" <mi...@fpgaarcade.nospam.com> wrote: > > Hi Mike, > > This could be a job for 'Directed routing constraints'. In FPGA editor > > click Tools -> Directed Routing Constraints . You can select nets in your > > design that are routed as you want and get the tool to spit out a load of > > gobbledegook that you can cut-n-paste into your UCF file. This ensures (in > > the Xilinx software sense of the word) that your routing is the same every > > time. > > HTH., Syms. > > Jim, thanks very much for trying it, I managed to get the same result. I > moved the locs on the DCM from 0,1 to 2,3 and removed a skew constraint on > this clock which seems to be confusing the tools. In 4vlx25, DCM_X0Y0,1,2 are in the bottom half and DCM_X0Y3,4,5,6,7 are in the top half. You can see this clearly from the "Component View" in ADEPT (http://home.comcast.net/~jimwu88/tools/adept/). So locking DCMs to 0,1 or 2,3 will certainly cause the tool to use local routing resources from your clock input, which is in the top half of the device. Cheers, JimArticle: 123128
Hi All, From reading UG071, part of the Virtex4 user guide, I see that I can reconfigure the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes on-the-fly using the DCM's dynamic reconfiguration port. Very nice. My question is this. Can I use this port to reconfigure the CLKDV_DIVIDE attribute on-the-fly, and if so, how? I couldn't find a reference to this in the document. For background, I have a >500MHz clock coming into the part which I divide by two using the DCM's CLKIN_DIVIDE_BY_2 feature. It would be nice and easy if I could use the DRP to change the divide ratio of the signal at CLKDV. It's no big deal if I can't as I could always do this programmable division in the fabric, but the DRP would make things neater. Cheers, Syms.Article: 123129
Ok, I'm signed up and I've used it. I have one suggestion but don't know where to post it. Maybe you could forward it? Please add a way to see all new postings, regardless of which subgroup they where in. Most likely anyone interested in this web forum would be interested in more than just one subsection, but they way it's implemented right now you have to manually visit each one to see new postings. In fact as web forums go, this one is fairly basic, maybe too basic. Regards TommyArticle: 123130
Jim, > > In 4vlx25, DCM_X0Y0,1,2 are in the bottom half and DCM_X0Y3,4,5,6,7 > are in the top half. You can see this clearly from the "Component > View" in ADEPT (http://home.comcast.net/~jimwu88/tools/adept/). So > locking DCMs to 0,1 or 2,3 will certainly cause the tool to use local > routing resources from your clock input, which is in the top half of > the device. quite right, sorry I was posting from memory at home. > 1.213ns - comp.pin "/snip/DCM_ADV_INST.CLKIN", site.pin > "DCM_ADV_X0Y5.CLKIN" > 1.222ns - comp.pin "/snip/DCM_ADV_INST.CLKIN", site.pin > "DCM_ADV_X0Y4.CLKIN" I moved the DCMs from 7,6 down to 5,4 so they were in the top half before - I moved them closer to the clock pin - but looking at the routing it goes up and then back down to the DCMs, I suspect to keep the delay length the same to them all. Clever. I did not notice before DCM 3 is in the top half, I would have expected it to be down below. Thanks for ADEPT, it is very useful. Interestingly I have just come back from supporting some Chinese customers, and they were also using ADEPT! We were using it to find and loc down the correct IDELAYCTRL blocks, something that is tricky in fpga_editor. Cheers, Mike.Article: 123131
Brad Smallridge wrote:
> I am using this code to adjust a value for a menu
> display and I have pushbuttons controlling its value.
> One pb for up and another for down.
Ahh. I see. How do you debounce?
> Having separate
> up and down inputs was the first thing that occurred to
> me, although that isn't usually how an up/down counter
> is ported, is it.
Well, two inputs is two inputs and
there aren't really any LS191's inside anyway :)
> The enable is controlled by the
> "cursor" position.
Sounds like fun.
-- Mike Treseler
Article: 123132On Aug 16, 10:50 am, Peter Alfke <pe...@xilinx.com> wrote: > I hate to sound like a broken record, but: > Huffman run-length encoding was invented exactly for such a problem, > and it has proven its effectiveness in fax machines the world over. I don't think it'd work very well for this problem. I'd be happy to discuss and provide code offline if you wish. -MArticle: 123133
"vu3rdd" <vu3rdd@gmail.com> wrote in message news:1187289432.172508.63740@i13g2000prf.googlegroups.com... > Hi, > > This is my first post to this group. I am an FPGA newbie trying to > learn this new and exciting stuff. > > I have a set of 3 boards from an amateur radio project. Board #1 is a > back plane where board #2 and #3 plugs in. > > Board #2 has a Cypress FX2 chip and a Altera Cyclone II FPGA. Board #3 > has a Max-II based CPLD. > > I would like to download Max-II configuration thru the FX2. For that I > am trying to use kawk's excellent usb-blaster emulation code: > http://www.ixo.de/info/usb_jtag/ > > I route the FX2 port B pins 0..3 which are emulating TDI, TDO, TCK and > TMS pins as shown in Variant-A in the above webpage. These pins go > into the FPGA (cyclone-II) on board #2. Inside the FPGA, these are > routed to some lines shared thru the backplane to the board #3, which > are routed to the CPLD JTAG pins. > > To accomplish this, I load a simple code into the Cyclone II on board > #2, which simply 'assigns' the appriate input pins to the output (TDI, > TCK, TMS are taken as input from port B and output into relevant I/O > pins into board #3 thru the backplane, TDO is taken from board #3, and > simply assigned to the appropriate pin of port B). After loading this > FPGA configuration, I load the FX2 code built from the above webpage. > > Windows recognize the FX2 at this point as USB-Blaster and I pointed > it to the right drivers. Quartus also recognize it as USB-Blaster. But > when it tries to scan for devices, it finds none! i.e. the routing of > JTAG pins thru the FPGA does not seem to be working fine. > > Is there anything special I need to do inside the FPGA code? I am > pasting the FPGA routing code here. > > // B0 - TDI > // B1 - TDO > // B2 - TCK > // B3 - TMS > // A23 - Atlas TMS - output > // A24 - Atlas TCK - output > // A27 - Atlas TDO - input > // A29 - Atlas TDI - output > > module usb_blaster_emulation( > B0, B1, B2, B3, > A23, A24, A27, A29 > ); > > input B0; > output B1; > input B2; > input B3; > > output A23; > output A24; > input A27; > output A29; > > assign A23 = B3; > assign A24 = B2; > assign B1 = A27; > assign A29 = B0; > > > endmodule > > > I haven't done too much of FPGA work. I would very much appreciate any > help in finding the mistake in the above setup. Thanks > > Ramakrishnan > Have you got your TDO and TDI connections right? TDO of one device normally drives TDI of another. I'm not saying it's wrong; but your comment against A27 above is confusing. Do you need pull-ups?Article: 123134
Peter Alfke wrote: > I hate to sound like a broken record, but: > Huffman run-length encoding was invented exactly for such a problem, > and it has proven its effectiveness in fax machines the world over. Isn't RLC implicit in the dT edge encoding ? If there is a common Freq, and wide dynamic range is needed, then another layer of compression is possible via lookup tables. Probably not needed here -jgArticle: 123135
Symon, I believe that DRP can only change the attributes for phase shift, M and D values of the DCM. Not CLKDV values. -David "Symon" <symon_brewer@hotmail.com> wrote in message news:fa26un$40q$1@aioe.org... > Hi All, > From reading UG071, part of the Virtex4 user guide, I see that I can > reconfigure the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes on-the-fly > using the DCM's dynamic reconfiguration port. Very nice. > > My question is this. Can I use this port to reconfigure the CLKDV_DIVIDE > attribute on-the-fly, and if so, how? I couldn't find a reference to this > in the document. > > For background, I have a >500MHz clock coming into the part which I divide > by two using the DCM's CLKIN_DIVIDE_BY_2 feature. It would be nice and > easy if I could use the DRP to change the divide ratio of the signal at > CLKDV. It's no big deal if I can't as I could always do this programmable > division in the fabric, but the DRP would make things neater. > > Cheers, Syms. >Article: 123136
Hi, kobelai15@gmail.com wrote: > what's wrong with following error???? > > [root@184pc140 bin]# ./mb-gcc hello.c > /home/devel/uclinux/bin/mb_tools/bin/../lib/gcc/microblaze/ > 3.4.1/../../../../microblaze/lib/libc.a(write.o): In function `write': > write.o(.text+0x34): undefined reference to `outbyte' > write.o(.text+0x58): undefined reference to `outbyte' > /home/devel/uclinux/bin/mb_tools/bin/../lib/gcc/microblaze/ > 3.4.1/../../../../microblaze/lib/libc.a(read.o): In function `read': > read.o(.text+0x2c): undefined reference to `inbyte' > collect2: ld returned 1 exit status inbyte and outbyte are provided by the Xilinx low level libxil.a library file. However, by invoking gcc from the command line with no extra options (like link path etc), the linker has been unable to find this. What are you trying to do? Build a C app for MicroBlaze in standalone mode, or for Linux? If you are building Linux apps, grab PetaLinux (developer.petalogix.com) which includes a standalone MicroBlaze Linux toolchain - you can just do microblaze-uclinux-gcc -o hello hello.c and it will magincally produce a Linux-ready binary. Regards, JohnArticle: 123137
I am currently using FIFO16 with xilinx Virtex-4. I found out in my design, the "almostempty" "almostfull" "empty" "full" flags are all stay high. That means some errors happen. The FIFO16s are configured as: width 36 depth 512 almostempty offset 12'd128 almostfull offset 12'd256 first word fall through (FWFT) Mode "True" read_clk 162Mhz write_clk 200Mhz Is there any issues here? It's been reseted before use, (reset assertion time is more than 3 clock cycles for both read and write clock). Anyone have similar experience or something wrong I doing. The clock speed should be OK based on performance table. Thanks, ChaoArticle: 123138
Eric Crabill wrote: > All three of these kits you mention have the slower -4 speedgrade component > on them and will run the MIG-generated DDR2 controller at 133 MHz, giving > you DDR2-266 performance. > > The recently announced support for DDR2-400 performance requires a faster -5 > speedgrade component, and this solution was tested on Spartan-3A Starter > Kits which had been built with the faster components. Does the Spartan-3A DDR2 SDRAM Interface Development Kit have the -5 speed grade FPGA?Article: 123139
> I saw a reduction from 28 to 27 ALUTs with /=
> for limits of 1 and -1+2**16 using quartus.
I am not sure what is going on Mike. I cleaned
up my code to post here below called count_test.
Count_test has quite a few LUTs because I guess
all the inputs are variables. Count_wrap wraps
Count_test and holds max and start to constant
values, a situation that I think would be the
most likely use. Here the less/greater than
packed better than not equal. Go figure.
I then ran my top level again to see if my
original results were wrong. They were not.
The not equal version ran better. I'm thinking
that the clutter in the design may effect how
well the counters versions are synthesized.
------------- FFlops 4inLUts Slices Warnings
count_test /= 16 65 41 15
count_wrap /= 16 32 17 0
count_wrap <> 16 30 16 0
top /= 415 479 451
top <> 414 535 493
There are three counters presently in top, more to
come.
Brad Smallridge
Ai Vision
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count_test is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
up : in std_logic;
down : in std_logic;
start : in std_logic_vector(15 downto 0);
max : in std_logic_vector(15 downto 0);
count : out std_logic_vector(15 downto 0) );
end count_test;
architecture beh of count_test is
signal count_int : std_logic_vector(15 downto 0);
begin
count_int_proc:process(clk)
begin
if(clk'event and clk='1')then
if(reset='1')then
count_int <= start;
elsif( enable='1') then
if( up='1' and count_int/=max )then
--if( up='1' and count_int<max )then
count_int<=count_int+1;
elsif( down='1' and count_int/=0 )then
--elsif( down='1' and count_int>0 )then
count_int<=count_int-1;
end if;
end if;
end if;
end process;
count_proc:process(count_int)
begin
count <= count_int;
end process;
end beh;
---------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity count_wrap is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
up : in std_logic;
down : in std_logic;
count : out std_logic_vector(15 downto 0) );
end count_wrap;
architecture beh of count_wrap is
component count_test
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
up : in std_logic;
down : in std_logic;
start : in std_logic_vector(15 downto 0);
max : in std_logic_vector(15 downto 0);
count : out std_logic_vector(15 downto 0) );
end component;
begin
count_test_1: count_test
port map(
clk => clk,
reset => reset,
enable => enable,
up => up,
down => down,
start => "0000000000000001",
max => "1000000000000101",
count => count );
end beh;
Article: 123140
> Ahh. I see. How do you debounce?
The ML402 has some RC debounce but it wasn't
to good. Lots of skips. I corrected it just
yesterday with this code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debounce is
port(
clk : in std_logic; -- 100MHz
reset : in std_logic;
button_in : in std_logic_vector(4 downto 0);
button_out : out std_logic_vector(4 downto 0));
end debounce;
architecture beh of debounce is
signal button_1 : std_logic_vector(4 downto 0);
signal button_2 : std_logic_vector(4 downto 0);
signal stable_count : std_logic_vector(20 downto 0);
begin
debounce_proc:process(clk)
begin
if(clk'event and clk='1')then
button_1 <= button_in;
button_2 <= button_1;
if(reset='1')then
stable_count<=(others=>'0');
elsif( button_1=button_2)then
if( stable_count(20)='1')then
button_out<=button_2;
else
stable_count<=stable_count+1;
end if;
else
stable_count<=(others=>'0');
end if;
end if;
end process;
end beh;
Brad Smallridge
Ai Vision
Article: 123141
Brad Smallridge wrote:
> I am not sure what is going on Mike. I cleaned
> up my code to post here below called count_test.
...
> max => "1000000000000101",
The difference is your max limit value.
My version is below.
-- Mike Treseler
_________________________________________
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity updown is
generic (vec_len : natural := 16);
port (clk : in std_ulogic;
reset, enable, up, down : in std_ulogic;
out_of_range : out std_ulogic;
count : out std_logic_vector(vec_len-1 downto 0));
end updown;
architecture synth of updown is
begin
main : process(clk, reset)
constant up_limit : natural := 2**vec_len-1;
constant dn_limit : natural := 2**0;
variable cnt_v : unsigned(vec_len-1 downto 0);
variable out_of_range_v : std_ulogic;
begin
template : if reset = '1' then
init_cnt : cnt_v := (others => '0');
out_of_range_v := '0';
elsif rising_edge(clk) then
if enable = '1' then
out_of_range_v := '0';
if up = '1' and cnt_v < up_limit then
-- if up = '1' and cnt_v /= up_limit then -- saves one alut
cnt_v := cnt_v + 1;
elsif down = '1' and cnt_v > dn_limit then
-- elsif down = '1' and cnt_v /= dn_limit then -- saves one
cnt_v := cnt_v - 1;
else
out_of_range_v := '1';
end if;
end if;
end if template;
count <= std_logic_vector(cnt_v);
out_of_range <= out_of_range_v;
end process main;
end synth;
__________________________________________________
-- Using <
--Fitter Status : Successful - Wed Aug 15 11:39:30 2007
--Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
--Revision Name : updown
--Top-level Entity Name : updown
--Family : Stratix II GX
--Device : EP2SGX30DF780C3
--Timing Models : Preliminary
--Logic utilization : < 1 %
-- Combinational ALUTs : 28 / 27,104 ( < 1 % )
-- Dedicated logic registers : 17 / 27,104 ( < 1 % )
Article: 123142Hi Eric, No, it does not -- it has a -4 speed grade FPGA like the other two similar kits. Eric "Eric Smith" <eric@brouhaha.com> wrote in message news:m3wsvvgfji.fsf@donnybrook.brouhaha.com... > Eric Crabill wrote: >> All three of these kits you mention have the slower -4 speedgrade >> component >> on them and will run the MIG-generated DDR2 controller at 133 MHz, giving >> you DDR2-266 performance. >> >> The recently announced support for DDR2-400 performance requires a >> faster -5 >> speedgrade component, and this solution was tested on Spartan-3A Starter >> Kits which had been built with the faster components. > > Does the Spartan-3A DDR2 SDRAM Interface Development Kit have the -5 speed > grade FPGA?Article: 123143
In the Xilinx EDK tool flow it is possible to synthesize a design and automatically program it into your FPGA using iMPACT. Therefore, a standard iMPACT command file is generated, which typically looks like: setMode -bscan setCable -p auto identify assignfile -p 3 -file implementation/download.bit program -p 3 quit This works fine as long as the programming cable is connected to the local system. In case the cable can not be found by iMPACT, its user interface is opened and an error is displayed. However, in our situation we are doing the synthesis and par flow on a dedicated remote server. The FPGA is connected to my desktop pc with a Xilinx USB platform cable. Furthermore, I am running the Xilinx CableServer such that a remote pc can use my desktop system for programming the FPGA. Obviously, I would like to change the generated iMPACT command file (as shown above) such that the tool is told to use my desktop pc as a remote host. This is possible when the iMPACT gui is executed (via menu Output -> Cable Setup -> Cable Location: Remote, hostname), but iMPACT does not show any command in the Output window (as it does when you change basically any other option). iMPACT's reference manuals do not mention such a command; however, they do mention the possibility to program via a remote host which is running the CableServer. Does such a command exist?Article: 123144
On Aug 17, 2:28 am, Chao <ss...@yahoo.com> wrote: > I am currently using FIFO16 with xilinx Virtex-4. I found out in my > design, the "almostempty" "almostfull" "empty" "full" flags are all stay > high. That means some errors happen. The FIFO16s are configured as: > > width 36 > depth 512 > almostempty offset 12'd128 > almostfull offset 12'd256 > first word fall through (FWFT) Mode "True" > read_clk 162Mhz > write_clk 200Mhz > > Is there any issues here? It's been reseted before use, (reset assertion > time is more than 3 clock cycles for both read and write clock). > > Anyone have similar experience or something wrong I doing. The clock > speed should be OK based on performance table. Have you read this : http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=22462 SylvainArticle: 123145
On Aug 17, 1:06 am, "Andrew Holme" <and...@nospam.com> wrote: > "vu3rdd" <vu3...@gmail.com> wrote in message > > news:1187289432.172508.63740@i13g2000prf.googlegroups.com... > > > > > Hi, > > > This is my first post to this group. I am an FPGA newbie trying to > > learn this new and exciting stuff. > > > I have a set of 3 boards from an amateur radio project. Board #1 is a > > back plane where board #2 and #3 plugs in. > > > Board #2 has a Cypress FX2 chip and a Altera Cyclone II FPGA. Board #3 > > has a Max-II based CPLD. > > > I would like to download Max-II configuration thru the FX2. For that I > > am trying to use kawk's excellent usb-blaster emulation code: > >http://www.ixo.de/info/usb_jtag/ > > > I route the FX2 port B pins 0..3 which are emulating TDI, TDO, TCK and > > TMS pins as shown in Variant-A in the above webpage. These pins go > > into the FPGA (cyclone-II) on board #2. Inside the FPGA, these are > > routed to some lines shared thru the backplane to the board #3, which > > are routed to the CPLD JTAG pins. > > > To accomplish this, I load a simple code into the Cyclone II on board > > #2, which simply 'assigns' the appriate input pins to the output (TDI, > > TCK, TMS are taken as input from port B and output into relevant I/O > > pins into board #3 thru the backplane, TDO is taken from board #3, and > > simply assigned to the appropriate pin of port B). After loading this > > FPGA configuration, I load the FX2 code built from the above webpage. > > > Windows recognize the FX2 at this point as USB-Blaster and I pointed > > it to the right drivers. Quartus also recognize it as USB-Blaster. But > > when it tries to scan for devices, it finds none! i.e. the routing of > > JTAG pins thru the FPGA does not seem to be working fine. > > > Is there anything special I need to do inside the FPGA code? I am > > pasting the FPGA routing code here. > > > // B0 - TDI > > // B1 - TDO > > // B2 - TCK > > // B3 - TMS > > // A23 - Atlas TMS - output > > // A24 - Atlas TCK - output > > // A27 - Atlas TDO - input > > // A29 - Atlas TDI - output > > > module usb_blaster_emulation( > > B0, B1, B2, B3, > > A23, A24, A27, A29 > > ); > > > input B0; > > output B1; > > input B2; > > input B3; > > > output A23; > > output A24; > > input A27; > > output A29; > > > assign A23 = B3; > > assign A24 = B2; > > assign B1 = A27; > > assign A29 = B0; > > > endmodule > > > I haven't done too much of FPGA work. I would very much appreciate any > > help in finding the mistake in the above setup. Thanks > > > Ramakrishnan > > Have you got your TDO and TDI connections right? TDO of one device normally > drives TDI of another. I'm not saying it's wrong; but your comment against > A27 above is confusing. I am actually not chaining devices. I am using FPGA on one board to route the JTAG emulation pins into the JTAG pins of an FPGA sitting on another board. > Do you need pull-ups? Yes, I have the pull ups in place. Thanks RamakrishnanArticle: 123146
Thanks for all the advice. My link will be running at 3.25Gbps. I think that I am going to use one of the santec board to board 50 ohmn connectors. JonArticle: 123147
hey, in FPGA-Editor i can choose a slice and type in an equation for this block. i need information, where i can find this equation (truth table) in the generated bitstream and how they are arranged. thanks for helpArticle: 123148
Hi all, We are trying to programme a FLASH memory linked to a APA1000. However, we have a data-blaster that should programme the FLASH quickly, providing we can drive the write signal from teh APA to a high imedance state via the JTAG port. It seems we're having trouble doing this. Is it possible to force/ drive a particular pin to 'Z' via JTAG? The data-blaster write is driven through a buffer which is enabled only when the appropriate APA pin is driven to a '1' rather than '0', but the buffer o/p conflicts with the APA write signal unless we can tri-state that. TIA, Niv.Article: 123149
On 17 Aug., 13:42, Niv <kev.pars...@mbda.co.uk> wrote: > Hi all, > We are trying to programme a FLASH memory linked to a APA1000. > However, we have a data-blaster that should programme the FLASH > quickly, providing we can drive the write signal from teh APA to a > high imedance state via the JTAG port. > > It seems we're having trouble doing this. Is it possible to force/ > drive a particular pin to 'Z' via JTAG? > > The data-blaster write is driven through a buffer which is enabled > only when the appropriate APA pin is driven to a '1' rather than '0', > but the buffer o/p conflicts with the APA write signal unless we can > tri-state that. > > TIA, Niv. always check the BSDL Files !!! "HIGHZ (00000111), "& Antti Lukats prelim docu about actel undoc http://docs.google.com/Doc?docid=ddn2thkw_36f29b7c
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