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"Mike Treseler" <mike_treseler@comcast.net> skrev i en meddelelse news:CMqdnQkoMae0GezcRVn-uA@comcast.com... > Adam Megacz wrote: > > What was the first FPGA? > > Maybe the xc2064 in 1986. > > -- Mike Tresler > ________________________________________________________________ > From: 13-MAR-1986 14:39:46.57 > To: @sys$mail:engineer > CC: Subj: SOFT GATE ARRAY > > > For anyone interested in the XILINX XC-2064 LOGIC CELL ARRAY read > on. > > This is a 1000-1500 gate Gate Array that is configured by > downloading a bit stream to it from rom at power up time. The > configuration 'links' are maintained in CMOS static ram cells in > the IC. > I have a spare copy of the data sheet plus some other information > obtained at the XILINX - HAMILTON/AVNET Seminar. > > Some general information : > . 12000 bits are required for configuration > using a 1Mhz clock requires 12 milliseconds to load. > . There are 122 flop flops per IC distributed in 58 I/O blocks and > 64 combinational blocks. > . Package size is 68 pin PLCC, 48 pin (40 i/o pins) DIP package > available soon. > . Development software runs on IBM PC XT/AT or compatible, with > hard disk. > . Full speed in circuit emulator is available. > (you can set a hardware breakpoint with this device) > > PRICING AND AVAILABILITY. > Development software: > Evaluation Kit $ 250.00 > XACT Development system software, including Macro library $3,600.00 > SILOS Timing/simulation package $3,500.00 > XACTOR in circuit emulator with one pod $3,000.00 > (can accomodate 4 pods for simulation of 4 devices at once) > XACTOR pods $ 850.00 > XACT training/demo package $ 350.00 > > Piece parts : > Speed package 1-24 25-99 100-999 5K+ (end '86) > -1 68 lead plcc $60 $53 $47 $20 > -2 68 lead plcc $80 $72 $63 $28 > > -1 (20Mhz) available now, -2 (33Mhz) available end 2nd quarter. > 48 pin package "soon" Hello I would like some more info about the XC2064 FPGA. Could you email the info to me? How do you program it? What is the pinout of the XC2064? How do you connect the ROM to the XC2064? etc. etc. I have got an old FPGA board with the XC2064 but I have no information at all. It would be nice if I could use the board for something. Thanks RuneArticle: 75551
Nicolas Matringe <matringe.nicolas@numeri-cable.fr> wrote in message news:<4190788F.4010306@numeri-cable.fr>... > Tom Hawkins a écrit: > > Hello, > > > > InFormal can prove the correctness of Verilog designs without using simulation > > I'm sure VHDL users will be very happy to know this... Sounds like you're volunteering! The InFormal netlist representation is very straight forward. Simply write some code for GHDL to generate an InFormal netlist; then you're all set: formal verification with VHDL. -TomArticle: 75552
250MWords/s that's often enough (you need to do a little math here to make sure it works), as Martin said, you dont have to refresh SDRAM during writing (assume you use write with auto precharge). But the problem araise when you stop the burst, what you going to do with the SDRAM? Pause & wait for user command? or read it out immediately... at what speed?Article: 75553
Manish, It is better to use the DDR FF in the IOB to do clock forwarding with the least duty cycle distortion. One IOB gets the DDR FF with the D tied to Vcc for the top FF,and the D tied to GND on the bottom FF, and the other (complement) IOB has the top D tied to GND, and the bottom D tied to Vcc. Austin Manish wrote: > Hi.. > Is it recommended to use following scheme, to generate "Differential > SSTL_2" clock signals which are sourcing DDR SDRAM & another > controller. > 1. Normal 125 MHz LVTTL clock source(Oscillator) feeding clock to > FPGA. > 2. FPGA functionality inverts this clock. > 3. The same i/p clock & inverted clock are sent out of FPGA, with > setting I/O standard of these to outputs as "OBUF_SSTL2_I". > > If this scheme is ok, will there be any constrain on using particular > family of FPGA like Spartan 2, Spartan 3 or virtex etc. > > Cheers, > ManishArticle: 75554
Two rows are not ACTive at one time in standard SDRAM in a single Bank & Rank. To access a new row, the first must go through a PREcharge before the other can be ACTivated to perform a read or write. "ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0411090018.74e797d4@posting.google.com... > Hi @ all, > > I am trying to implement a SDR/DDR SDRAM controller. > > My question: > > Is it possible to access (write or read) two different rows > in one bank at the same time ? > I could not find that situation described in any of those > papers I read (for example Micron, Infineon). > > Thank you for your help. > > > Rgds > > AndreArticle: 75555
Hi all,
I'm designing a C compiler for the PicoBlaze processor.
The compiler is a subset of the C language, but is quite good.
I called the C compiler PicoC :-)
I'm an FPGA designer and I want to use this compiler for my job.
I think is very interesting to have a small microprocessor in an FPGA that
you can program in C!
Are you using PicoBlaze at moment?
do you think you can help me to test the Compiler?
The compiler at moment gives working code, but I need someone to do some
good testing.
I do not promise that I'll give the compiler to eveybody, but I'll give
the compiler to 5 or 10 people in all.
Also,the compiler is in pre Alpha version.
That means that has not all the functionality.
When the compiler will be finished I'll do some optimization on the generated code.
At moment I can write code like this:
EXAMPLE:
int i;
int *ii;
char s;
char *ss;
void main()
{
i =0;
for(i=0;i<0x123;i++){
s=1;
*ss=s;
do {s++;
*ss +=s;
}
while (*ss<100);
if(s)
i = 10;
else
i = 100;
}
ii = 1;
*ii = 1;
}
and when I lunch the PicoC compiler this is the result:
CONSTANT _i_low , ff
CONSTANT _i_high , fe
CONSTANT _ii , fd
CONSTANT _s , fc
CONSTANT _ss , fb
LOAD S3 , fb
;int i;
;int *ii;
;char s;
;char *ss;
;void main()
_main:
;{
; i =0;
LOAD S5,00
LOAD S4,00
OUTPUT S5 , _i_low
OUTPUT S4 , _i_high
; for(i=0;i<0x123;i++){
LOAD S5,00
LOAD S4,00
OUTPUT S5 , _i_low
OUTPUT S4 , _i_high
L2:
INPUT S1 , _i_low
INPUT S0 , _i_high
SUB S3 , 01
OUTPUT S0 , (S3)
SUB S3 , 01
OUTPUT S1 , (S3)
LOAD S5,23
LOAD S4,01
INPUT S1, (S3)
ADD S3 , 01
INPUT S0, (S3)
ADD S3 , 01
SUB S1 , S5
SUBCY S0, S4
JUMP C , L3
JUMP L5
JUMP L4
L3:
INPUT S5 , _i_low
INPUT S4 , _i_high
ADD S5 , 01
ADDCY S5 , 00
OUTPUT S5, _i_low
OUTPUT S4, _i_high
SUB S5 , 01
SUBCY S5 , 00
JUMP L2
L4:
; s=1;
LOAD S5,01
OUTPUT S5 , _s
; *ss=s;
INPUT S1 , _ss
INPUT S5 , _s
OUTPUT S5, (S1)
; do {s++;
L6:
INPUT S5 , _s
ADD S5 , 01
OUTPUT S5, _s
SUB S5 , 01
; *ss +=s;
INPUT S1 , _ss
INPUT S5, (S1)
SUB S3 , 01
OUTPUT S5 , (S3)
INPUT S5 , _s
INPUT S1, (S3)
ADD S3 , 01
ADD S1 , S5
; }
; while (*ss<100);
L7:
INPUT S5 , _ss
INPUT S5, (S5)
SUB S3 , 01
OUTPUT S5 , (S3)
LOAD S5,64
INPUT S1, (S3)
ADD S3 , 01
SUB S1 , S5
JUMP C , L9
JUMP L8
L9:
JUMP L6
L8:
; if(s)
INPUT S5 , _s
LOAD S4 , 00
OR S5 , S4
JUMP NZ , L10
JUMP L10
L11:
; i = 10;
LOAD S5,0a
LOAD S4,00
OUTPUT S5 , _i_low
OUTPUT S4 , _i_high
; else
JUMP L12
L10:
; i = 100;
LOAD S5,64
LOAD S4,00
OUTPUT S5 , _i_low
OUTPUT S4 , _i_high
L12:
; }
JUMP L3
L5:
; ii = 1;
LOAD S5,01
LOAD S4,00
OUTPUT S5 , _ii
; *ii = 1;
INPUT S1 , _ii
LOAD S5,01
LOAD S4,00
OUTPUT S5, (S1)
SUB S1 , 01
OUTPUT S4 , (S1)
;}
I hope someone of you is interested
Regards,
Francesco
Article: 75556Hello, Im trying to find a nice and simple FPGA board without having LEDs and digital displays and other stuff I dont need. Im just looking for a board with just the essentials for an fpga to run and just some pinouts. I know some of the prototyping boards have some things like this, but they're generaly lower end FPGAs. Im looking for atleast a virtex-II. Anyone know of any good companys that provide something like this without all the bells and whistles? Thanks -MarkArticle: 75557
Francesco Poderico wrote: > Hi all, > I'm designing a C compiler for the PicoBlaze processor. > The compiler is a subset of the C language, but is quite good. > > I called the C compiler PicoC :-) > > I'm an FPGA designer and I want to use this compiler for my job. > I think is very interesting to have a small microprocessor in an FPGA that > you can program in C! You might want to check out SDCC on sourceforge. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 75558
>Im trying to find a nice and simple FPGA board without having LEDs and >digital displays and other stuff I dont need. Im just looking for a >board with just the essentials for an fpga to run and just some >pinouts. I know some of the prototyping boards have some things like >this, but they're generaly lower end FPGAs. Im looking for atleast a >virtex-II. Anyone know of any good companys that provide something >like this without all the bells and whistles? What do you want? What sort of ballpark price are you interested in? LEDs and such aren't very expensive. You will probably do better if you ignore them on some board that otherwise looks good. The Spartan3 starter kit is $100. That includes programming cable and wall wart. It's got a couple of 40 pin connectors, but they don't have enough ground pins for high end work. The FAQ has a page listing lots of board. Google can find it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75559
Bless, you even posted from Google Groups! So why not go back to the GG search page, and search for 'simple fpga board' in CAF. It's quicker than typing a post! ;-) Best, Syms. "weizbox" <mwiesbock@gmail.com> wrote in message news:335c6753.0411090856.2f466dc6@posting.google.com... > Hello, > > Im trying to find a nice and simple FPGA board without having LEDs and > digital displays and other stuff I dont need. Im just looking for a > board with just the essentials for an fpga to run and just some > pinouts. I know some of the prototyping boards have some things like > this, but they're generaly lower end FPGAs. Im looking for atleast a > virtex-II. Anyone know of any good companys that provide something > like this without all the bells and whistles? > > Thanks > -MarkArticle: 75560
"weizbox" <mwiesbock@gmail.com> wrote in message news:335c6753.0411090856.2f466dc6@posting.google.com... > Hello, > > Im trying to find a nice and simple FPGA board without having LEDs and > digital displays and other stuff I dont need. Im just looking for a > board with just the essentials for an fpga to run and just some > pinouts. I know some of the prototyping boards have some things like > this, but they're generaly lower end FPGAs. Im looking for atleast a > virtex-II. Anyone know of any good companys that provide something > like this without all the bells and whistles? > > Thanks > -Mark you cant go lower than than on pricing! unfortunatly the proto on the picture has been sold. I still have one overleft XCV2000E same package as on the picture http://xilinx.openchip.org/proto/ if you want something more do your homework, but expect the board with no LEDs to cost way more than one with LED's!! http://www.orangetreetech.com/zest100.htm Antti My first SoC in 1 Day? http://ebook.openchip.org/soc1day/Article: 75561
Hello.
I am trying to do a partial reconfiburation design on our virtex2
pro board. But now instead of a suggested topview and several modules
hierarchy as the xpp290, my current design has a 3 layer hierarchy: a
topview, with several modules, then for each module, it may contains
one or more submodules. And where I want to carry out the partial
reconfiguration is on the bottom submodules.
So my question is whether i can do the partial reconfiguration
with such hierachy? or I have to stick to the suggested modular design
strategy. If can, then how to treat the middle layer modules when run
the ngdbuild? do I use the parameter of -modular initial or the
-modular module -active.
thank you.
Article: 75562tripledirrble <anttonhu@gmail.com> wrote in message news:<ee89f0f.1@webx.sUN8CHnE>... > Yes, the old Virtex E configuration have only one PROM. what do you mean by "and twisting a ground with each signal helped"? Is that true to have a ground trace in parrallel with each signal? I believe that magnetic coupling is a function of the loop area between the signal and a AC ground. If you have a wire hanging out in free space, it is my belief that it generates a lot of garbage and is susceptible to such. I believe the theory behind the twist is that it will reduce the loop area to a given magnetic field orientation. I believe E-field interference is reduced by a shield. Do not take my explanation of this too seriously. NewmanArticle: 75563
Has anyone had experience using the chipscope VIO core? Does it work well? Is it viable to replace unfinished blocks with chipscope VIO core? Thanks, p.s. on a side note, when using synchronous vio inputs i get the signals coming in to be interpreted as clocks from xilinx ise, is this normal???Article: 75564
Francesco Poderico wrote: > Hi all, > I'm designing a C compiler for the PicoBlaze processor. > The compiler is a subset of the C language, but is quite good. Did you check out the LCC ? http://www.cs.princeton.edu/software/lcc/Article: 75565
"Rune Christensen" <rune.christensen@adslhome.dk> wrote in message news:<4190ce09$0$256$edfadb0f@dread12.news.tele.dk>... > "Mike Treseler" <mike_treseler@comcast.net> skrev i en meddelelse > news:CMqdnQkoMae0GezcRVn-uA@comcast.com... > > Adam Megacz wrote: > > > What was the first FPGA? > > > > Maybe the xc2064 in 1986. > > > > -- Mike Tresler > > ________________________________________________________________ > > From: 13-MAR-1986 14:39:46.57 > > To: @sys$mail:engineer > > CC: Subj: SOFT GATE ARRAY > > > > > > For anyone interested in the XILINX XC-2064 LOGIC CELL ARRAY read > > on. > > > > This is a 1000-1500 gate Gate Array that is configured by > > downloading a bit stream to it from rom at power up time. The > > configuration 'links' are maintained in CMOS static ram cells in > > the IC. > > I have a spare copy of the data sheet plus some other information > > obtained at the XILINX - HAMILTON/AVNET Seminar. > > > > Some general information : > > . 12000 bits are required for configuration > > using a 1Mhz clock requires 12 milliseconds to load. > > . There are 122 flop flops per IC distributed in 58 I/O blocks and > > 64 combinational blocks. > > . Package size is 68 pin PLCC, 48 pin (40 i/o pins) DIP package > > available soon. > > . Development software runs on IBM PC XT/AT or compatible, with > > hard disk. > > . Full speed in circuit emulator is available. > > (you can set a hardware breakpoint with this device) > > > > PRICING AND AVAILABILITY. > > Development software: > > Evaluation Kit $ 250.00 > > XACT Development system software, including Macro library $3,600.00 > > SILOS Timing/simulation package $3,500.00 > > XACTOR in circuit emulator with one pod $3,000.00 > > (can accomodate 4 pods for simulation of 4 devices at once) > > XACTOR pods $ 850.00 > > XACT training/demo package $ 350.00 > > > > Piece parts : > > Speed package 1-24 25-99 100-999 5K+ (end '86) > > -1 68 lead plcc $60 $53 $47 $20 > > -2 68 lead plcc $80 $72 $63 $28 > > > > -1 (20Mhz) available now, -2 (33Mhz) available end 2nd quarter. > > 48 pin package "soon" > > Hello > > I would like some more info about the XC2064 FPGA. > > Could you email the info to me? > > How do you program it? > What is the pinout of the XC2064? > How do you connect the ROM to the XC2064? > etc. > etc. > > I have got an old FPGA board with the XC2064 but I have no information at > all. It would be nice if I could use the board for something. > > Thanks > Rune Somebody has a few of these up for auction on eBay: http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&category=50913&item=3851303288 DerekArticle: 75566
Hi group,
When I am developing code for a hobby project, I find that ModelSim XE
II/Starter 5.7c (came with Xilinx Webpack 6.1.03i infered unnecessary latch
in place of logic. It is a before-synthesis simulation, not a post-fit
simulation.
Here is the sample code (complete and compiles) and the simulated result
is posted at <http://www.geocities.com/mscpscsi/PHOTOS/simulation.jpg>.
In the program I combined signals (EAL0 and EAL2) to make the code clean.
It might be that I made some mistake that I did't know of. I examined the
program over and over and still could not find where the problem is. Any
idea? Thanks.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TEST is
Port (
RESULT: out std_logic_vector(1 downto 0);
TEMP: INOUT std_logic_vector(1 downto 0);
EAL0: in std_logic;
EAL2: in std_logic
);
end TEST;
architecture Behavioral of TEST is
begin
TEMP <= EAL0 & EAL2;
TEST_PROCESS:process (EAL0, EAL2)
begin
if TEMP = "00" then RESULT <= "01";
elsif TEMP = "01" then RESULT <= "10";
elsif TEMP = "10" then RESULT <= "00";
else RESULT <= "XX";
end if;
end process;
end Behavioral;
--vax, 9000
Article: 75567One grid on the simulated waveform represents 10ns. --vax, 9000Article: 75568
Fix your sensitivity list. It should be: TEST_PROCESS:process (temp) Regards, Jim > Hi group, > When I am developing code for a hobby project, I find that ModelSim XE > II/Starter 5.7c (came with Xilinx Webpack 6.1.03i infered unnecessary latch > in place of logic. It is a before-synthesis simulation, not a post-fit > simulation. > Here is the sample code (complete and compiles) and the simulated result > is posted at <http://www.geocities.com/mscpscsi/PHOTOS/simulation.jpg>. > In the program I combined signals (EAL0 and EAL2) to make the code clean. > It might be that I made some mistake that I did't know of. I examined the > program over and over and still could not find where the problem is. Any > idea? Thanks. > > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity TEST is > Port ( > RESULT: out std_logic_vector(1 downto 0); > TEMP: INOUT std_logic_vector(1 downto 0); > EAL0: in std_logic; > EAL2: in std_logic > ); > end TEST; > > architecture Behavioral of TEST is > > begin > > TEMP <= EAL0 & EAL2; > > TEST_PROCESS:process (EAL0, EAL2) > begin > if TEMP = "00" then RESULT <= "01"; > elsif TEMP = "01" then RESULT <= "10"; > elsif TEMP = "10" then RESULT <= "00"; > else RESULT <= "XX"; > end if; > end process; > > end Behavioral; > > --vax, 9000 -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 75569
Jim Lewis wrote: > Fix your sensitivity list. It should be: TEST_PROCESS:process (temp) That's where the problem was. After changing the sensitivity list, the problem is gone. Thank you very much. --vax, 9000 > > Regards, > Jim >> Hi group, >> When I am developing code for a hobby project, I find that ModelSim XE >> II/Starter 5.7c (came with Xilinx Webpack 6.1.03i infered unnecessary >> latch in place of logic. It is a before-synthesis simulation, not a >> post-fit simulation. >> Here is the sample code (complete and compiles) and the simulated >> result >> is posted at <http://www.geocities.com/mscpscsi/PHOTOS/simulation.jpg>. >> In the program I combined signals (EAL0 and EAL2) to make the code >> clean. >> It might be that I made some mistake that I did't know of. I examined the >> program over and over and still could not find where the problem is. Any >> idea? Thanks. >> >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use IEEE.STD_LOGIC_ARITH.ALL; >> use IEEE.STD_LOGIC_UNSIGNED.ALL; >> >> entity TEST is >> Port ( >> RESULT: out std_logic_vector(1 downto 0); >> TEMP: INOUT std_logic_vector(1 downto 0); >> EAL0: in std_logic; >> EAL2: in std_logic >> ); >> end TEST; >> >> architecture Behavioral of TEST is >> >> begin >> >> TEMP <= EAL0 & EAL2; >> >> TEST_PROCESS:process (EAL0, EAL2) >> begin >> if TEMP = "00" then RESULT <= "01"; >> elsif TEMP = "01" then RESULT <= "10"; >> elsif TEMP = "10" then RESULT <= "00"; >> else RESULT <= "XX"; >> end if; >> end process; >> >> end Behavioral; >> >> --vax, 9000 > >Article: 75570
"vax, 9000" <vax9000@gmail.com> wrote in message news:<cmrjkn$ivq$1@charm.magnus.acs.ohio-state.edu>... > Hi group, > When I am developing code for a hobby project, I find that ModelSim XE > II/Starter 5.7c (came with Xilinx Webpack 6.1.03i infered unnecessary latch > in place of logic. It is a before-synthesis simulation, not a post-fit > simulation. > Here is the sample code (complete and compiles) and the simulated result > is posted at <http://www.geocities.com/mscpscsi/PHOTOS/simulation.jpg>. > In the program I combined signals (EAL0 and EAL2) to make the code clean. > It might be that I made some mistake that I did't know of. I examined the > program over and over and still could not find where the problem is. Any > idea? Thanks. > > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity TEST is > Port ( > RESULT: out std_logic_vector(1 downto 0); > TEMP: INOUT std_logic_vector(1 downto 0); > EAL0: in std_logic; > EAL2: in std_logic > ); > end TEST; > > architecture Behavioral of TEST is > > begin > > TEMP <= EAL0 & EAL2; > > TEST_PROCESS:process (EAL0, EAL2) > begin > if TEMP = "00" then RESULT <= "01"; > elsif TEMP = "01" then RESULT <= "10"; > elsif TEMP = "10" then RESULT <= "00"; > else RESULT <= "XX"; > end if; > end process; > > end Behavioral; > > --vax, 9000 In general, the process sensitivity list normally has signals from the right side of an assignment statement, or signals that would alter the flow of statements. I think you need to remove EAL0 and EAL2 from the sensitivity list and put in signal temp. For an event based simulator (Modelsim), when EAL0 or EAL2 change, because this is a functional simulation, (e.g. no component or routing delays, the value of temp is scheduled to change some small delta time in the future. When the simulator hits the process statement, the change in EAL0 or EAL2 triggers the process, but temp has not changed yet because it is not scheduled to change until a little bit in the future. When temp does change, since it is not in the sensitivity list, the process does not get triggered. Synthesizers that I have used modify the sensitivity list accordingly, and issue a warning to the user. This would cause the functional simulation to mismatch against the gate level one. I use emacs because it has a great VHDL package that automatically updates the sensitivity list for you. Hope this helps, NewmanArticle: 75571
<John> wrote in message news:ee89f65.11@webx.sUN8CHnE... > Has anyone had experience using the chipscope VIO core? Does it work well? Is it viable to replace unfinished blocks with chipscope VIO core? hm, the async in and out works well at least! and as I am able to write my own VIO style cores that can be plugged into ICON thats sufficent for me:) > Thanks, > > p.s. on a side note, when using synchronous vio inputs i get the signals coming in to be interpreted as clocks from xilinx ise, is this normal??? I guess it is, hm that means if many clocks used you might need some manual glock buffer assignment to make sure all signal that need global clock buffers defenetly get them AnttiArticle: 75572
Hello Chris, In Nios II version 1.01 there is an example called Simple Socket Server which includes the sockets.h header file. If you are still using Nios II version 1.0, and have not upgraded yet to Nios II version 1.01 (which is available on the Nios Forum at www.niosforum.com), there is a networking example named ntp_client which also includes sockets.h (in ntp_client.c) The Simple Socket Server example, included with the Nios II 1.01 distribution, includes the socket.h header file. The source file which includes socket.h is simple_socket_server.c, and uses the following syntax for the include: #include "lwip/sockets.h" You should be able to use the same syntax in your project. If this does not work for your project, make sure that you are creating your project under the nios2 installation directory. Try using the Nios II IDE new project creation default directory location for your new application project, which is: <Nios_II_Install_Dir (i.e. C:\altera\kits\nios2)>\verilog \niosII_cyclone_1c20\standard\software\ where "verilog" could be "vhdl", "niosII_cyclone_1c20" refers to your Nios development board flavor (Cyclone, Stratix, etc.), and "standard" refers to the particular reference design (standard, full_featured, etc.) or other Quartus project containing a Nios II cpu. Use the Nios II IDE to create your project based on the Simple Socket Server template via File->New Project. You can then drop in all of your source code into the new projects's source code directory (path listed above), right click on the project name in Nios II IDE and select "refresh", and all of your sources will be pulled into the Nios II IDE generated make system. This will insure that all of the application project properties and system project properties defined by the Simple Socket Server template are used, and consequently will allow inclusion of "lwip/sockets.h" to find the header file. Best regards, Stephen sichstre@netscape.net (sichstre) wrote in message news:<9647c109.0411040149.6703d91a@posting.google.com>... > Hi there! > > > Quick question. Is anyone using the Nios II IDE (Quartus II Software > version 4.1 by Altera)? If so, I'm having difficulties in how to > include certain header files, e.g. socket.h and so on when using the > C/C++ editor. Is there an option, I can select which tells the IDE > where to find those header files? In the installation directory of > Quartus I've already spotted lot's of these .h files, problem is the > IDE obviously doesn't know that :-( > > A workaround that I've found is to include those files manualy in my > project using File -> Import, but in a larger project where header > files depend on other header files, this becomes very time consuming > and therefore doesn't seem to be a very smart solution. > > I've also tried right click on the root directory of the project -> > System Library Properties -> C/C++ Build -> Include Paths, and entered > the path where my needed headers are located, but to no avail. > > > Any hints or solutions are greatly appreciated, because a site search > at Altera wasn't very enlightning for me either. > > regards, > Chris.Article: 75573
johnsonlee@itri.org.tw (Johnson Lee) wrote in message news:<8bd844de.0411080725.d52350@posting.google.com>... > > > Hi Andrew, > > > Yes, you are right about those 5 different tests! > > > And I didn't check all outputs using oscolloscope only Enable pin and > > > some data bits. I can see from oscilloscope when enable pin is > > > initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD > > > module is switched on, but remain 3.0V when LCD is off. > > > > Those voltages don't sound right. The logic should swing from 0 to > > Vcc. What power supply voltage are you running the CPLD / FPGA at? > > 5.0V or 3.3V? What power supply voltage are you running the LCD at? > > You're not missing a ground connection somewhere are you? > > > > > Same IO assignment in those files... > > > Ya, I can show you my code! > > > But I don't know how to do that! > > > Mail the .QAR to you directly? > > > > Can you put it on a web server and post the URL? > > If not, my mail is http://www.holmea.demon.co.uk/IMG/email.gif Hi Andrew, I already find the bug. It was the software which read the busy flag when system boot up. I am going to modify my code. Thanks for sharing your time with me discussing this problem! BR, Johnson LeeArticle: 75574
On Tue, 09 Nov 2004 22:03:51 -0800, Johnson Lee wrote: > johnsonlee@itri.org.tw (Johnson Lee) wrote in message news:<8bd844de.0411080725.d52350@posting.google.com>... >> > > Hi Andrew, >> > > Yes, you are right about those 5 different tests! >> > > And I didn't check all outputs using oscolloscope only Enable pin and >> > > some data bits. I can see from oscilloscope when enable pin is >> > > initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD >> > > module is switched on, but remain 3.0V when LCD is off. >> > >> > Those voltages don't sound right. The logic should swing from 0 to >> > Vcc. What power supply voltage are you running the CPLD / FPGA at? >> > 5.0V or 3.3V? What power supply voltage are you running the LCD at? >> > You're not missing a ground connection somewhere are you? >> > >> > > Same IO assignment in those files... >> > > Ya, I can show you my code! >> > > But I don't know how to do that! >> > > Mail the .QAR to you directly? >> > >> > Can you put it on a web server and post the URL? >> > If not, my mail is http://www.holmea.demon.co.uk/IMG/email.gif > > Hi Andrew, > I already find the bug. > It was the software which read the busy flag when system boot up. > I am going to modify my code. > > Thanks for sharing your time with me discussing this problem! > I can only speak for myself, but I believe others might agree with me - coming back to the NG to say what you've done, its results, and especially acknowledging the help, is a Good Thing. Thanks. Rich
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