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Jon Kirwan wrote: > > On Wed, 16 Aug 2000 11:11:51 -0400, "¸.·´¯`·.¸.·>Strings" > <ggilbert@prsguitars.com> wrote: > > >What are ya gonna do? Catch 22. Sign it and see, or go elsewhere. > >I personally haven't found it so difficult to sign the NDA. > >It's dependent upon the level of employment, and the directness of > >competition. > > I'd not sign and I haven't ever done so, for a job interview, in the > nearly 30 years I've been in business. There hasn't been a need yet. > > I suppose if the business was interested in sitting down with me to > explain in great detail, on paper as an addendum, what exactly it was > they intended and if it made sense when made concrete that way, I > might. But for a job interview, that sounds like a big burden to > start on. We'd probably both be better off saving the effort. > > No NDAs just for a job interview. The fact that some people are in a > bad enough situation, job wise, to need to sign such things doesn't > make them sensible. They aren't. I feel the same way. I am finding that different companies handle this issue differently. > However, I'll have to defer on whether there is substance with which > to enforce them on. I don't really know. But it doesn't seem that > there is much worthy of enforcement, since there is no way the signer > knows what they are expected to do under it. They probably don't > know, even after they leave. There is no meeting of the minds and > probably no value received. But I'm not an attorney. > > It's still stupid to sign one for an interview, in my opinion. > > Jon It certainly should not be necessary. When I post my experience from this morning you will see that the company was being very anal and the engineers were not planning on divulging any confidential info anyway. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24676
OneStone wrote: > I do embedded systems, I'm mad. I work ludicrous hours, I drink caffeine > and have the worlds most disturbed diet. I consider psychology and > psychiatry one rung at least below witch doctors. I don't do psych > tests, pee in bottles or sign anything to get an interview and neither > should anyone else have to. At the end of the day there is a world wide > shortage of good engineers so if they get too obnoxious with their tests > they won't find many takers, and will end up the losers. If you have not been reading Ayn Rand, you should... Try "Atlas Shrugged". -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24677
Jon Kirwan wrote: > > There is no value obtained from someone showing you something you cannot use > anywhere else. No value at all. Not exactly so true. If there is value in it to another company then it has value. They do not want you to be the one to sell it to them. The whole point behind any sell is to take something you have and exchange it to someone else for something you want more. If you have a secret that means nothing to you personally as long as you keep it but has value to someone else then it does indeed have intrinsic value.Article: 24678
Hi Everyone, Just wanted to thank all of you for your help. It was greatly appreciated, and extremely helpful. The simple fix and my project objectives are now completed. :) And I learned a great deal about XILINX chips and FPGAs. Here is the working solution: I disconnected my external clock from the STARTUP CLK pin (I left the clear). And I added two BUFG...the first to my user clock feeding the initial clock divider, and the second on the output of the clock divider (which feeds the rest of the circuit). This seems to have fixed everything. Thanks, RamyArticle: 24679
Hello, I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?) Also, If any of you know some web-sites that could provide information on programming FPGAs with PROM that would be helpful too. Thanks, RamyArticle: 24680
Come to where the traffic and pollution aren't. I am recruiting for ASIC engineers of all levels. Must at least have at least a BS and some development experience. The company is young, in start-up mode and willing to make it worth your time. I'm also searching for PCB Design Engineers; Software Development Engineers experienced in embedded development with Power engineering in their background; ASIC engineers for a quickly growing international company… OR Embedded developers with experience in networking or telecom environments. Spokane has mountains, trees, lots and lots of lakes and very little traffic. All of these companies offer stock options and the ability to get on the cutting edge of technology without having to live in a concrete jungle. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24681
Send resumes or questions regarding these postions to jhatley@voltservgp.com Thanks, Jason In article <8nevip$nk7$1@nnrp1.deja.com>, jason_hatley@my-deja.com wrote: > Come to where the traffic and pollution aren't. > > I am recruiting for ASIC engineers of all > levels. Must at least have at least a BS and > some development experience. The company is > young, in start-up mode and willing to make it > worth your time. > > I'm also searching for PCB Design Engineers; > Software Development Engineers experienced in > embedded development with Power engineering in > their background; ASIC engineers for a quickly > growing international company… > OR > Embedded developers with experience in networking > or telecom environments. > > Spokane has mountains, trees, lots and lots of > lakes and very little traffic. > > All of these companies offer stock options and > the ability to get on the cutting edge of > technology without having to live in a concrete > jungle. > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24682
Most Xilinx FPGAs are being programmed from a serial PROM. It is the most popular form of configuration. You can read up on it in the Xilinx documentation, in the data book, in the software manuals, on the Applinx CD, or on the web. It's called Master Serial configuration mode. Peter Alfke, Xilinx Applications Ramy wrote: > Hello, > > I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?) > > Also, If any of you know some web-sites that could provide information on programming FPGAs with PROM that would be helpful too. > > Thanks, > RamyArticle: 24683
Hi all I'm new to Xilinx FPGAs, although I've done several Viewlogic schematic based Actel designs. I'm starting a design which should fit in a Xilinx Spartan II, either a XC2S30 or XC2S50. I need to use the blockRAM in dual port mode. I have access to Mentor products, and would like to use mainly HDL, although I may want to enter some sections of the design as schematics. It looks like the Mentor FPGA Advantage suite (Renoir, ModelSim, and Leonardo) will work for me. Anyone out there have experience with this toolset for the Spartan II target? I assume I also need the Xilinx Alliance software? TIA Paul SmithArticle: 24684
My students and I are working on a multi-FPGA project using Virtex series parts which we want to be able to program via the JTAG interface. We have the Xilinx JTAG parallel port cable as well as the alliance programing s/w, and they work fine. However, we want to be able to program (and possibly perform some boundary scan tests) from within our own home brew software. We've played around a bit and found that, while we can access the parallel port and still leverage the Xilinx cable, we are unable to get nearly the port performace the Xilinx software gets. (less than half). Because we are using about 16 FPGA's in our design, programming time is a factor. Is there source code available to help with this task, or is there someone knowledgeable in parallel ports I could be put in contact with? To further complicate matters, we are developing under Winnt. Thanks, Steve BermanArticle: 24685
I have a question about the Spartan II block RAM. I need to write as fast as possible into one port of a dual port RAM. The CLK minimum pulse widths are specified as 1.9 nS for high and low. There is no spec for cycle time. Can I just derive the cycle speed as 1/(1.9 + 1.9) = 263 MHz? Or am I missing something? TIA Paul SmithArticle: 24686
Hi, In the last EDA in LA at least one company we talk to claim to have 0.08 already in work even tho' still not in production phase, if I recall right they menation, the end of the year as the time they will be ready for production. have a nice day Illan In article <399A2463.9278707A@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > Patrick Schulz wrote: > > Rick, > > > > I know of a alternative lithography method currently used in MPW runs, which is called Direct Slice > > Writing (DSW). They use electron-beams to write patterns directly onto a wavers resist layer and can > > achieve resolutions up to 0.07um. But of course that is too expensive for mass production. > > The lithography people say that wavelengths below 0.13um become unusable, because materials for > > lenses and masks become completely absorbant at this wavelength. Therefore, feature sizes below > > 0.10um could not be managed by common lithographic methods. > > > > Patrick > > Then what is planned beyond .10 um? This is not very far away as .12 um > is currently being set up in the latest fabs under construction I > believe. Certainly they must know what is planned for 0.08 um since it > is likely only two years away (or maybe less). > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24687
No suffix is needed on a UNIX machine, just make the file executable by setting it's properties. On a PC a suppose the suffix could be .bat Thomas "zheng Daixun" <y917@hotmail.com> skrev i diskussionsgruppsmeddelandet:F119S62JAm2RKS6Qn3b0000167e@hotmail.com... > I want to ask how to use script file in Xilinx Design Manager. > I need to run the following command with the parameter by sequence. > ngdbuild > map > par > bitgen > promgen > > I know I can write them to a script file. But how to use this script file? > What is the suffix of this script file. > > Thanks! > > Hu > ________________________________________________________________________ > Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com > > > -- > Posted from [131.227.8.189] by way of f119.law3.hotmail.com [209.185.241.119] > via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 24688
"Ramy" <ramy@cim.mcgill.ca> ha scritto nel messaggio news:ee6d8f0.-1@WebX.sUN8CHnE... > Hello, > > I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?) > > Also, If any of you know some web-sites that could provide information on programming FPGAs with PROM that would be helpful too. > > Thanks, > Ramy Use Actel anti-fuse FPGA... http://www.actel.com/ Renzo VenturiArticle: 24689
On 16 Aug 2000 15:31:53 -0500, William Killian <killian@mnsinc.com> wrote: >Jon Kirwan wrote: >> >> There is no value obtained from someone showing you something you cannot use >> anywhere else. No value at all. > >Not exactly so true. If there is value in it to another company then it >has value. They do not want you to be the one to sell it to them. Yes, it has value to others perhaps. But no value to me. So I have received no consideration at all. >The whole point behind any sell is to take something you have and >exchange it to someone else for something you want more. If you have a >secret that means nothing to you personally as long as you keep it but >has value to someone else then it does indeed have intrinsic value. It seems better to simply avoid the whole scenario. JonArticle: 24690
Yes. Just look at the corresponding Virtex spec: it lists an extra line: "Min clock period to meet address write cycle time", and that value is exactly twice the min pulse width. But make sure you buy the right speed grade, and don't run the part hotter than spec ( 85 degr junction) You are running close to the edge, but we stand behind our worst-case specs. :-) Peter Alfke, Xilinx Applications =============================== Paul Smith wrote: > I have a question about the Spartan II block RAM. > > I need to write as fast as possible into one port of a dual port RAM. > > The CLK minimum pulse widths are specified as 1.9 nS for high and low. > There is no spec for cycle time. Can I just derive the cycle speed as > 1/(1.9 + 1.9) = 263 MHz? > > Or am I missing something? > > TIA > > Paul SmithArticle: 24691
All: Does anyone have any leads on chip vendors for the upcoming jpeg 2000 video compression standard? Any help would be appreciated. Mike Spencer ============================================================================== Michael Spencer 520 794 2957 (office) Electrical Engineer 520 794 5452 (fax) Raytheon Systems Company PO Box 11337, Bldg 805 M/S F6 Tucson, AZ 85734 mjspencer@west.raytheon.com ==============================================================================Article: 24692
Renzo Venturi wrote: > "Use Actel anti-fuse FPGA... > You forgot the :-) Otherwise we are going to let out the secret about all the Antifuse FPGAs used up in the debugging process. :-) Peter AlfkeArticle: 24693
Hi Paul, You are missing something and a bit. My limited experience tells me this. Anyways, the experts should be answering you soon with the details For now, the data sheet boasts 200MHZ performance. This would be best case and would only apply to certain operations. Read over the IO switching delays on page 48 of the Spartan II data sheet. Sincerely Daniel DeConinckArticle: 24694
Xilinx has a serial prom that's made for the purpose. Actel also offers Xilinx compatible serial proms. Ramy wrote: > > Hello, > > I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?) > > Also, If any of you know some web-sites that could provide information on programming FPGAs with PROM that would be helpful too. > > Thanks, > RamyArticle: 24695
The licensed distees for Xilinx have no stock on Spartan II. NuHorizons Insight Avnet I have been calling for several months, since I first read the data sheet. Its always the same answer; 4-8 weeks, but the answer has never changed. WHEN WHEN WHEN will they be in stock!!! I would like to buy several different parts for new projects but the frustration makes me direct my energies elsewhere. SIncerely Daniel DeConinckArticle: 24696
Folks,
I am working on a digital QPSK demodulator and run into problems of
designing an all-digital phase-locked loop (ADPLL) for the carrier
recovery circuitry.
The basic design of the QPSK demodulator is being simulated in
Matlab/Simulink, and the design uses a Costas Loop to recover the
carrier. I am closely following the design as suggested in figure 8.38
(p. 444) of Marvin E. Frerking's book "Digital Signal Processing in
Communication Systems". If anyone is interested in the block diagram, I
can redraw and post the block diagram onto my web page for reference.
Anyway, The Costas Loop generates an error signal +/- A/2 *
sin(theta), where theta is the phase difference between the incoming
signal and the VCO's output. I also have an NCO design from my
colleague which takes two inputs: frequency word and phase offset word,
and generates the corresponding cosine and sine signal for I/Q
demodulation. My biggest problem is how do I design the loop filter to
map the error signal to the corresponding phase offset word, and how do
I design the system so that it is stable? I have read some books on the
design of phase-locked loops in general, but none of them really dig
deep into the details of a design: what is the effect of the table size,
how to design the loop filter (FIR, IIR, etc.), how to design the NCO,
and how to analyze the loop for ensure it is stable, etc.
I would appreciate if someone could point me to a good book, a
paper, or online reference about the design of such a PLL. Thank you
very much.
Artur
8.16.2000
Article: 24697The easiest way is to use one of the serial PROMs offered by Xilinx or Atmel. The FPGAs will automatically load from these if you set the mode pins correctly. Look on the Xilinx site for the XC17XX prom family Ramy wrote: > > Hello, > > I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?) > > Also, If any of you know some web-sites that could provide information on programming FPGAs with PROM that would be helpful too. > > Thanks, > Ramy -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24698
Yes, you can. The Spartan data sheet is missing the line of the Virtex data sheet that claims a min cycle time equal to twice the min pulse width. But remember to order the proper speed grade, and to keep the junction temperature below the guaranteed 85 degrees C. You are very close to the edge, but we guarantee our worst-case numbers. :-) PeterAlfke, Xilinx Applications Paul Smith wrote: > I have a question about the Spartan II block RAM. > > I need to write as fast as possible into one port of a dual port RAM. > > The CLK minimum pulse widths are specified as 1.9 nS for high and low. > There is no spec for cycle time. Can I just derive the cycle speed as > 1/(1.9 + 1.9) = 263 MHz? > > Or am I missing something? > > TIA > > Paul SmithArticle: 24699
I had my interview with company A this morning. It started out a little uneven. I entered and was presented with the application, NDA and some other paperwork to fill out. I was also asked to sign into the visitors log. However the visitor's log was like none I had ever seen before. Each visitor had an entire page with a three paragraph agreement to sign. One of the paragraphs was a brief, but broadly worded NDA. Words to the effect that I would not divulge any information that I obtained while at this facility. I did not sign. I just filled in my name and other info and left it at that. I then proceded to fill in the application. When it came to the NDA, I had decided that the best approach was to add a line to the NDA that indicated that a written statement would be provided of all confidential information divulged to me. When the first interviewer came to greet me, I spoke with him about my concerns. He told me that no proprietary information would be shared with me during the interview. I asked then if the NDA was not needed. The receptionist said it was required. I stated my need for a written statement of what was disclosed to me and the interviewer indicated that this was not a problem. I added my line to the NDA and signed it. The interview proceded in the lunch room as they were doing mass interviews and the conference rooms were all booked. We spoke for about a half an hour during which I was told only superficial information about their products and processes. A second interviewer began and presented me with a series of "test" questions that were well thought out although a bit vague. This actually simulated a real project rather well. Again, no information that could be considered confidential was disclosed to me. The third interview was conducted by a pair of mechanical engineers who almost immediately confessed that they were in no way qualified to test my knowledge of EE work. So I took the lead and we discussed some of the issues relating to integration of electromechanical systems. Nothing proprietary was discussed. Only very general statements like, "we use photodiodes to detect the light along with high gain amplifiers". The fourth interviewer was a person that I had spoken to on the phone. We prepared to move to another building when a party of several people entered and asked if I was Rick Cole. I identified myself and listened to an explanation of why they were terminating the interview. When I altered the NDA, I broke their policy so that they needed to get me out of their building. They were polite about it, but it was clear that they considered me a threat. So I left on good terms mentioning that they were welcome to consider me for future consulting work. I am not sure if I will be receiving a call anytime soon. ;) In retrospect, I think it would have been better if instead of changing the NDA, which I could only expect to be met with considerable resistance, I should have simply taken good notes and asked each interviewer to sign. This would have been more likely to slip past scrutiny and I would likely have an offer that I then would be able to accept or turn down. The funny part was that on the way out they asked me to complete the signout procedure. While doing that they noticed that I had not signed the mini-NDA. This was pointed out. I pointed out that it was an NDA. I was asked to sign it by the HR person. I could not help but laugh a bit. I guess they thought I had as much nerve as I thought they did. Meanwhile I spoke to a manager from company B. They also have a NDA for the interview. We discussed the issues of my signing an NDA and agreed that the best thing would be to have the interview and for them to not divulge any confidential information. So I will interviewing tomorrow with company B. We will see if the manager was stepping beyond his bounds and I get the boot in the middle of the interview. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z