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Some suggestions...
As someone else has suggested you must make certain that the power
supplies are properly bypassed. Also make certain that the i/o lines are
properly terminated. At the speed that the virtex chips operate the chip is
easily subject to stray glitches from these types of sources. Given your
comment about your hand I would suspect the unterminated i/o lines as a major
potential problem. A third potential problem may be the A/D converter
itself. I know that at least one video A/D converter on the market is subject
to generating glitches. Check the ap notes on the A/D converter. Good luck.
Dan wrote:
> Hello
>
> V50-6PQ240C with a 2.5V supply from a LM2937ET-2.5 and a Vcco at 3.3 volt
> from a LM2937ET-3.3.
>
> The TTL inputs are noisy. I am interfacing the V50 to a SAA7110 Philips
> video ADC.
>
> How reliable is the V50 with 5V TTL inputs?
>
> By touching (with my hand) the input trace & pins I am able to get a clean
> input. But I can not be shipped with the product.
>
> I wonder if the one chip I have is flaky ? I tried bringing in other TTL
> signals from another PCB via a patch wire and had the same poor results.
>
> I have several successful Xilinx designs using the SAA7110. This is my
> first Virtex design and this is a real road block.
>
> Ideas.
>
> Sincerely
> Daniel DeConinck
Article: 24576Ramy, Your problem may be due to the delay from your 8-bit counter to the I/O pins of the FPGA device - if theses delays are not all of a similar value, then the DAC will glitch from one value to the next. 1. Which Development Package are you using - are you using VHDL or Schematics. 2. Which DAC are you using. 3. Assuming the DAC simply converts the 8-bit value from the FPGA (i.e. there are no clocks to clock the data into the DAC device) then you must ensure that all 8-bits are presented to the DAC at the same time. The easiest way to do this is to use the output flip-flops in the I/O cells of the FPGA (OFD flip-flops in the IOB's). This is easy to do in Schematics, a bit trickier in VHDL. There is also an implementation switch in the software to force the use of IO flip-flops. Regards, Neil Carrington (Xilinx FAE for Insight Memec - UK) "ramy" <ramy@cim.mcgill.ca> wrote in message news:ee6d780.-1@WebX.sUN8CHnE... > Hello, > > I have been working with the Foundation Series to program my XC4010E-4 PG191, and I have been having many problems. Any ideas or suggestions would be greatly appreciated. > > What I need: > I need to create a triangular wave voltage signal. I implemented an 8-bit counter that counts from 0 to 255 to 0 and back to 255, etc. The output goes through a D/A converter and to an amplifier to generate at 30V peak to peak triangular wave. > > Problem: > Occasionally, the bit file will program correctly, and the triangle wave will be as desired. However, when I implement other parts of the Xilinx control circuit, the new bit file does not program the chip correctly: the resulting triangle wave is not smooth, but rather a very odd shape that is more like a staircase. > > The previous version of this project has used the XC4010 version of the chip and works correctly. However, I am currently using Foundation Series which only implements the XC4010E library. However, the results are identical when programming the XC4010 and XC4010E chips. > (note, the XC4010E chip is backwards compatible with XC4010, but differs by architectural enhancements.) > > If you have any idea what might be causing this problem, ideas or solutions (anything!!) or would like me to provide more information, please e-mail me ramy@cim.mcgill.ca. > > thanks, > RamyArticle: 24577
disk wrote:
> > Please try to read any VLSI or ASIC book that you get.
>
> Please don't always think that your are the best and so we must read book
> because you don't want to answer any question... If you think that some
> question are not interresting for you, please, forget it! Or the next time,
> please, forget the first word "Please"! You are not in your scool but over
> Internet, here !
>
> Tankx
> Paul
Paul,
If you want help you should not insult the one you are asking to help you.
On the other hand, I think the question was answered correctly and without any
insult being given.
Article: 24578
>>>>> "Ben" == Ben Franchuk <bfranchuk@jetnet.ab.ca> writes:
[main subject removed...]
Ben> Ben.
Ben> PS.I still have to find a good generic postscript printer to use.
For reasonable volume (ie typical home use) I recommend the Lexmark Optra
Color 40, _if_ you can still find them. Lexmark was trying to offload their
remaining stock through distributors. It's inkjet printheads are compatible
with their current printers (so you should not have refill supply problems)
and it does real color postscript. I got mine about two or three months ago
for about $85 (US) from buy.com. I was looking for a printer that
intergrated seemlessly in Windows AND Linux. Real parallel port and genuine
postscript. For memory upgrades (if you should so desire) it takes standard
SIMMs that folks are throwing away from their old 486s. I up'ed mine from
4MB to 20MB. It doesn't get much more standard than that. Inexpensive too!
--
Scott Bilik VAutomation Inc.
http://www.vautomation.com 402 Amherst St #100
(603) 882-2282 x24 Nashua NH 03063
Article: 24579Hi all, Is anybody using above tools? I have a mixed design(verilog and VHDL). So I synthesised these blocks independently in Certify and replaced the verilog module by black box in certify(with estimated LCells). Then I used both .vqm file genertaed by Certify in Quartus for actual P&R. Now the problem is Quartus is not taking into account the LCells of verilog module, although its compiling and fitting properly into the APEX devices. I am getting approx 8000 less LCells(which is for verilog module)... The report file of Quartus shows the verilog module with complete hierachy... Any help?? Rgds Sanjay -- Sanjay Kumar Sharma ASIC Design Engineer Philips Semiconductors Eindhoven, The NetherlandsArticle: 24580
disk wrote: > > > Please try to read any VLSI or ASIC book that you get. > > Please don't always think that your are the best and so we must read book > because you don't want to answer any question... If you think that some > question are not interresting for you, please, forget it! Or the next time, > please, forget the first word "Please"! You are not in your scool but over > Internet, here ! Paul, Sorry, me reply should not offend you or Jon. Patrick -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 24581
Austin Tempany wrote: > > Patrick, > Can you suggest a suitable text book - something practical that gives me the basic knowledge. > Cheers, > Austin > -- > ------------------------------------------------------------ > Integrated Silicon Systems Ltd. Tel: +44 28 90 50 4000 > 50 Malone Road Fax: +44 28 90 50 4001 > Belfast BT9 5BS Web: www.iss-dsp.com Austin, I don't know a book especially for test, because it comes mostly with synthesis. But there is a book containing the whole asic design flow, including test, which doesn't go in details, but cover the whole flow. "It's the Methodology, Stupid!" Kurup, Abbasi, Bedi ByteKDesigns, Inc. ISBN 0-9663301-0-2 But be aware it's facile. The whole I know comes from the user guides and tutorials from synopsys, they are really good. Patrick -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 24582
Hello, I having a problem with a signal which needs to be connected to d-flipflop clock input which is not a globally defined clock such as used with flex10k devices. The problem is very fundemental one: A change in a signal must occur after a clock change from low->high and not before it. I'm having this problem with a shift register: suppose we have: DFF1.clk= semiclk DFF2.clk= semiclk + delay1 DFF1.q= DFF2.d (after delay2) I need to be sure that delay2 > delay1 + holdtime(DFF2)? How do I accomplish this? Can I assign a special status to my clk line which cant be a globally defined clock line? Regards, JasperArticle: 24583
Peter Alfke wrote: > > For the article on crossing clock boundaries, just click on: > > http://www.isdmag.com/editorial/2000/design0003.html > > Peter Alfke > =============================================== > Barry Brown wrote: > Peter, is it possible to get this article as .pdf or .ps ? I dont want to republish it, just for educational purposes! Thanks Patrick -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 24584
Philip explained the error you are seeing. I think your problem with the circuit not working may be from your clock distribution. You did not say that you route the 2 MHz clock through a clock buffer. In order for the clock to arrive at the different FFs at the same time (or close enough) you need to use the dedicated clock routing. This is done by adding a clock buffer to the clock net at the output of the 2 bit divider. That may well solve your problem. If you don't have a clock buffer, it certainly would explain why you are seeing different results on different routes of the chips. As the routing delays change, some parts of the circuit work and others don't, seemingly at random. Ramy wrote: > > Thanks Peter. > > I suspect the problem is in the bit file generated. This is the log file BOX.BGN at the end. It mentions a possible warning about the STARTUP and the CCLK. I don't understand what it means. Could you explain its meaning and a possible fix? > > I'm using an external 8 MHz clock that is divided into a 2 MHz clock inside the chip. This clock signal is connected to the STARTUP and all other flipflops, etc. The external 8 MHz clock is used only to clock the 2-bit clock divider. > > Another possibility is that my XCHECKER.EXE program might be too old to program the chip? I'm using a DOS version 5.2.0. I haven't been able to find a more recent version. If you know where I can find it, (DOS or UNIX) that would be great. > > This is the log file: > ---------------------------- > Loading device database for application Bitgen from file "box.ncd". > > "box" is an NCD, version 2.27, device xc4010e, package pg191, speed -4 > > Loading device for application Bitgen from file '4010e.nph' in environment > > C:/fndtn. > > Opened constraints file box.pcf. > > BITGEN: Xilinx Bitstream Generator M1.5.25 > > Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. > > Fri Jul 21 13:13:47 2000 > > bitgen -l -w -g ConfigRate:SLOW -g TdoPin:PULLNONE -g M1Pin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no -g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 -g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable -g M0Pin:PULLNONE -g M2Pin:PULLNONE box.ncd > > WARNING:x4kbs:36 - There is a STARTUP component with a signal on the CLK pin > > but StartupClk is Cclk. > > Running DRC. > > DRC detected 0 errors and 0 warnings. > > Saving ll file in "box.ll". > > Creating bit map... > > Saving bit stream in "box.bit". -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24585
Patrick Schulz wrote: > Peter, > > is it possible to get this article as .pdf or .ps ? > You can cut and paste this article to your heart's desire. (Or is that because I have a Mac?) Schöne Grüße PeterArticle: 24586
Can anybody show me ( or point me toward a reference)how does a bit serial Baugh-Wooley multiplier work??? I have a book which describes an array multiplier (bit parallel) based on Baugh-Wooley algorithm. I wanna know how does a bit serial one work? Please Help!!! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24587
If you need to build a shift register, but your clock uncertainty is large, use two flip-flops per bit and clock the even numbered flip-flops on the rising edge, and the odd numbered ones on the falling edge. That gives you a clock High or Low time tolerance against clock skew. Very safe, but wasteful. But then FPGAs have lots of flip-flops... Peter Alfke, Xilinx Applications ========================================== Jasper Hendriks wrote: > Hello, > > I having a problem with a signal which needs to be connected to d-flipflop > clock input which is not a globally defined clock such as used with flex10k > devices. > > The problem is very fundemental one: > A change in a signal must occur after a clock change from low->high and not > before it. > > I'm having this problem with a shift register: > suppose we have: > > DFF1.clk= semiclk > DFF2.clk= semiclk + delay1 > > DFF1.q= DFF2.d (after delay2) > > I need to be sure that delay2 > delay1 + holdtime(DFF2)? > How do I accomplish this? Can I assign a special status to my clk line which > cant be a globally defined clock line? > > Regards, > > JasperArticle: 24588
This was a valid question that deserves more than a flip answer, and "disk" (whoever you are): we can do without your vitriolic comments. Let's all be nice here ! As usual, there is a short and a long answer: Basically, the number describes the smallest dimension achieved on the chip, usually the gate length of the transistors. 0.35 microns is pretty old. We are now designing to 0.15 and even 0.13 micron gate length. The shorter this value, the faster the transistors, and the smaller the chip, and the more logic can be crammed on the largest manufacturable chip.about an inch square. But also the lower the supply voltage. By a quirk, the supply voltage ( in V ) is almost exactly the same number as the transistor gate length ( in microns) times hundred. So, 0.35 micron = 3.3 V, 0.25 micron = 2.5 V, etc. Metal width tends to be somewhat larger than the min gate length. And metal pitch is usually twice the metal width. At 0.2 micron horizontal width, and 1 micron vertical height, the metal lines are not the way you usually think of them, e.g. the way they are on a pc-board... It's all a matter of photolithography, using lots of optical trickery to achieve a resolution that is significantly smaller than the wavelength of the UV light being used. But the industry wants to stay with optical methods as long as possible, since X-rays or e-beam are far more expensive. Peter Alfke, Xilinx ApplicationsArticle: 24589
I don't see any problems with what you've tried. It may be something to do with how you're using pci_clk in your upper level module. Does it come straight from an input at the top level? I've done this same kind of thing in a top level module and as a submodule. (I'm using Leonardo 1999.1j with Alliance 3.1i) Nicolas Matringe wrote: > > hi > I am trying to sythesize a design with Leonardo Spectrum but I have > problems with the clock buffers and the DLL. > When I do not explicitly use clock buffers (only the DLL), ngdbuild > gives me a warning (something like "you should use a BUFG for your clock > signal") and then the mapper complains that the DLL cannot be driven by > an IPAD (Leonardo automatically put a IPAD) > So I tried to explicitly instantiate clock buffers but then ngdbuild > complains that a clock signal (called pciclk_int) has multiple drivers > and an illegal connection. > Any idea? I'm desperate... > > (anyone at Exemplar: I am evaluating Leonardo. Help me or I won't buy > ;o) > > Sample code (Verilog) : > > module inv_clk > (pciclk, bpciclk, nclk, rst); > > input pciclk; > input rst; > output nclk; > output bpciclk; > > wire neg_clk; > wire pciclk0; > wire iclk; > > CLKDLL dll0 ( > .CLKIN (iclk), > .CLKFB (bpciclk), > .RST (rst), > .CLK0 (pciclk0), > .CLK180 (neg_clk)); > > IBUFG clk_buf ( > .I(pciclk), > .O(iclk)); > > BUFG neg_bufg ( > .I(neg_clk), > .O(nclk)); > > BUFG pos_bufg ( > .I(pciclk0), > .O(bpciclk)); > > endmodule > > -- > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE > Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 24590
On Mon, 14 Aug 2000 09:44:47 -0400, Theron Hicks <hicksthe@egr.msu.edu> wrote: >Paul, > If you want help you should not insult the one you are asking to help you. I think it was Jon asking, not Paul. JonArticle: 24591
I'm not 100% sure of the names, but I believe Baugh-Wooley is the method of modifying the output to make it correct for signed (2's complement) inputs. It doesn't translate to bit serial as well as treating one input as having a negative weight in the MSB. jj_okocha@my-deja.com wrote: > > Can anybody show me ( or point me toward a reference)how does a bit > serial Baugh-Wooley multiplier work??? I have a book which describes an > array multiplier (bit parallel) based on Baugh-Wooley algorithm. I > wanna know how does a bit serial one work? > > Please Help!!! > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 24592
Are you sure that Gray is a valid encoding style for an FSM? Although Gray may be used for counters, it may not be valid for FSMs. Have you looked at the machine logic produced to see if you are really getting some sort of Gray code? threehero wrote: > > Later,I find the automated conversion into "one-hot" does not occur any > more, when I don't choose the option of Symbolic FSM Compiler in the main > window of Synplify. So I think it is the Symbolic FSM Complier that performs > the optimization of FSM during synthesis and converts the state-encoding to > "one-hot" automatically, though I hava specify it as "gray" using the > attribute of syn_encoding as follows: > -- synthesis syn_encoding= "gray" . -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24593
This message has no body. The body was in the subject. Well, the real meat of the message was in the subject. However that now appears to be changing. Back to debugging my XCV50.... DanArticle: 24594
Baugh-Wooley is a parallel algorithm by definition. Its like asking how do you do parallel multi CPU processing on a single CPU. Answer you don't. You might want to ask what would be a good bit serial algorithm. Steve "Ray Andraka" <ray@andraka.com> wrote in message news:39984C55.2A5DA23D@andraka.com... > I'm not 100% sure of the names, but I believe Baugh-Wooley is the method of > modifying the output to make it correct for signed (2's complement) inputs. It > doesn't translate to bit serial as well as treating one input as having a > negative weight in the MSB. > > jj_okocha@my-deja.com wrote: > > > > Can anybody show me ( or point me toward a reference)how does a bit > > serial Baugh-Wooley multiplier work??? I have a book which describes an > > array multiplier (bit parallel) based on Baugh-Wooley algorithm. I > > wanna know how does a bit serial one work? > > > > Please Help!!! > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 24595
rickman wrote: > I am interviewing for jobs and I am finding more than one company > that wants me to sign a non-disclosure (ND). > This is disturbing to me since it puts me in a difficult position. > Let's say I sign a ND with company A > and take a job with company B who is a direct competitor. > I end up working on a project > similar to the one that company A told me about. > So because I interviewed with company A > I am now liable for a lawsuit? > > Is this what a lot of companies are doing now? > Are interviewees generally willing to sign such agreements? > > I had gotten to the point where I decided that > I would not "pee in a bottle" to conduct an interview. > I found that companies were using this as a way to reject applicants > without giving them a chance to object to the drug test results. > If you flunk the test because you ate a poppy seed roll that morning, > you just don't get an offer. No offer, no challenges. > > Now they want you to sign away the right to work > on a competing product just to get an interview? Nonsense! Nobody is asking you to sign a non compete agreement before you interview or accept a job offer. They are asking you to promise to sign a non compete agreement if you are offered a job and accept that offer. Your prospective employer needs to be "up front" with you and tell you everything that is expected of you should you accept employment. No contract between you and a prospective employer would have any force in law unless they paid you. If you feel queezy about signing a non compete agreement, look for work elsewhere. Don't waste your time or theirs.Article: 24596
I am interviewing for jobs and I am finding more than one company that wants me to sign a non-disclosure (ND). This is disturbing to me since it puts me in a difficult position. Let's say I sign a ND with company A and take a job with company B who is a direct competitor. I end up working on a project similar to the one that company A told me about. So because I interviewed with company A I am now liable for a lawsuit? Is this what a lot of companies are doing now? Are interviewees generally willing to sign such agreements? I had gotten to the point where I decided that I would not "pee in a bottle" to conduct an interview. I found that companies were using this as a way to reject applicants without giving them a chance to object to the drug test results. If you flunk the test because you ate a poppy seed roll that morning, you just don't get an offer. No offer, no challenges. Now they want you to sign away the right to work on a competing product just to get an interview? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24597
Hi Mr Rickman, I won't sign it - I had the same problem recently. During an interview, the company is interviewing you, not so much vice versa, so why would they want a ND? You open yourself to unneccesary litigation by signing. There is another serious hiccup developing here in Alberta, probably in other places as well. Electronic engineers who register as Pr Eng find that it is impossible to obtain Prof Liability Insurance. That should tell one something. (that you should run away screaming?) Firstly, it tells me that my rates are too low by a factor of 10 and secondly, it tells me that I made the correct decision NOT to register as Pr Eng and rather work under the protection of a Limited Company. Interestingly, when I read the AB Eng Prof Act, I found absolutely nothing at all that can be remotely construed to refer to electronic engineering, so although APEGGA would accept a willing EE's money, it doesn't really mean anything, since there is no ground for it in the act and secondly, the impossibility of obtaining insurance, makes it imposible to practice that way. The EEs that do practice as Pr Eng are taking a huge risk, so big that even the large insurance companies don't want any part of it. So even if they do have insurance, the insurance company will probably refuse to cough up in case of a real lawsuit, claiming that Electronics is outside the scope of the insurance policy. So the poor sod just paid thousands of dollars every year for nothing. So, as far as I can see, EEs are in a very precarious position and are simply being ripped off. The only solution I see, is to incorporate and that with a tiered structure: Holding company --> Operating company Each layer of indirection increases the cost of a lawsuit to the other party, by at least $30 000, meaning that it becomes less likely that you will in fact be sued in the first place. As an example: Lawyers typically work at a rate of $180 per hour and they have prof liability insurance, costing them about $5000 per year. So, as an EE, to work without insurance at enormous risk, one should have a rate significantly higher than that. Danger pay in the Army is typically 5x normal wages... Cheers, Herman Oosthuysen Electronic Engineer Member IEEE (not registered with APEGGA) rickman wrote: > > I am interviewing for jobs and I am finding more than one company that > wants me to sign a non-disclosure (ND). This is disturbing to me since > it puts me in a difficult position. Let's say I sign a ND with company A > and take a job with company B who is a direct competitor. I end up > working on a project similar to the one that company A told me about. So > because I interviewed with company A I am now liable for a lawsuit? > > Is this what a lot of companies are doing now? Are interviewees > generally willing to sign such agreements? > > I had gotten to the point where I decided that I would not "pee in a > bottle" to conduct an interview. I found that companies were using this > as a way to reject applicants without giving them a chance to object to > the drug test results. If you flunk the test because you ate a poppy > seed roll that morning, you just don't get an offer. No offer, no > challenges. > > Now they want you to sign away the right to work on a competing product > just to get an interview? > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 24598
rickman wrote: > "E. Robert Tisdale" wrote: > > > > rickman wrote: > > > > > I am interviewing for jobs and I am finding more than one company > > > that wants me to sign a non-disclosure (ND). > > > This is disturbing to me since it puts me in a difficult position. > > > Let's say I sign a ND with company A > > > and take a job with company B who is a direct competitor. > > > I end up working on a project > > > similar to the one that company A told me about. > > > So because I interviewed with company A > > > I am now liable for a lawsuit? > > > > > > Is this what a lot of companies are doing now? > > > Are interviewees generally willing to sign such agreements? > > > > > > I had gotten to the point where I decided that > > > I would not "pee in a bottle" to conduct an interview. > > > I found that companies were using this as a way to reject applicants > > > without giving them a chance to object to the drug test results. > > > If you flunk the test because you ate a poppy seed roll that morning, > > > you just don't get an offer. No offer, no challenges. > > > > > > Now they want you to sign away the right to work > > > on a competing product just to get an interview? > > > > Nonsense! > > > > Nobody is asking you to sign a non compete agreement > > before you interview or accept a job offer. > > They are asking you to promise to sign a non compete agreement > > if you are offered a job and accept that offer. > > Your prospective employer needs to be "up front" with you > > and tell you everything that is expected of you > > should you accept employment. > > No contract between you and a prospective employer > > would have any force in law unless they paid you. > > > > If you feel queezy about signing a non compete agreement, > > look for work elsewhere. Don't waste your time or theirs. > > I don't know where you got your information. I have been asked to sign a > non-disclosure agreement for the interview process. One company > specifically said that they don't feel they can conduct a proper > interview without revealing sensitive information. I think that is > nonsense! This was stated as a precondition to the interview along with > completing an application. It did not even come out until I asked if > there was anything that I needed to sign. I have been through a few > interviews over the years. > > I don't know that a non-disclosure would not be enforceable just because > I was not hired. I remember a story (of course I don't know for sure it > is true, but it was in the book "Fire in the Valley") that told of IBM > requiring Microsoft to sign that MS would not disclose any proprietary > info in their first meeting. Then when IBM was happy that MS had > something to offer, they had MS sign a ND for the second meeting where > IBM spilled thier beans. In neither case did the two companies have any > working agreements that required money to be given. The only requirement > for the ND contract to be enforceable in that regard is that each side > received "consideration". This can take many forms. > > But you are way off base telling me that you know what I was told and > that I don't. A non disclosure agreement wouldn't prevent you from working for a competitor. You just agree not to disclose what you learn in the interview. If the agreement actually prevents you from going to work for a competitor, it is a non compete agreement. Have you read the agreement? Can you post it here? If you need to retain a lawyer to tell you whether you are signing a non disclosure agreement or a non compete agreement, you shouldn't sign anything. Just look for work elsewhere.Article: 24599
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this code from some HDL text book ....
if you want to use , please tell Author (not me)=20
"Peter Alfke" <palfke@earthlink.net> wrote in message =
news:398B90D3.A2B3CE81@earthlink.net...
Eduardo Augusto Bezerra wrote:=20
Hi=20
<Does anybody know the price of a synthesizable 8251A core? I'm also =
looking for a Manchester encoder/decoder. Is there a place where I=20
can find these cores for free? I'll decide which FPGA to use in my=20
design as soon as I find the cores. >=20
=20
A Manchester encoder is trivial, essentially an XOR.=20
A Manchester decoder is described in the Xilinx XCell magazine in =
1995.=20
The design uses only three XC3000 or XC4000 or Spartan CLBs.=20
http://www.xilinx.com/xcell/xl17/xl17-30.pdf=20
Peter Alfke, Xilinx Applications=20
------=_NextPart_001_001F_01C00697.9B4CBDA0
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<DIV><FONT face=3DArial size=3D2>this code from some HDL text book =
....</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>if you want to use , please tell Author =
(not me)=20
</FONT></DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV>"Peter Alfke" <<A=20
href=3D"mailto:palfke@earthlink.net">palfke@earthlink.net</A>> =
wrote in=20
message <A=20
=
href=3D"news:398B90D3.A2B3CE81@earthlink.net">news:398B90D3.A2B3CE81@eart=
hlink.net</A>...</DIV>Eduardo=20
Augusto Bezerra wrote:=20
<P> Hi=20
<P> <Does anybody know the price of a synthesizable 8251A =
core? I'm=20
also <BR> looking for a Manchester encoder/decoder. Is there a =
place=20
where I <BR> can find these cores for free? I'll decide which =
FPGA to=20
use in my <BR> design as soon as I find the cores. > =
<BR> =20
<P>A Manchester encoder is trivial, essentially an XOR. <BR>A =
Manchester=20
decoder is described in the Xilinx XCell magazine in 1995. <BR>The =
design uses=20
only three XC3000 or XC4000 or Spartan CLBs.=20
<P><U><A=20
=
href=3D"http://www.xilinx.com/xcell/xl17/xl17-30.pdf">http://www.xilinx.c=
om/xcell/xl17/xl17-30.pdf</A></U>=20
<P>Peter Alfke, Xilinx Applications </P></BLOCKQUOTE></BODY></HTML>
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name="8251.v"
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filename="8251.v"
/*
Examples from The Verilog Hardware Description Language, by D.E. Thomas =
and P.R. MoorbyExamples=20
from "The Verilog Hardware Description Language"
by D.E. Thomas and P.R. Moorby=20
*/
=20
=20
//THE 8251A EXAMPLE
//Cadence Design Systems, Inc. does not guarantee
//the accuracy or completeness of this model.
//Anyone using this does so at their own risk.
//Intel and MCS are trademarks of the Intel Corporation.
module I8251A(dbus,rcd,gnd,txc_,write_,chipsel_,comdat_,read_,rxrdy,
=
txrdy,syndet,cts_,txe,txd,clk,reset,dsr_,rts_,dtr_,rxc_,vcc);
parameter [7:0] instance_id =3D 8'h00;
parameter [8:1] dflags =3D 8'b00000100; // Defaults for =
diagnostics
// |||||
// diagnostic dflags: |||||
// bit 5 (16) operation event trace <-+||||
// bit 4 (8) communication errors <---+||| (parity, frame, =
overrun)
// bit 3 (4) timing check <-----+||
// bit 2 (2) =3D print receiving <-------+|
// bit 1 (1) =3D print transmitting <---------+
/* timing constants, for A. C. timing check, only non-zero times=20
are specified, in nano-sec */
/* read cycle */
`define TRR 250
`define TRD 200
`define TDF 100 // max. time used
/* write cycle */
`define TWW 250
`define TDW 150
`define TWD 20
`define TRV 6 // in terms of clock cycles
/* other timing */
`define TTXRDY 8 // 8 clock cycles
input
rcd, // receive data
rxc_, // receive clock
txc_, // transmit clock
chipsel_, // chip selected when low
comdat_, // command/data_ select
read_, write_,
dsr_, // data set ready
cts_, // clear to send
reset,// reset when high
clk, // at least 30 times of the transmit/receive data bit rates
gnd,
vcc;
output
rxrdy, // receive data ready when high
txd, // transmit data line
txrdy, // transmit buffer ready to accept another byte to =
transfer
txe, // transmit buffer empty
rts_, // request to send=20
dtr_; // data terminal ready
inout[7:0]
dbus;
inout
syndet; //outside synchonous detect or output to indicate syn =
det
supply0
gnd;
supply1
vcc;
reg
txd,
rxrdy,
txe,
dtr_,
rts_;
reg[7:0]
receivebuf,
rdata,
status;
reg
recvdrv,
statusdrv;
assign
// if recvdrv 1 dbus is driven by rdata
dbus =3D recvdrv ? rdata : 8'bz,
dbus =3D statusdrv ? status : 8'bz;
reg[7:0]
command,
tdata_out, // data being transmitted serially
tdata_hold, // data to be transmitted next if tdata_out is full
sync1, sync2, // synchronous data bytes
modreg;
and (txrdy,status[0],command[0], ~ cts_);
reg transmitter_reset, // set to 1 upon a reset, cleared upon write =
data
tdata_out_full, // 1 if data in tdata_out has not been =
transmitted.
tdata_hold_full, // 1 if data in tdata_hold has not been =
transferred to
// tdata_out for serial transmission.
tdata_hold_cts; // 1 if tdata_hold_full and it was cts when =
data was
// transferred to tdata_hold.
// 0 if tdata_hold is empty or is full but was =
filled
// while it was not cts.
reg tdata_out_wait; // 0 if a stop bit was just sent and we do not =
need
// to wait for a negedge on txc before =
transmitting
reg[7:0] syncmask;
nmos syndet_gate1(syndet,status[6], ~ modreg[6]);
reg sync_to_receive; // 1(2) if looking for 1st(2nd) sync on rxd
reg syncs_received; // 1 if sync chars received, 0 if looking for =
sync(s)
reg rec_sync_index; // indicating the syn. character to be matched
=20
integer breakcount_period; // number of clock periods to count as =
break
reg sync_to_transmit; // 1(2) if 1st(2nd) sync char should be =
sent next
reg[7:0] data_mask; // masks off the data bits (if char size is =
not 8)
// temporary registers
reg[1:0] csel; // indicates what next write means if =
comdat_=3D1:
// (0=3Dmode =
instruction,1=3Dsync1,2=3Dsync2,3=3Dcommand)
reg[5:0]
baudmx,
tbaudcnt,
rbaudcnt; // baud rate=20
reg[7:0]
tstoptotal; // no. of tranmit clock pulses for stop bit (0 if =
sync mode)
reg[3:0]
databits; // no. of data bits in a character (5,6,7 or 8)
reg
rdatain; // a data byte is read in if 1
reg was_cts_when_received; // 0: if cts_ was high when char was =
received
// 1: if cts_ was low when char was =
received
// (and so char was sent before =
shutdown)
event
resete,
start_receiver_e;
reg receive_in_progress;
event txende;
/*** COMMUNICATION ERRORS ***/
task frame_error;
begin
if(dflags[4])
$display("I8251A (%h) at %d: *** frame error",
instance_id, =
$time);
status[5]=3D1;
end
endtask
task parity_error;
begin
if(dflags[4])
$display("I8251A (%h) at %d: *** parity error on data: =
%b",
instance_id, $time, =
receivebuf);
status[3]=3D1;
end
endtask
task overrun_error;
begin
if(dflags[4])
$display("I8251A (%h) at %d: *** overrun error",
instance_id, =
$time);
status[4]=3D1;
end
endtask
/*** TIMING VIOLATIONS ***/
integer
time_dbus_setup,
time_write_begin,
time_write_end,
time_read_begin,
time_read_end,
between_write_clks; // to check between write recovery
reg reset_signal_in; // to check the reset signal pulse width
initial
begin
time_dbus_setup =3D -9999;
time_write_begin =3D -9999;
time_write_end =3D -9999;
time_read_begin =3D -9999;
time_read_end =3D -9999;
between_write_clks =3D `TRV; // start: TRV clk periods since =
last write
end
/** Timing analysis for read cycles **/
=20
always @(negedge read_)=20
if (chipsel_=3D=3D0)
begin
time_read_begin=3D$time;
read_address_watch;
end
/* Timing violation: read pulse must be TRR ns */
always @(posedge read_)
if (chipsel_=3D=3D0)
begin
disable read_address_watch;
time_read_end=3D$time;
if(dflags[3] && (($time-time_read_begin) < `TRR))
$display("I8251A (%h) at %d: *** read pulse width =
violation",
instance_id, =
$time);
end
/* Timing violation: address (comdat_ and chipsel_) must be =
stable */
/* stable throughout read =
*/
task read_address_watch;
@(comdat_ or chipsel_) // if the "address" changes
if (read_=3D=3D0) // and read_ did not change at the =
same time
if (dflags[3])
$display("I8251A (%h) at %d: *** address hold error =
on read",
instance_id, =
$time);
endtask
/** Timing analysis for write cycles **/
=20
always @(negedge write_)=20
if (chipsel_=3D=3D0)
begin
time_write_begin=3D$time;
write_address_watch;
end
/* Timing violation: read pulse must be TRR ns */
/* Timing violation: TDW ns bus setup time before posedge write_ =
*/
/* Timing violation: TWD ns bus hold time after posedge write_ =
*/
always @(posedge write_)
if (chipsel_=3D=3D0)
begin
disable write_address_watch;
time_write_end=3D$time;
if(dflags[3] && (($time-time_write_begin) < `TWW))
$display("I8251A (%h) at %d: *** write pulse width =
violation",
instance_id, =
$time);
if(dflags[3] && (($time-time_dbus_setup) < `TDW))
$display("I8251A (%h) at %d: *** data setup violation on =
write",
instance_id, =
$time);
end
always @dbus
begin
time_dbus_setup=3D$time;
if(dflags[3] && (($time-time_write_end < `TWD)))
$display("I8251A (%h) at %d: *** data hold violation on =
write",
instance_id, =
$time);
end
/* Timing violation: address (comdat_ and chipsel_) must be =
stable */
/* stable throughout write =
*/
task write_address_watch;
@(comdat_ or chipsel_) // if the "address" changes
if (write_=3D=3D0) // and write_ did not change at =
the same time
if (dflags[3])
$display("I8251A (%h) at %d: *** address hold error =
on write",
instance_id, =
$time);
endtask
/* Timing violation: minimum of TRV clk cycles between writes */
always @(negedge write_)
if (chipsel_=3D=3D 0)
begin
time_write_begin=3D$time;
if(dflags[3] && between_write_clks < `TRV)
$display("I8251A (%h) at %d: *** between write recovery =
violation",
instance_id, =
$time);
between_write_clks =3D 0;
end
=20
always @(negedge write_)
repeat (`TRV) @(posedge clk)
between_write_clks =3D between_write_clks + 1;
/** Timing analysis for reset sequence **/
/* Timing violation: reset pulse must be 6 clk cycles */
always @(posedge reset)
begin :reset_block
reset_signal_in=3D1;
repeat(6) @(posedge clk);
reset_signal_in=3D0;
// external reset
-> resete;
end
always @(negedge reset)
begin
if(dflags[3] && (reset_signal_in=3D=3D1))
$display("I8251A (%h) at %d: *** reset pulse too short",
instance_id, =
$time);
disable reset_block;
end
/*** BEHAVIORAL DESCRIPTION ***/
/* Reset sequence */
initial
begin // power-on reset
reset_signal_in=3D0;
->resete;
end
always @resete
begin
if(dflags[5])
$display("I8251A (%h) at %d: performing reset sequence",
instance_id, =
$time);
csel=3D0;
transmitter_reset=3D1;
tdata_out_full=3D0;
tdata_out_wait=3D0;
tdata_hold_full=3D0;
tdata_hold_cts=3D0;
rdatain=3D0;
status=3D4; // only txe is set
txe=3D1;
statusdrv=3D0;
recvdrv=3D0;
txd=3D1; // line at mark state upon reset until data is =
transmitted
// assign not allowed for status, etc.
rxrdy=3D0;
command=3D0;
dtr_=3D1;
rts_=3D1;
status[6]=3D0; // syndet is reset to output low=20
sync_to_transmit=3D1; // transmit sync char #1 when sync are =
transmt'd
sync_to_receive=3D1;
between_write_clks =3D `TRV;
receive_in_progress=3D0;
disable read_address_watch;
disable write_address_watch;
disable trans1;
disable trans2;
disable trans3;
disable trans4;
disable rcv_blk;
disable sync_hunt_blk;
disable double_sync_hunt_blk;
disable parity_sync_hunt_blk;
disable syn_receive_internal;
disable asyn_receive;
disable break_detect_blk;
disable break_delay_blk;
end
always @(negedge read_)=20
if (chipsel_=3D=3D0)
begin
#(`TRD) // time for data to show on the data bus
if (comdat_=3D=3D0) // 8251A DATA =3D=3D> DATA BUS
begin
recvdrv=3D1;
rdatain=3D0; // no receive byte is ready
rxrdy=3D0;
status[1]=3D0;
end
else // 8251A STATUS =3D=3D> DATA BUS
begin
statusdrv=3D1;
if (modreg [1:0] =3D=3D 2'b00) // if sync mode
status[6]=3D0; // reset syndet upon =
status read
// Note: is only reset upon =
reset
// or rxd=3D1 in async =
mode
end
end
always @(posedge read_)
begin
#(`TDF) // data from read stays on the bus after posedge =
read_
recvdrv=3D0;
statusdrv=3D0;
end
always @(negedge write_)
begin
if((chipsel_=3D=3D0) && (comdat_=3D=3D0))
begin
txe=3D0;
status[2]=3D0; // transmitter not empty after receiving data
status[0]=3D0; // transmitter not ready after receiving data
end
end
always @(posedge write_) // read the command/data from the =
CPU
if (chipsel_=3D=3D0)
begin
if (comdat_=3D=3D0) // DATA BUS =3D=3D> 8251A DATA
begin
case (command[0] & ~ cts_)
0: // if it is not clear to send
begin
tdata_hold=3Ddbus;
tdata_hold_full=3D1;// then mark the data as =
received and
tdata_hold_cts=3D0; // that it should be sent =
when cts
end
1: // if it is clear to send ...
if(transmitter_reset) // ... and this is 1st data since =
reset
begin
transmitter_reset=3D0;
tdata_out=3Ddbus;
tdata_out_wait=3D1; // then wait for a negedge on =
txc
tdata_out_full=3D1; // and transmit the data
tdata_hold_full=3D0;
tdata_hold_cts=3D0;
repeat(`TTXRDY) @(posedge clk);
status[0]=3D1; // and set the txrdy =
status bit
end
else // ... and a sync/data char is =
being sent
begin
tdata_hold=3Ddbus; // then mark the data as =
being received
tdata_hold_full=3D1;// and that it should be =
transmitted if
tdata_hold_cts=3D1; // it becomes not cts,
// but do not set the txrdy =
status bit
end
endcase
end
else // DATA BUS =3D=3D> CONTROL
begin
case (csel)
0: // case 0: MODE INSTRUCTION
begin
modreg=3Ddbus;=20
if(modreg[1:0]=3D=3D0) // synchronous mode
begin
csel=3D1;
baudmx=3D1;
tstoptotal=3D0; // no stop bit for synch. op.
end
else
begin // asynchronous mode
csel=3D3;
baudmx=3D1; // 1X baud rate
if(modreg[1:0]=3D=3D2'b10)baudmx=3D16;
if(modreg[1:0]=3D=3D2'b11)baudmx=3D64;
// set up the stop bits in clocks
tstoptotal=3Dbaudmx;
if(modreg[7:6]=3D=3D2'b10)tstoptotal=3D
tstoptotal+baudmx/2;
if(modreg[7:6]=3D=3D2'b11)tstoptotal=3D
tstoptotal+tstoptotal;
end
databits=3Dmodreg[3:2]+5; // bits per char
data_mask=3D255 >> (3-modreg[3:2]);
end
1: // case 1: 1st SYNC CHAR - SYNC MODE
begin
sync1=3Ddbus;=20
/* the syn. character will be adjusted to the most
significant bit to simplify syn. hunt,=20
syncmask is also set to test the top data bits =
*/
case (modreg[3:2])
0:
begin
sync1=3Dsync1<< 3;
syncmask=3D8'b11111000;
end
1:
begin
sync1=3Dsync1<< 2;
syncmask=3D8'b11111100;
end
2:
begin
sync1=3Dsync1<< 1;
syncmask=3D8'b11111110;
end
3:
syncmask=3D8'b11111111;
endcase
if(modreg[7]=3D=3D0)
csel=3D2; // if in double sync char mode, get =
2 syncs
else
csel=3D3; // if in single sync char mode, get =
1 sync
end
2: // case 2: 2nd SYNC CHAR - SYNC MODE
begin
sync2=3Ddbus;
case (modreg[3:2])
0: sync2=3Dsync2<< 3;
1: sync2=3Dsync2<< 2;
2: sync2=3Dsync2<< 1;
endcase
csel=3D3;
end
3: // case 3: COMMAND INSTRUCTION - =
SYNC/ASYNC MODE
begin
status[0]=3D0; // Trick: force delay txrdy pin if =
command[0]=3D1
command=3Ddbus;
dtr_=3D ! command[1];
if(command[3]) // if send break command
assign txd=3D0; // set txd=3D0 =
(ignores/overrides
else // later non-assign =
assignments)
deassign txd;
if(command[4]) status[5:3]=3D0; // Clear =
Frame/Parity/Overrun
rts_=3D ! command[5];
if(command[6]) ->resete; // internal reset
if(modreg[1:0]=3D=3D0 && command[7])
begin // if sync mode and enter =
hunt
disable // disable the sync =
receiver
syn_receive_internal;
disable
syn_receive_external;
receivebuf=3D8'hff; // reset recieve =
buffer 1's
-> start_receiver_e; // restart sync mode =
receiver
end
if(receive_in_progress=3D=3D0)
-> start_receiver_e;
repeat(`TTXRDY) @(posedge clk);
status[0]=3D1;
end
endcase =20
end
end
reg [7:0] serial_data;
reg parity_bit;
always wait (tdata_out_full=3D=3D1)
begin :trans1
if(dflags[1])
$display("I8251A (%h) at %d: transmitting data: %b",
instance_id, $time, tdata_out);
if (tdata_out_wait) // if the data arrived any =
old time
@(negedge txc_); // wait for a negedge on =
txc_
// but if a stop bit was =
just sent
// do not wait
serial_data=3Dtdata_out;
if (tstoptotal !=3D 0) // if async mode ...
begin
txd=3D0; // then send a start =
bit 1st
repeat(baudmx) @(negedge txc_);
end
repeat(databits) // send all start, data bits
begin
txd=3Dserial_data[0];
repeat(baudmx) @(negedge txc_);
serial_data=3Dserial_data>> 1;
end
if (modreg [4]) // if parity is enabled ...
begin
parity_bit=3D ^ (tdata_out & data_mask);
if(modreg[5]=3D=3D0)parity_bit=3D ~parity_bit; // odd parity
txd=3Dparity_bit;
repeat(baudmx) @(negedge txc_); // then send the parity =
bit
end
if(tstoptotal !=3D 0) // if sync mode
begin
txd=3D1; // then send out the =
stop bit(s)
repeat(tstoptotal) @(negedge txc_);
end
tdata_out_full=3D0;// block this routine until data/sync char to =
be sent
// is immediately transferred to tdata_out.
->txende; // decide what data should be sent =
(data/sync/stop bit)
end
event transmit_held_data_e,
transmitter_idle_e;
always @txende // end of transmitted data/sync =
character
begin :trans2
case (command[0] & ~ cts_)
0: // if it is not now cts
// but data was received while it =
was cts
if (tdata_hold_full && tdata_hold_cts)
-> transmit_held_data_e; // then send the data char
else
-> transmitter_idle_e; // else send sync char(s) or 1 stop =
bit
1: // if it is now cts
if (tdata_hold_full) // if a character has been =
received
// but not yet transmitted =
...
-> transmit_held_data_e; // then send the data char
else // else (no character has been =
received)
-> transmitter_idle_e; // send sync char(s) or 1 =
stop bit
endcase
end
always @transmitter_idle_e // if there are no data chars to send =
...
begin :trans3
status[2]=3D1; // mark transmitter as being =
empty
txe=3D1;
if (tstoptotal !=3D 0 || // if async mode or after a =
reset
command[0]=3D=3D0 || cts_=3D=3D1)// or =
TxEnable=3Dfalse or cts_=3Dfalse
begin
if(dflags[1])
$display("I8251A (%h) at %d: transmitting data: 1 (stop =
bit)",
instance_id, =
$time);
txd=3D1; // then send out 1 stop =
bit
tdata_out=3D1; // and make any =
writes
// go to tdata_hold
repeat(baudmx) @(negedge txc_);
-> txende;
end
else // if sync mode
case (sync_to_transmit)
1: // ... send 1st sync char now
begin
tdata_out=3Dsync1 >> (8-databits);
tdata_out_wait=3D0; // without waiting on =
negedge txc
tdata_out_full=3D1;
if(modreg[7]=3D=3D0) // if double sync =
mode
sync_to_transmit=3D2;// send 2nd sync =
after 1st
end
2: // ... send 2nd sync char now
begin
tdata_out=3Dsync2 >> (8-databits);
tdata_out_wait=3D0; // without waiting on =
negedge txc
tdata_out_full=3D1;
sync_to_transmit=3D1; // send 1st sync char =
next
end
endcase
end
always @ transmit_held_data_e // if a character has been =
received
begin :trans4
tdata_out=3Dtdata_hold; // but not transmitted ...
tdata_out_wait=3D0; // then do not wait on =
negedge txc
tdata_out_full=3D1; // and send the char =
immediately
tdata_hold_full=3D0;
repeat(`TTXRDY) @(posedge clk);
status[0]=3D1; // and set the txrdy status =
bit
end
/******************** RECEIVER PORTION OF THE 8251A =
********************/
// data is received at leading edge of the =
clock
event break_detect_e, //
break_delay_e; //
event hunt_sync1_e, // hunt for the 1st sync char
hunt_sync2_e, // hunt for the 2nd sync char (double sync =
mode)
sync_hunted_e, // sync char(s) was found (on a bit aligned =
basis)
external_syndet_watche;// external sync mode: whenever syndet =
pin
// goes high, set the syndet status =
bit
always @start_receiver_e
begin :rcv_blk
receive_in_progress=3D1;
case(modreg[1:0])
2'b00:
if(modreg[6]=3D=3D0) // if internal syndet mode =
...
begin
if(dflags[5])
$display("I8251A (%h) at %d: starting internal sync =
receiver",
instance_id, =
$time);
if(dflags[5] && command[7])
$display("I8251A (%h) at %d: hunting for syncs",
instance_id, =
$time);
if(modreg[7]=3D=3D1) // if enter hunt mode
begin
if(dflags[5])
$display("I8251A (%h) at %d: receiver waiting on =
syndet",
instance_id, =
$time);
-> hunt_sync1_e; // start search for sync =
char(s)
// & wait for syncs to be =
found
@(posedge syndet);
if(dflags[5])
$display("I8251A (%h) at %d: receiver DONE =
waiting on syndet",
instance_id, =
$time);
end
syn_receive_internal; // start sync mode receiver
end
else // if external syndet mode ...
begin
if(dflags[5])
$display("I8251A (%h) at %d: starting external sync =
receiver",
instance_id, =
$time);
if(dflags[5] && command[7])
$display("I8251A (%h) at %d: hunting for syncs",
instance_id, =
$time);
-> external_syndet_watche;// whenever syndet pin goes =
to 1
// set syndet status =
bit
if (command[7]=3D=3D1) // if enter hunt mode
begin :external_syn_hunt_blk
fork
syn_receive_external;// assemble chars while =
waiting
@(posedge syndet) // after rising edge of =
syndet
@(negedge syndet) // wait for falling edge
// before starting char =
assembly
disable external_syn_hunt_blk;
join
end
syn_receive_external; // start external sync mode =
receiver
end
default: // if async mode ...
begin
if(dflags[5])
$display("I8251A (%h) at %d: starting asynchronous =
receiver",
instance_id, =
$time);
-> break_detect_e; // start check for rcd=3D0 =
too long
asyn_receive; // and start async mode =
receiver
end
endcase
end
/**** EXTERNAL SYNCHRONOUS MODE RECEIVE ****/
task syn_receive_external;
forever
begin
repeat(databits) // Whether in hunt mode or not, assemble a =
character
begin
@(posedge rxc_)
receivebuf=3D{rcd, receivebuf[7:1]};
end
get_and_check_parity; // reveive and check parity bit, if any
mark_char_received; // set rxrdy line, if enabled
end
endtask
always @external_syndet_watche
@(posedge rxc_)
status[6]=3D1;
/**** INTERNAL SYNCHRONOUS MODE RECEIVE ****/
/* Hunt for the sync char(s) */
/* (if in synchronous internal sync detect mode) */
/* Syndet is set high when the sync(s) are found */
always @ hunt_sync1_e // search for 1st sync char in the data =
stream
begin :sync_hunt_blk
while(!(((receivebuf ^ sync1) & syncmask)=3D=3D=3D8'b00000000))
begin
@(posedge rxc_)
receivebuf=3D{rcd, receivebuf[7:1]};
end
if(modreg[7]=3D=3D0) // if double sync mode
-> hunt_sync2_e; // check for 2nd sync char directly =
after 1st
else
-> sync_hunted_e; // if single sync mode, sync hunt is =
complete
end
always @ hunt_sync2_e // find the second synchronous character
begin :double_sync_hunt_blk
repeat(databits)
begin
@(posedge rxc_)
receivebuf=3D{rcd, receivebuf[7:1]};
end
if(((receivebuf ^ sync2) & syncmask)=3D=3D=3D8'b00000000)
->sync_hunted_e; // if sync2 followed syn1, sync hunt is =
complete
else
->hunt_sync1_e; // else hunt for sync1 again
// Note: the data stream [sync1 sync1 sync2] will have sync =
detected.
// Suppose sync1=3D11001100:
// then [1100 1100 1100 sync2] will NOT be detected.
// In general: never let a suffix of sync1 also be a prefix of =
sync1.
end
always @ sync_hunted_e
begin :parity_sync_hunt_blk
get_and_check_parity;
status[6]=3D1; // set syndet status bit (sync chars =
detected)
end
task syn_receive_internal;
forever
begin
repeat(databits) // no longer in hunt mode so read entire =
chars and
begin // then look for syncs (instead of on bit =
boundaries)
@(posedge rxc_)
receivebuf=3D{rcd, receivebuf[7:1]};
end
case (sync_to_receive)
2: // if looking for 2nd sync =
char ...
begin
if(((receivebuf ^ sync2)
& syncmask)=3D=3D=3D0)
begin // ... and 2nd sync char is =
found
sync_to_receive=3D1; // then look for 1st sync =
(or data)
status[6]=3D1; // and mark sync =
detected
end
else if(((receivebuf ^ sync1)
& syncmask)=3D=3D=3D0)
begin // ... and 1st sync char is =
found
sync_to_receive=3D2; // then look for 2nd sync =
char
end
end
1: // but if looking for 1st or =
data ...
begin
if(((receivebuf ^ sync1) // ... and 1st sync is found
& syncmask)=3D=3D=3D0)
begin
if(modreg[7]=3D=3D0) // if double sync mode
sync_to_receive=3D2; // look for 2nd sync =
to follow
else // else look for 1st or =
data
status[6]=3D1; // and mark sync =
detected
end
else ; // ... and data was found, do =
nothing
end
endcase
get_and_check_parity; // reveive and check parity bit, if any
mark_char_received;
end
endtask
task get_and_check_parity;
begin
receivebuf=3Dreceivebuf >> (8-databits);
if (modreg[4]=3D=3D1)
begin
@(posedge rxc_)
if((^receivebuf ^ modreg[5] ^ rcd) !=3D 1)
parity_error;
end
end
endtask
task mark_char_received;
begin
if (command[2]=3D=3D1) // if receiving is enabled
begin
rxrdy=3D1;
status[1]=3D1; // set receive ready status bit
if (rdatain=3D=3D1) // if previous data was not read
overrun_error; // overrun error
rdata=3Dreceivebuf; // latch the data
rdatain=3D1; // mark data as not having been =
read
end
if(dflags[2])
$display("I8251A (%h) at %d: received data: %b",
instance_id, $time, =
receivebuf);
end
endtask
/************** ASYNCHRONOUS MODE RECEIVER **************/
/* Check for break detection (rcd low through 2 */
/* receive sequences) in the asynchronous mode. */
always @ break_detect_e
begin :break_detect_blk
#1 /* to be sure break_delay_blk is waiting on break_deley_e
after it triggered break_detect_e */
if(rcd=3D=3D0)
begin
-> break_delay_e;//start + databits + parity + stop bit
breakcount_period =3D 1 + databits + modreg[4] + =
(tstoptotal !=3D 0);
// the number of rxc periods needed for 2 receive =
sequences
breakcount_period =3D 2 * breakcount_period * baudmx;
// If rcd stays low through 2 =
consecutive
// (start,data,parity,stop) sequences =
...
repeat(breakcount_period)
@(posedge rxc_);
status[6]=3D1; // ... then set break detect =
(status[6]) high
end
end
always @break_delay_e
begin : break_delay_blk
@(posedge rcd) // but if rcd goes high during that =
time ...
begin :break_delay_blk
disable break_detect_blk;
status[6]=3D0; // ... then set the break detect low
@(negedge rcd) // and when rcd goes low again ...
-> break_detect_e; // ... start the break detection =
again
end
end
/**** ASYNCHRONOUS MODE RECEIVE TASK ****/
task asyn_receive;
forever
@(negedge rcd) // the receive line went to zero, maybe a start =
bit=20
begin
rbaudcnt =3D baudmx / 2;
if(baudmx=3D=3D1)
rbaudcnt=3D1;
repeat(rbaudcnt) @(posedge rxc_); // after half a bit ...
if (rcd =3D=3D 0) // if it is still a =
start bit
begin
rbaudcnt=3Dbaudmx;
repeat(databits) // receive the data =
bits
begin
repeat(rbaudcnt) @(posedge rxc_);
#1 receivebuf=3D {rcd, receivebuf[7:1]};
end
repeat(rbaudcnt) @(posedge rxc_);
// shift the data to the low part
receivebuf=3Dreceivebuf >> (8-databits);
if (modreg[4]=3D=3D1) // if parity is enabled
begin
if((^receivebuf ^ modreg[5] ^ rcd) !=3D 1)
parity_error; // check for a parity =
error
repeat(rbaudcnt) @(posedge rxc_);
end
#1 if (rcd=3D=3D0) // if middle of stop =
bit is 0
frame_error; // frame error (should =
be 1)
mark_char_received;
end
end
endtask
endmodule
------=_NextPart_000_001E_01C00697.9B4CBDA0--
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