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Hello all, I get pretty confused with Xilinx's low gate-count products and want someone could give some explanations. I use the Virtex and know Virtex/Virtex-E series are for large gate-count applications, but can't really distinguish the use of Spartan/Spartan-II compared to XC4000 series (both are a few K to 20 K devices). Anyone can help? Thanks, - starry.Article: 24501
Laurent Gauch wrote: > "How many registers are required to implement a vending machine?" It depends on the cost of the vending machine products,you just need sufficient F/F's to keep count of the money entered, and maybe a few one-shots to debounce the money sensors, and if you need to make change. Then washing machines have no registers needed for money but a counter (with enable when the lid is closed) to handle the logic. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Octal Computers:Where a step backward is two steps forward!" http://www.jetnet.ab.ca/users/bfranchuk/index.htmlArticle: 24502
Hallo, I designed a board with a Virtex 300, XC18V02 and PCI Logicore. If configure the virtex via JTAG the system works correctly. In Master Serial Mode the FPGA does not start up. 1.) Which settings I need for the BITGEN command (startupclk) ? I have only the PCI clock at GCLK2. 2.) It is possible to program the XC18V02 via JTAG ? Any comments about the suggested solution? Thanks. DI(TU) Thomas Rinder -- Dipl.Ing. Thomas Rinder Meß- und Informationstechnik Universität der Bundeswehr Holstenhofweg 85 D-22043 Hamburg T.: +49 40 65 41 - 3369 F.: +49 40 65 41 - 2743 E-Mail: thomas.rinderNOSPAM@unibw-hamburg.deArticle: 24503
I am using Windows 2000 Professional and the MAX+plus II 9.6 Baseline Software. I want to use it with the El Camino DIGILAB picoMAX. When I try to install the Win2k Byteblaster driver I only get the message: "This location does not contain information about your hardware", "installation failed", respectively. I want to install the driver located in this directory: \maxplus2\Drivers\win2000 Is anyone facing the same problem? Thanks in advance. Alexander PaarArticle: 24504
disk wrote: > > This is the length of the smallest transistor... Actually, its the smallest _gate_ length of the transistors. Please try to read any VLSI or ASIC book that you get. -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 24505
josh_eckstein@my-deja.com wrote: > Can anyone push me to > an informative site so I can stop bugging you? > > Thank you for whatever help you can offer! Take a look at http://www.optimagic.com. I think thats the right start point. -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 24506
Austin Tempany wrote: > > Hi, > Could someone please explain the whole process of Scan Test with reference to ASIC implementation. Sorry, but this would go beyond the scope of this group. Try to read the documentation of your test tool. I could post some scan insertion scripts if you use DC2000.05 > > Apparently during Scan Testing (if the implementation has memory) the memory blocks are bypassed > while the remaining circuitry is Scan Tested. > Scan testing is only capable of testing combinational logic between two FFs. As your memory cell is a blackbox for your test tool, you need to bypass it in test mode to achieve highest test coverage. This would also happen with PLLs or other cells that are in the fanin cone of clk or reset pins of a FF. Hope this helps Patrick -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 24507
Playing around with the Altera software, using schematic entry I ask how can you save your schematic as a graphics image file? I am doing a homebrew cpu and would like to have the schematics on my web page. I can print to postscript printer (and save as file) to get postscript but it would be nice to get a GIF as well. Ben. PS.I still have to find a good generic postscript printer to use. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Octal Computers:Where a step backward is two steps forward!" http://www.jetnet.ab.ca/users/bfranchuk/index.htmlArticle: 24508
> Can the Xilinx router (PAR) be made to run deterministically (i.e. > produce the same exact output for different runs given the same input)? I do not know abnout Xilinx. Altera used to use 2 algorithms, the first to be used If enough RAM was available, the second was slower but used less RAM. Hence you cannot normally ensure repeatability as RAM availability is affected by Virus Checker versions etc. To ensure reproducing a previous result could be risky even if possible. Andrew InceArticle: 24509
Hello Thomas,
Thomas Rinder wrote:
> 1.) Which settings I need for the BITGEN command (startupclk) ? I have only
> the PCI clock at GCLK2.
You must use "-g startupclk:jtagclk" since you want to start the Virtex using
the TCK (JTAG) clock. The process is well described in XAPP139.
> 2.) It is possible to program the XC18V02 via JTAG ?
It is in fact the *only* method to program it...
> Any comments about the suggested solution?
Make sure you use the latest software versions.
Regards,
Étienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 24510Peter Alfke wrote: > > B) Does anyone have any characterization for newer parts they > > can share? > > Unfortunately not. > Two reasons: > The second reason is that this effort has a hard time getting top > priority. And it is hard to argue that metastability measurements should > take precedence over many other activities, like preparing for the > introduction of a new device family. It seems that Xilinx often has issues with "priority" of different activities. To me this is a critical measurement to at least set a floor (or ceiling) to the rate of metastable events. Shouldn't this be a part of the basice characterization data and therefor not have to be argued over in terms of priority? Without this information, it is hard to determine the failure rate of a design. If you could release numbers saying that the metastable rate is better than X then we could at least determine that our device will not fail (on the average) for 100 years even if it is really 10000 years. Without the numbers we can't say it has any maximum failure rate. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24511
Starry Hung wrote: > > Hello all, > > I get pretty confused with Xilinx's low gate-count products and want > someone could give some explanations. I use the Virtex and know > Virtex/Virtex-E series are for large gate-count applications, but can't > really distinguish the use of Spartan/Spartan-II compared to XC4000 > series (both are a few K to 20 K devices). Anyone can help? There is almost no value in counting gates in FPGAs. Gate counts vary depending on many assumptions that the manufacturers make so that you can not use gate counts to compare two manufacturers or even two product lines with the same manufacturer. For Xilinx like devices, you are much better off comparing LUT counts. But even there you will not be able to use the published numbers as Xilinx counts some imaginary LUTs to account for other features in the logic. So count the rows and the columns and multiply. This gives you the CLB count. In the XC4000 and Spartan series multiply by 2 to get a LUT count, in Virtex and Spartan II series multiply by 4 to get the LUT count. The LUT count is a much better measure of size equivalence between different Xilinx families. But do keep in mind that the Virtex and Spartan II lines have block RAM which can be very useful. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24512
"Domagoj" <domagoj@engineer.com> wrote in message news:8mv5mj$f40$1@bagan.srce.hr... > > What about the Automatic replacement of internal Tristates available in > > Synthesis tools.? > > Had no idea about that possiblity.. :) > Which tools can do that ? Leonardo says it can, but I have not tested it.Article: 24513
> In Master Serial Mode the FPGA does not start up. > > 1.) Which settings I need for the BITGEN command (startupclk) ? I have only > the PCI clock at GCLK2. When using the SPROM to configure the FPGA you need to use: -g StartupClk:CCLK in the command line for the bitgen program. You must program the SPROM with a bit file done with this option, or it will not work. Also, do not use fast clock, just use the slow default clock speed. > 2.) It is possible to program the XC18V02 via JTAG ? Yes. How did you program the SPROM for Master Serial Mode if not via JTAG? > Any comments about the suggested solution? There are a LOT of issues with hooking up the FPGA to the SPROM. There were also issues with programming the earlier masks of the SPROMs, so if you can't get it programmed via JTAG, perhaps you ought to look at what the date code is. Some people have it working by magic (pure dumb luck), some actually follow the spec (which has some inaccuracies too). I suggest hooking it up as follows: FPGA SPROM -------------------------------------- CCLK CLK PROG_N CF_N INIT_N OE/RESET_N DONE CE_N You should have a 4.75k pullup on PROG_N and INIT_N, and a 330 ohm pullup on DONE. It is also suggested you put an 82 ohm pulldown on CCLK. MAKE SURE THE SPROM IS THE FIRST DEVICE IN THE JTAG CHAIN...this is a bug in the SPROM, and you will not be able to program the SPROM if you put the FPGA first in the JTAG chain. I also recommend a 33 ohm resistor on the output of CCLK from the Master FPGA. Though CCLK is a slow clock, it has a VERY fast edge rate...in the sub-nanosecond range. One knee on CCLK and you will not get your FPGA configured correctly. Also, treat it as a clock net, and route it with no Ts or Ys. This 'problem' mostly shows up in systems with multiple FPGAs receiving CCLK...and a poorly routed CCLK. Probably not necessary for your single FPGA implementation.Article: 24514
hi
I am trying to sythesize a design with Leonardo Spectrum but I have
problems with the clock buffers and the DLL.
When I do not explicitly use clock buffers (only the DLL), ngdbuild
gives me a warning (something like "you should use a BUFG for your clock
signal") and then the mapper complains that the DLL cannot be driven by
an IPAD (Leonardo automatically put a IPAD)
So I tried to explicitly instantiate clock buffers but then ngdbuild
complains that a clock signal (called pciclk_int) has multiple drivers
and an illegal connection.
Any idea? I'm desperate...
(anyone at Exemplar: I am evaluating Leonardo. Help me or I won't buy
;o)
Sample code (Verilog) :
module inv_clk
(pciclk, bpciclk, nclk, rst);
input pciclk;
input rst;
output nclk;
output bpciclk;
wire neg_clk;
wire pciclk0;
wire iclk;
CLKDLL dll0 (
.CLKIN (iclk),
.CLKFB (bpciclk),
.RST (rst),
.CLK0 (pciclk0),
.CLK180 (neg_clk));
IBUFG clk_buf (
.I(pciclk),
.O(iclk));
BUFG neg_bufg (
.I(neg_clk),
.O(nclk));
BUFG pos_bufg (
.I(pciclk0),
.O(bpciclk));
endmodule
--
Nicolas MATRINGE DotCom S.A.
Conception electronique 16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE
Fax +33 1 46 67 51 01 http://www.dotcom.fr/
Article: 24515Or maybe, "How many registers are required to implement a vending machine?" Andy Peters a écrit : > yshamir wrote in message <040d9897.1cdefc39@usw-ex0104-031.remarq.com>... > >Hi Guys > >I will be attending interview for ASIC designer position. > >Can someone tell me what sort of technical questions are asked. > >Tricky questions etc . > > "How many registers are required to implement a vending machine?" > > -- > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "A sufficiently advanced technology is indistinguishable from magic" > --Arthur C. ClarkeArticle: 24516
Thanks Peter. I suspect the problem is in the bit file generated. This is the log file BOX.BGN at the end. It mentions a possible warning about the STARTUP and the CCLK. I don't understand what it means. Could you explain its meaning and a possible fix? I'm using an external 8 MHz clock that is divided into a 2 MHz clock inside the chip. This clock signal is connected to the STARTUP and all other flipflops, etc. The external 8 MHz clock is used only to clock the 2-bit clock divider. Another possibility is that my XCHECKER.EXE program might be too old to program the chip? I'm using a DOS version 5.2.0. I haven't been able to find a more recent version. If you know where I can find it, (DOS or UNIX) that would be great. This is the log file: ---------------------------- Loading device database for application Bitgen from file "box.ncd". "box" is an NCD, version 2.27, device xc4010e, package pg191, speed -4 Loading device for application Bitgen from file '4010e.nph' in environment C:/fndtn. Opened constraints file box.pcf. BITGEN: Xilinx Bitstream Generator M1.5.25 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Fri Jul 21 13:13:47 2000 bitgen -l -w -g ConfigRate:SLOW -g TdoPin:PULLNONE -g M1Pin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no -g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 -g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable -g M0Pin:PULLNONE -g M2Pin:PULLNONE box.ncd WARNING:x4kbs:36 - There is a STARTUP component with a signal on the CLK pin but StartupClk is Cclk. Running DRC. DRC detected 0 errors and 0 warnings. Saving ll file in "box.ll". Creating bit map... Saving bit stream in "box.bit".Article: 24517
Thanks to Altera phone support it works now. The Byteblaster driver must be installed as a multimedia device and not as as parallel port driver. That 's all... > I am using Windows 2000 Professional and > the MAX+plus II 9.6 Baseline Software. > > I want to use it with the El Camino DIGILAB picoMAX. > > When I try to install the Win2k Byteblaster driver > I only get the message: > "This location does not contain information about > your hardware", "installation failed", respectively. > > I want to install the driver located in this directory: > \maxplus2\Drivers\win2000 > > Is anyone facing the same problem? > > Thanks in advance. > > Alexander Paar >Article: 24518
On Thu, 10 Aug 2000 11:31:09 -0400, "B. Joshua Rosen" <bjrosen@polybus.com> wrote: >The Xilinx on Linux howto has been updated. There are new scripts which >handle the changes in Wine that were introduced in June. > >http://www.polybus.com/xilinx_on_linux.html Update for your web page: Synplify is now beta'ing on Linux. EvanArticle: 24519
On Thu, 10 Aug 2000 19:44:36 GMT, Don Frevele <dfrevele@hotmail.com> wrote: >Can the Xilinx router (PAR) be made to run deterministically (i.e. >produce the same exact output for different runs given the same input)? > >I'm asking because my bosses want to make the release procedure of >hardware design similar to that used for software designs. For software >they copy the source files to a temp directory, run the build procedure >and then compare the outputs (object file) between this build and what >they are releasing. >The equivalent for hardware would be start with the VHDL code and >compare the bitsteam files. I don't that the VHDL tools would be any >problem, but I know the Xilinx PAR is not deterministic. > >Long,long ago APR used a random seed, which you could feed back for >subsequent runs, but I don't see that anymore. > >How about using a guide file? Would feeding the released ncd as a guide >file force PAR to produce the same route given the same input? This is exactly what I do. The only inputs to the rebuild are the VHDL sources, any coregen EDIFs, the UCF, the bitgen option files, and a makefile. In the tests I've done, the bitstreams have been identical. Of course, you also have to make sure you archive all your tools. I haven't tested with a guidefile, but I don't think there'd be a problem. This process is pretty much essential for any meaningful maintenance. You could possibly have a problem with your synth, which may use a random seed. I've only used Spectrum in the rebuild flow, without problems. I believe that Synopsys calculates a seed based on the contents of the source, so that should work as well. EvanArticle: 24520
On Thu, 10 Aug 2000 20:18:20 GMT, Greg Neff <gregneff@my-deja.com> wrote: [...] > >Your build configuration should include: > >1) Schematics and/or HDL source > >2) Schematic part and/or HDL libraries > >3) All files generated by schematic/HDL/Xilinx tools > >4) Xilinx software CDs > >5) Xilinx executeable service packs > >6) Xilinx device speed and package files > >7) Xilinx Command History (from Design Manager utilities menu, select >command line option) > Or, instead of (7) (which implies that the Design Manager was used), use a decent Makefile. I can't imagine any reproducible results with all those fancy GUI stuff. Please, Altera and Xilinx, never give up the command line interface to your tools. chm. -- cmautner@ - Christian Mautner mail.com - Vienna/Austria/EuropeArticle: 24521
On Thu, 10 Aug 2000 01:06:46 GMT, bingoeugene@my-deja.com wrote: >Reliable and cost effective replacement solution for the Altera [...] (ad deleted) Technical question: What serial resistors are used on the interface? I'm asking because the original byteblaster uses quite high values (100 Ohm?), which can lead to a very long rise time on the TCK which cost me two days of debugging some weeks ago, 'cause my ACEX did not boot. No, I will not go into lamenting about posting commertials into this newsgroup. chm. -- cmautner@ - Christian Mautner mail.com - Vienna/Austria/EuropeArticle: 24522
In article <3992E3B0.CC640280@cern.ch> Jean-Marie Bussat <bussat_NOSPAM_@cern.ch> writes: >From: Jean-Marie Bussat <bussat_NOSPAM_@cern.ch> >Subject: Viewlogic to Orcad conversion >Date: Thu, 10 Aug 2000 19:17:36 +0200 >Hello, >The files to convert are from the xproz project and are in the >following zip archive. >ftp://137.193.64.130/pub/xproz/xproz.zip >I would like to understand how they made their system and since >the documentation is in german (and doesn't include schematics), Sorry, I added the PostScript prints of the schematics to the PS version of the documentionen already 5 years ago, but somehow it didn't find its way to the ftp-server. I converted it now to pdf format (including the schematics). You will find it at ftp://137.193.64.130/pub/xproz/xproz.pdfArticle: 24523
This is a multi-part message in MIME format. --------------3F2478126D6B0B80B7F21A2B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit --------------3F2478126D6B0B80B7F21A2B Content-Type: text/x-vcard; charset=us-ascii; name="jeff.carter.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jeff Carter Content-Disposition: attachment; filename="jeff.carter.vcf" begin:vcard n:Carter;Jeff tel;work:408.879.6961 x-mozilla-html:FALSE url:http://www.xilinx.com org:Xilinx Inc;W2C web | workflow | collaboration adr:;;2100 Logic Drive;San Jose;CA;95124; version:2.1 email;internet:jeff.carter@xilinx.com title:Sr. Information Systems Analyst fn:Jeff Carter end:vcard --------------3F2478126D6B0B80B7F21A2B--Article: 24524
Hi, I'm using the Xilinx Foundation 2.1 software and coding in VHDL for a 5210 FPGA. I was wondering if there is (or is there supposed to be) any difference in terms of delay/switching times between using a buffer vs. an and gate. For example: Buffer: A <= B when en = '1' else 'Z'; AND: A <= B and en; Also, will this use a buffer, or an AND gate (or something else)? A <= B when en='1' else '0'; Thanks. (BTW, anybody have advice on some good web sites with VHDL syntax tricks and/or sample code?)
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