Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Gabor, In the DCM status, there is the "clock lost" bit. For the CLKFX, there is also the "clock stopped" bit. The DCM is a digital synchronous state machine, so loss of input clock means that the lock bit, which is a state, will never change. These other two status bits are there to tell you what happened (provide more information). Good post, AustinArticle: 109151
http://www.xilinx.com/support/services/contact_info.htm AustinArticle: 109152
Karl, Does that mean you will not use Virtex 5? AustinArticle: 109153
I would like to evaluate the true performance of the various CPU cores available for FPGAs and I found that the "economy" version of the NIOS core uses a minimum of 6 clock cycles to complete an instruction! I guess they use the same division of logic and registers for all their cores, but change how they run in parallel. In fact, the smallest "economy" version runs at highest clock rate. But if you divide that by 6 to be an instruction rate, you only get about 33 MHz "true" performance. I guess that is why the DMIPS is only 31 vs. 218 for the "performance" version. How are DMIPS measured for a core? Is this done by measuring a benchmark program? It can be hard to collect all the necessary data for comparing the various cores available. This is especially true for the open-source versions. There are quite a number of cores available at opencores.org, but most do not provide any real data on their capabilities. Antti mentioned in a post that there are three NIOS clones and I found one MB clone at opencores.org. Where are the NIOS clones hiding and are there any other MB clones? Has anyone collected data on their speeds and sizes?Article: 109154
On Thu, 21 Sep 2006 10:23:25 +0200, Michael Schöberl <MSchoeberl@mailtonne.de> wrote: > >the PC market is changing quite fast and I would like to >get an update on the question from July ... > >back then I heard >- "Athlon 64 1M cache" is faster than Pentium 4 >- "Core 2 duo 4M cache" might be even better > > >Intel Core 2 is available and I would like to >know if anyone did really test it? does it help? > > >I heard an announcement of "Core 2 Quadro" but I guess >this is quite useless with Xilinx ISE? > > >bye, >Michael The only info I have on core2duo by someone who is doing actual development (porting/compiling firefox) is that for compiles & links it's worse than his athlon 64 machine. I don't know anyone who has run ise or synplicity on a core2duo yet. http://www.investorshub.com/boards/read_msg.asp?message_id=13431784Article: 109155
> How are DMIPS measured for a core? Is this done by measuring a > benchmark program? DMIPS usually referes to Dhrystone MIPS. Where Dhrystone is a very old and broken benchmark program. You can read why it is broken here: http://www.arm.com/pdfs/Dhrystone.pdf Cheers, JonArticle: 109156
> - "Core 2 duo 4M cache" might be even better I just bought one of these. Bloody quick. Sped up my P&R 4x compared to the Pentium 4 I was using. Well worth the money. Cheers, JonArticle: 109157
Austin Lesea wrote: > Karl, > > Does that mean you will not use Virtex 5? It might sound silly, but sometimes that is all it takes.. (Especially if the process is not fully automated, but I don't know whether that is the case here). Cheers, JonArticle: 109158
On 21 Sep 2006 08:52:34 -0700, "Jon Beniston" <jon@beniston.com> wrote: >> - "Core 2 duo 4M cache" might be even better > >I just bought one of these. Bloody quick. Sped up my P&R 4x compared to >the Pentium 4 I was using. Well worth the money. Could you give some spec, memory, cpu frequency on both machines?Article: 109159
We are only interested in serious designers, not just "tire-kickers". The registration is not a hurdle if you are serious. BTW: In this case, the errata are really trivial: a register that must be reset a special way, a reduced max frequency in synchronous FIFO mode, a missing optional clock inversion somewhere... "Early Silicon" is my interpretation of ES. To call it "Engineering Samples" would be misleading. These are full-quality, fully tested and characterized parts that work over temperature and voltage ranges. This is Early Silicon, and any design error (and there often is, since nobody is perfect the first time around) it is described on an errata sheet. By definition, every ES device has an errata sheet; at best the sheet just says: No errata! The errata will be fixed in the production (non-ES) version. That's why we suggest that you avoid, if you can, shipping our ES parts in your production equipment. Saves you some logistic confusion. We are excited that the Virtex-5 parts came out so clean, and with good manufacturing yield. That's why I took the unusual (controversial?) step of advertising availability in this newsgroup. Maybe I can help to reduce the usual design-in delay, to your and to our benefit. Peter Alfke, Xilinx ====================== Jon Beniston wrote: > Austin Lesea wrote: > > Karl, > > > > Does that mean you will not use Virtex 5? > > It might sound silly, but sometimes that is all it takes.. (Especially > if the process is not fully automated, but I don't know whether that is > the case here). > > Cheers, > JonArticle: 109160
David Ashley <dash@nowhere.net.dont.email.me> wrote: >Nico Coesel wrote: >> As AFAIK the opencores ddr controller uses some sort of scheme which >> routes the clock to the outside and pulls it back in again. This is >> totally unnecessary IMHO. > >Yep you're right, that was the feedback line for one of the DCM's. >Current design works but has no feedback from the outside as >you suggest. Original design was right on the edge as regards >sampling the DDR's output data. > >> For the DDR you'll need 2 DCMs: 1 to turn 50MHz into 100MHz and 1 to >> get a clock which is 90 degrees out of phase. fddrs have an internal >> inverter in their clock inputs so 1 clock to drive these is >> sufficient. > >You're exactly right. Also DCM -> DCM seems to work ok, however >I'm ignoring the "locked" bit on the 50->100 DCM and the system >only pays attention to the locked bit on the 2nd DCM. This is >probably bad. By the way, there is a Spartan3 issue with daisy chaining DCMs. See the other thread about 'product lifetime'. ISE 7.1 (dunno about the other ISE versions) will warn you about this when routing the design. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 109161
jerzy.zielinski wrote: > Hi, > > I wanted to deal with interrupts in Microblaze project. I would like to > procesor react to int from swich or a button sending a led blik on > GPIO. Can someone tell me how to do it. > Create a MicroBlaze + GPIO (w/ interrupts) design using BSB. It will create a TestApp_Peripheral s/w project which does exactly what you want. /SivaArticle: 109162
Hi, I've designed a PowerPC C++ Application (as standalone configuration) that communicates with an custom peripheral. The custom peripheral, simply counts up a std_logic_vector until it reaches the decimal value 100. This increment is done every clock cycle, the design is made up as an FSM. Now I send a start signal to the peripheral, the peripheral starts counting. The PowerPC now waits for the peripheral, that sends a "ready" signal, indicating that it puts the first increment to the output register. Now I want to read every clock cycle from this output register, so that the powerPC gets something like (1,2,3...,100) as input from the peripheral. Therefore the PowerPC waits for the ready signal and then continously reads the output register. Unfortunately, all I get as an input from the peripheral is the last value of the counting :( The peripheral is connected via the OPB bus to the PowerPC, I've learned that this Bus runs at 100 Mhz when configuring the PowerPC to run at 300 Mhz. The clock of the peripheral is connected to the sys_clk_s. I expect that the PowerPC reads data much faster from the Bus than the peripheral writes them onto the bus. I even build up a clock divider, slowing down the peripheral to sys_clk_s/4 but all I get is the last value. What is missing in my configuration or do you have an assumption what I am doing wrong? Any help is highly appreciated, regards PeterArticle: 109163
Brian Davis wrote: > Have a look at Answer Record 11778 Thanks, that took care of #1. SteveArticle: 109164
The OpenFire is an open source (MIT license) MB clone available from here: http://www.ccm.ece.vt.edu/~scraven/openfire.html It has several serious limitations that I have yet to address, including the lack of a usable interface other than FSL. And that is why it isn't yet available on OpenCores. However, it achieves 58 DMIPs at 100 MHz using somewhere between 500 and 600 slices, IIRC, on a 2VP-6. An aging but good comparison of the MB, Leon, and OpenRISC soft cores can be found here: http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf > Antti mentioned in a post that there are three NIOS clones and I found > one MB clone at opencores.org. Where are the NIOS clones hiding and > are there any other MB clones? Has anyone collected data on their > speeds and sizes?Article: 109165
Antti wrote: >>port or thought of doing one? Conversely if someone wants >>a uclinux port to plasma I'll do it for $$$. :) >... > how much $$$ are we talking about? > I am looking for open-source core with uclinux, but OR1K is too large > > Antti BTW this discussion moved to email, discussions of money are somewhat delicate... -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109166
stephen.craven@gmail.com wrote: > The OpenFire is an open source (MIT license) MB clone available from > here: > http://www.ccm.ece.vt.edu/~scraven/openfire.html > > It has several serious limitations that I have yet to address, > including the lack of a usable interface other than FSL. And that is > why it isn't yet available on OpenCores. FSL = Fast Simplex Link? Is this a xilinx proprietary interface? I'm trying to understand why it can't be on opencores. Openfire, is related to 68000 or the coldfire? -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109167
David Ashley wrote: > stephen.craven@gmail.com wrote: > >>The OpenFire is an open source (MIT license) MB clone available from >>here: >>http://www.ccm.ece.vt.edu/~scraven/openfire.html >> >>It has several serious limitations that I have yet to address, >>including the lack of a usable interface other than FSL. And that is >>why it isn't yet available on OpenCores. > > > FSL = Fast Simplex Link? Is this a xilinx proprietary interface? > I'm trying to understand why it can't be on opencores. > > Openfire, is related to 68000 or the coldfire? > > -Dave Sorry, it's a verilog microblaze clone. I'm still struggling with vhdl, don't want to mess with verilog yet, but that's just me. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109168
Jack, If I understand you correctly, you are saying that some internal signals that you expect to be at certain chip IO are not there. I've had problems like that before when signals were NOT asigned in the ucf file. If that is the case, Xilinx will randomly assign these signals for you. I believe the assignment will change at each place and route based on internal logic used. Check your .ucf file. Good luck. Ira- Jack Zkcmbcyk wrote: > Hi! > > I have been working on a design lately where I use a the Xilinx Spartan > 3E starter kit board. I use a logic analyser to check the output on some > signals which are assigned to the boards' J1, J2 and J4 connectors. > Sometimes, I get some of the signals to not even be "connected" on the > external pins. When this happens, I find that going in to the VHDL code and > adding a few changes that are usually never related to the signals I want to > observe in the first palce, fix things for me. > > Lately, I have tried verifying the FPGA after downloading a newly > generated configuration to it. The verification came back with 3076 errors. > When I look at the logic analyser trace, it seems to provide "most" of the > signals except for one one that should be there but it is not. > > Is there a way to obtain more info as to why thee would be so many > errors during the programming of an FPGA? Are there some settings I may not > be using correctly in the tool that causes the recompile to not be as clean > as I think it should? Does the verification process pick up noise on te > programming cable (I use the USB cable in this case)? Could the FPGA be > damaged (static perhaps)? > > I guess I am curious as to why this is happening. Most of the time > things seem to work fine, but on the odd compile, something disapears. > > Thanks for any help/hints. > >Article: 109169
"Peter Alfke" <peter@xilinx.com> wrote:
>You can order Virtex-5 devices from your distributor now, and he will
>offer short delivery times.
>Whether the distributor carries these parts on his shelves is entirely
>his business decision, but he can always get them for you from Xilinx
>at short notice. ("4 to 6 weeks" seems to be the standard answer, but
>don't be surprised if it is much faster.)
>Available from inventory here at Xilinx are nine part / package
>combinations, eighteen if you count the leaded/lead-free versions:
>
>XC5VLX30-1FF(G)324C and -676C
>XC5VLX50-1FF(G)324C and -676C and -1153C
>XC5VLX85-1FF(G)676C and -1153C
>XC5VLX110-1FF(G)676C and -1153C
>
>LX is the logic-oriented sub-family, with BlockRAMs and DSP slices, but
>without multi-gigabit transceivers. See the data sheet on the Xilinx
>website.
>The 30 to 110 is a proportional indicator of logic density (thousands
>of "equivalent Logic Cells")
>The -1 stands for the slowest speed grade (the only one available this
>early)
>The FF stands for flip-chip ball-grid array, the one way we package all
>Virtex-5 family devices
>The G stands for "green" = lead-free packages which are all available
>right now.
>
>We have found over the years that small-volume users and consultants
>often are the most enthusiastic early adopters, but they may not always
>be sure about instant availability.
>Now you know !
>More parts to come very soon.
>
>Peter Alfke, who has been working on and with these parts for over a
>year.
How about some budgetary prices for low volumes? I'm Dutch so my first
question is always: "How much does it cost?".
--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
Article: 109170
Jon Beniston wrote:
> > but it uses verilog at such advanced level that is not supported
> > by Xilinx XST synthesis, e.g. it is only useable with Synplify
> > as synthesis tool
>
> It's about time Xilinx had full Verilog 2001 support really. What year
> is it?
>
> Still, on the plus side, if you do use Synplify, at least the rest of
> your design might work too ;-)
>
> Cheers,
> Jon
In fairness, the verilog2001 support is not the issue.
The main reason the source did not compile was XST's adherence to some
rules, like naming generate statement begin blocks, etc, and an issue
with using clogb2 in a parameter.
All small issues really - few tweaks here and there, took me a half an
hour to do, and it synthesized!
This was for a (very) basic configuration, I just tried to synth this
to the slowest speed grade V5,
Number of Slice Registers: 780
Number of Slice LUTs: 1174
Number used as Logic: 1046
Number used as Memory: 128
Number used as RAM: 128
and it came out at 170MHz (post synth timing only - did not run PAR).
Would be Interesting to see if it works, and with more features turned
on..though I have no time to test it..
But XST can do it - with relatively small amount of code massaging.
Article: 109171I cannot get the MIG to work in Core Generator. I've written Xilinx, but hope I can get a faster answer here. I used the Tools->Updates Installer in coregen to install MIG. Help->About now says I have IP updates 1 and MIG 1.6 installed. It also says I have MIG 1.5 installed. Xilinx says to list available cores by function, select Memories&Storage Elements, then select MIG. However MIG simply does not appear as an option. Does anyone have any idea why the insallation (apparantly) failed? I am running under Fedora 4, and using ISE 8.1 sp 3. Thanks kjhalesArticle: 109172
viswanathank@gmail.com wrote: > Hi, > You wont have to insert any sync circuits to the 2X clock domain unless > this domain is sampling signals in the 1X domain as well. The DCM > should take care of all the syncing with respect to the 1X domain > (thats what the DCM is there for). If the 2X domain samples signals in > the 1X domain ( and there is no handshaking between the domains) then > you may have to use a double sync ( two back to back DFF ). > > Anonymous via the Cypherpunks Tonga Remailer wrote: > >>Hi, >> >>I have a question regarding Xilinx DCM. If a clock signal >>is generated by DCM (say 2X) and used to drive >>another clock domain. Is the new domain still >>"synchronized" with the original clock domains? >>Do I need to insert synchronization circuit >>when a signal crossing form 1X domain to 2X domain >>and vice versa? >> >>Thank you in advance. >> >>Will G. > > In a perfect world, yes, they are aligned. However, if you have clock jitter on the clock going into the DCM, it is possible for the edges to lose alignment, at least on the older CLK_DLLs. I got bitten badly on that when Xilinx first introduced the Virtex line...they assured me that the clocks were aligned, but as it turned out, clock jitter at the DLL input can cause misalignment beyond the alignment spec. In my case we were seeing a large misalignment of several hundred ps, enough to make the design fail. It turned out that jitter was getting introduced onto the clock by a bunch of outputs switching on the same bank as the single-ended clock input, and that jitter was in turn causing the 1x and 2x outputs to go out of alignment. The moral of the story is, be careful and conservative in your design.Article: 109173
> In fairness, the verilog2001 support is not the issue. > The main reason the source did not compile ... and an issue > with using clogb2 in a parameter. Is this not a Verilog 2001 feature that isn't supported? Cheers, JonArticle: 109174
Have you modified timing constraints in the UCF file to match your increased clock speeds? /Mikhail
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z