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Amazing project :)))Article: 157726
Here's an addendum. The style above only works for a 7-input mux, not a 5-input. For less than 7 inputs, Vivado still omits the F7. Here's the Vivado kludge:
wire [7:0] mux_inputs[0:4]; // only 5 inputs
wire [7:0] mux_out;
wire [2:0] mux_sel;
(*keep="true"*) wire [2:0] dummy_x[5:7];
assign dummy_x[5] = 3'bx;
assign dummy_x[6] = 3'bx;
assign dummy_x[7] = 3'bx;
always@(posedge clk)
if (mux_sel<5)
mux_out <= mux_inputs[mux_sel];
else
mux_out <= dummy_x[mux_sel];
After synthesis, Vivado uses extra LUTs to implement the KEEP dummy wires, but then it removes these in PAR.
This whole thing is ridiculous, but this is how you get Vivado to do what it's supposed to do.
Article: 157727
Nah, that doesn't always work either. This seems to work more consistently:
(*keep="true"*) wire [7:0] mux_inputs[0:7]; // only 5 inputs used
wire [7:0] mux_out;
wire [2:0] mux_sel;
// Assign unused mux inputs to 'bx so there are exactly 2^n inputs
assign mux_inputs[5] = 'bx;
assign mux_inputs[6] = 'bx;
assign mux_inputs[7] = 'bx;
always@(posedge clk)
mux_out <= mux_inputs[mux_sel];
Article: 157728Looking for someone to work on a project. Quick Notes 1. PCI FGPA Card (standard off the shelf is possible) 2. Interface to decryption engine 3. Multiple decryption engines, as many as the FPGA will allow, and parallel decoding email joolzg@btinternet.com for more info joolz -- --------------------------------- --- -- - Posted with NewsLeecher v6.5 Beta 4 Web @ http://www.newsleecher.com/?usenet ------------------- ----- ---- -- -Article: 157729
>Looking for someone to work on a project. > >Quick Notes > >1. PCI FGPA Card (standard off the shelf is possible) >2. Interface to decryption engine >3. Multiple decryption engines, as many as the FPGA will allow, and parallel >decoding > >email joolzg@btinternet.com for more info > >joolz > >------------------- ----- ---- -- - Does this project violate the DCMA? John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 157730
On 2/23/2015 1:03 PM, jt_eaton wrote: >> Looking for someone to work on a project. >> >> Quick Notes >> >> 1. PCI FGPA Card (standard off the shelf is possible) >> 2. Interface to decryption engine >> 3. Multiple decryption engines, as many as the FPGA will allow, and > parallel >> decoding >> >> email joolzg@btinternet.com for more info >> >> joolz >> >> ------------------- ----- ---- -- - > > Does this project violate the DCMA? I think if you look hard enough, *every* project violates the DMCA. Heck, reading the DCMA on the Internet probably violates the DMCA. -- RickArticle: 157731
In reply to "jt_eaton" who wrote the following: > > Looking for someone to work on a project. > > > > Quick Notes > > > > 1. PCI FGPA Card (standard off the shelf is possible) > > 2. Interface to decryption engine > > 3. Multiple decryption engines, as many as the FPGA will allow, and parallel > > decoding > > > > email joolzg@btinternet.com for more info > > > > joolz > > > > ------------------- ----- ---- -- - > > Does this project violate the DCMA? > > > John Eaton > > > > > --------------------------------------- > Posted through http://www.FPGARelated.com DCMA, a US law so NO joolz -- --------------------------------- --- -- - Posted with NewsLeecher v6.5 Beta 4 Web @ http://www.newsleecher.com/?usenet ------------------- ----- ---- -- -Article: 157732
Hi Jim, glen, JK, rickman, Mike, Andy,=20
I have filed a provisional patent application: "Systematic method of coding=
wave pipelined circuits in HDL". If it is proved correct, the patent will =
introduce 1 keyword, 3 permanent constants, 1 concurrent statement and four=
source code modules for a new library in HDL and thoroughly resolve a pend=
ing problem so that every digital designer can code wave-pipelined circuits=
in HDL.=20
Here is the abstract of the invention:=20
The present invention classifies all critical paths into two basic type=
s: a series critical path and a feedback critical path, and divides each of=
wave-pipelined circuits into two components: a static logic part, called c=
ritical path component (CPC), and a dynamic logic part, formalized into fou=
r wave-pipelining components (WPC) shared by all wave-pipelined circuits. E=
ach wave-pipelining ready code in HDL comprises two components: a WPC insta=
ntiation and a CPC instantiation wire-connected and linked by a new link st=
atement. Each WPC has new wave constants which play the same role as generi=
c constants do, but whose initial values are determined and assigned by a s=
ynthesizer after code analysis, so designers can use after-synthesization i=
nformation in their code before synthesization for wave-pipelining technolo=
gy. The responsibility of analyzing and manipulating wave-pipelining ready =
code, generating and implementing wave-pipelined circuits on a design-wide =
or chip-wide scale in HDL is shifted from designers to synthesizers.=20
Anyone who are interested in its content is welcome to send a email request=
to the following email address: wtx wtx @ gmail . com with title "Systemat=
ic" and he will receive the full documents: one specification, 9 drawings a=
nd one text file in VHDL.=20
If one reviews the files and feels that it would be a good thing to recomme=
nd the application to his company to buy it, the first person to do it afte=
r his recommended company does so will receive $10,000 commission fee.=20
All people who are interested in the topics are better to refer the same to=
pics in VHDL group, because its example source code is in VHDL and it canno=
t not be implemented in any FPGA chip.
https://groups.google.com/forum/#!forum/comp.lang.vhdl
Thank you.=20
Weng=20
Article: 157733Hi There, From time to time I see people having Altera CPLDs on the "JTAG Lockout" st= atus. I have a few EPM7128s on this state myself. I wonder how difficult would it be to create an "eraser/unlocker". I know t= his process can be done by the Master Programmers, but they are clumsy, com= plex, impossible to find on eBay, incompatible with Windows 7/8 and/or USB,= and VERY VERY expensive. What I am thinking about would be something simpler, which would imitate th= e signals sent by the Master Programmer to erase the chip (thus freeing the= JTAG pins for reprogramming). From that moment on, JTAG would be used to do the programming. Have anyone ever seen something like this? Tried something like this? Succe= eded? Have anyone ever seen the algorithm used by the master programmers? THere has to be some information out there, as programmers from other vendo= rs than Altera are able to unlock the chips. This is definitely something that would sell out on eBay I guess. I see the (magic) GQ-4X USB programmer does program Alteras (still using JT= AG, though), and it has an adapters for the CPLDs (ADP-095, ADP-096 and ADP= -097). If its driver could be modified to send such signals, then we alread= y have the hardware, no need to build one. Yes? No? Anyone? Cheers, Marcelo.Article: 157734
Hi guys,
I'm not sure this is the right place to ask this question, but I found no
answers to it on xilinx forums. Hope you can help me!
intro:
I work with atlys board. using Microblaze processor. Using xilinx EDK and
SDK as tools.
For an image processing purpose, I designed a custom coprocessor with FSL
bus, which gets a (4,4) pixel window of an image from microblaze and
applies a filter on it ,then sends it back to microblaze.I iterate the
window on image to apply filter on all of the image.
I put the original image as a header file in C code. And use RS232 to send
the resulted image from board to computer. The resulted image is a matrix
of numbers between 0 and 255
First I used RS232 with baud rate 9600. it worked perfect and gives the
resulted image to computer. the only problem was that the speed of sending
image was too low.
problem:
I went back to edk, changed RS232 baud rate to 19200 and regenerated
everything. it also worked with 19200. but still the speed was too low.
I changed the baud rate to 57600 and regenerated everything. when I tested
the design, IT GIVES THE ALPHABET CODES CORRECT BUT THE MATRIX IS ALL
ZEROS.
for example main part of my C code is like:
xil_printf("hello");
print("Hello Worldnr");
MYCORE_SelfTest(); //the custom IP works here
xil_printf("printing final image...rnrn");
for(i=0;i<img_size;i++){
for(j=0;j<img_size;j++){
sprintf(out,"%d ",image_res[i][j]);
print(out);
}
print("nr");
}
and it gives me:
helloHello World
printing final image...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
it's completely ridiculous! I don't know what is the relation between
baudrate of RS232 and work of the FSL coprocessor.
i think the problem is related to FSL coprocessor, why it works for slower
baud rates!!!
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 157735
hafezmg48 wrote:
> Hi guys,
>
> I'm not sure this is the right place to ask this question, but I found no
> answers to it on xilinx forums. Hope you can help me!
>
> intro:
>
> I work with atlys board. using Microblaze processor. Using xilinx EDK and
> SDK as tools.
>
> For an image processing purpose, I designed a custom coprocessor with FSL
> bus, which gets a (4,4) pixel window of an image from microblaze and
> applies a filter on it ,then sends it back to microblaze.I iterate the
> window on image to apply filter on all of the image.
>
> I put the original image as a header file in C code. And use RS232 to send
> the resulted image from board to computer. The resulted image is a matrix
> of numbers between 0 and 255
>
> First I used RS232 with baud rate 9600. it worked perfect and gives the
> resulted image to computer. the only problem was that the speed of sending
> image was too low.
>
> problem:
> I went back to edk, changed RS232 baud rate to 19200 and regenerated
> everything. it also worked with 19200. but still the speed was too low.
>
> I changed the baud rate to 57600 and regenerated everything. when I tested
> the design, IT GIVES THE ALPHABET CODES CORRECT BUT THE MATRIX IS ALL
> ZEROS.
>
> for example main part of my C code is like:
>
> xil_printf("hello");
> print("Hello Worldnr");
> MYCORE_SelfTest(); //the custom IP works here
>
> xil_printf("printing final image...rnrn");
> for(i=0;i<img_size;i++){
> for(j=0;j<img_size;j++){
> sprintf(out,"%d ",image_res[i][j]);
> print(out);
> }
> print("nr");
> }
>
>
>
> and it gives me:
>
> helloHello World
> printing final image...
> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
>
>
> it's completely ridiculous! I don't know what is the relation between
> baudrate of RS232 and work of the FSL coprocessor.
> i think the problem is related to FSL coprocessor, why it works for slower
> baud rates!!!
>
>
>
>
>
>
> ---------------------------------------
> Posted through http://www.FPGARelated.com
I can only think of two things:
1) The FSL is not finished when you start the printout, so lowering the
baud rate allows the system to wait for the results.
2) You lost the data in the header file when you re-built for the higher
baud rate, and the reference image is therefore all zero.
--
Gabor
Article: 157736Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship from China and are fake copies I assume, they cost less than $7 inc shipping. If I download and install Altera Quartus II software can I use that to JTAG program my device file compiled in Xilinx ISE? Thanks for any help.Article: 157737
jackm wrote: > Hello, > I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On > Ebay they sell Altera USB Blaster JTAG programmers that ship from China > and are fake copies I assume, they cost less than $7 inc shipping. If I > download and install Altera Quartus II software can I use that to JTAG > program my device file compiled in Xilinx ISE? Thanks for any help. I got a Platform USB cable from China for about $30. I'm guessing it is a well-made but unauthorized clone. It works fine. I used to use a Parallel Cable III, but have not been able to get it to work on 64-bit Linux OS. JonArticle: 157738
Jon Elson wrote: > jackm wrote: > >> Hello, >> I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On >> Ebay they sell Altera USB Blaster JTAG programmers that ship from China >> and are fake copies I assume, they cost less than $7 inc shipping. If I >> download and install Altera Quartus II software can I use that to JTAG >> program my device file compiled in Xilinx ISE? Thanks for any help. > I got a Platform USB cable from China for about $30. I'm guessing it > is a well-made but unauthorized clone. It works fine. > > I used to use a Parallel Cable III, but have not been able to get it > to work on 64-bit Linux OS. > > Jon Xilinx dropped support for the Parallel cable 3 in recent versions of Impact. It still supports Parallel cable 4. That being said, it's getting harder to find a PC with a parallel port, and the Xilinx software doesn't like USB to parallel adapters, so at a minimum you'd need either a motherboard with the parallel port or a PCI add-in card with a legacy-compliant parallel port. Forget the Altera cable, because Xilinx software doesn't work with anything they don't make or authorize. A lot of small cheap FPGA demo boards use an FTDI chip that is compatible with Digilent's Adept software. It might actually be cheaper if you can find such a board on eBay and just put wires on the JTAG lines to go to your own board (you'd have to cut the TDO connection from the on-board FPGA). If you can still get the Chinese clones for $30 that might be the cheapest way without jumping through a lot of hoops. -- GaborArticle: 157739
> Forget the Altera cable, because Xilinx software doesn't work > with anything they don't make or authorize. Yes I know that Xilinx software would not work with an Altera programmer but my question is what if I used Altera's Quartus II software with the Altera programmer? I don't know much about JTAG but would it be possible for the Quartus II software to detect a Xilinx device in the JTAG chain and let me program it with a file of my choosing??Article: 157740
jackm <jmm385@gmail.com> wrote: > >> Forget the Altera cable, because Xilinx software doesn't work >> with anything they don't make or authorize. > Yes I know that Xilinx software would not work with an Altera > programmer but my question is what if I used Altera's Quartus II > software with the Altera programmer? > I don't know much about JTAG but would it be possible for the > Quartus II software to detect a Xilinx device in the JTAG chain > and let me program it with a file of my choosing?? I have wondered if the Xilinx software and cable will load or dump JTAG devices that aren't FPGAs. Seems like it is the same question for Altera. You might have to convert the bits to a different format first, though. -- glenArticle: 157741
On 2015-02-26 glen herrmannsfeldt wrote in comp.arch.fpga: > jackm <jmm385@gmail.com> wrote: >> >>> Forget the Altera cable, because Xilinx software doesn't work >>> with anything they don't make or authorize. > >> Yes I know that Xilinx software would not work with an Altera >> programmer but my question is what if I used Altera's Quartus II >> software with the Altera programmer? >> I don't know much about JTAG but would it be possible for the >> Quartus II software to detect a Xilinx device in the JTAG chain >> and let me program it with a file of my choosing?? > > I have wondered if the Xilinx software and cable will load or dump > JTAG devices that aren't FPGAs. > > Seems like it is the same question for Altera. > > You might have to convert the bits to a different format first, though. Well, in a lot of cases you don't load the FPGA, you load the configuration memory. I remember a Spartan-3 project that where we booted the FPGA from SPI dataflash. This dataflash was directly programmed with Impact, using parallel cable IV(?) and also with the USB cable. In that same project there was another dataflash for a CPU that was also programmed using Impact. But indeed you had to watch things like word size bit order etc. But this was all with stuff that's pretty old now, I don't know if they 'fixed' this in current stuff. Later we switched to using the Aardvark for programming the dataflashes, as this was less cumbersome to use than Impact. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Don't talk to me about naval tradition. It's nothing but rum, sodomy and the lash. -- Winston ChurchillArticle: 157742
thanks for reply. answer to: 1. I'm using blocking getfsl function, so it only gets to the next line when it recieves the data. Meaning that the FSL core has ended it's work. 2. No I'm sure it is just related to baud rate, because after this issue, when I decreased the baud rate again to the previous number, it worked! I figured out that it just works with 9600 and 19200. it gives 0 for higher baud rates. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 157743
Stef wrote: > On 2015-02-26 glen herrmannsfeldt wrote in comp.arch.fpga: >> jackm <jmm385@gmail.com> wrote: >>>> Forget the Altera cable, because Xilinx software doesn't work >>>> with anything they don't make or authorize. >> >>> Yes I know that Xilinx software would not work with an Altera >>> programmer but my question is what if I used Altera's Quartus II >>> software with the Altera programmer? >>> I don't know much about JTAG but would it be possible for the >>> Quartus II software to detect a Xilinx device in the JTAG chain >>> and let me program it with a file of my choosing?? >> I have wondered if the Xilinx software and cable will load or dump >> JTAG devices that aren't FPGAs. >> >> Seems like it is the same question for Altera. >> >> You might have to convert the bits to a different format first, though. > > Well, in a lot of cases you don't load the FPGA, you load the > configuration memory. I remember a Spartan-3 project that where we > booted the FPGA from SPI dataflash. This dataflash was directly > programmed with Impact, using parallel cable IV(?) and also with > the USB cable. In that same project there was another dataflash > for a CPU that was also programmed using Impact. But indeed you > had to watch things like word size bit order etc. > > But this was all with stuff that's pretty old now, I don't know > if they 'fixed' this in current stuff. > They "fixed" direct SPI programming in the sense you "fix" the cat you don't want to have kittens. However there are much cheaper devices on the market to go from USB to SPI that can directly program SPI flash. No good for direct JTAG load of FPGA's or for ChipScope. > Later we switched to using the Aardvark for programming the > dataflashes, as this was less cumbersome to use than Impact. >Article: 157744
Den onsdag den 25. februar 2015 kl. 23.10.46 UTC+1 skrev Gabor: > Jon Elson wrote: > > jackm wrote: > > > >> Hello, > >> I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On > >> Ebay they sell Altera USB Blaster JTAG programmers that ship from China > >> and are fake copies I assume, they cost less than $7 inc shipping. If I > >> download and install Altera Quartus II software can I use that to JTAG > >> program my device file compiled in Xilinx ISE? Thanks for any help. > > I got a Platform USB cable from China for about $30. I'm guessing it > > is a well-made but unauthorized clone. It works fine. > > > > I used to use a Parallel Cable III, but have not been able to get it > > to work on 64-bit Linux OS. > > > > Jon > > Xilinx dropped support for the Parallel cable 3 in recent versions > of Impact. It still supports Parallel cable 4. That being said, > it's getting harder to find a PC with a parallel port, and the > Xilinx software doesn't like USB to parallel adapters, so at a > minimum you'd need either a motherboard with the parallel port > or a PCI add-in card with a legacy-compliant parallel port. > > Forget the Altera cable, because Xilinx software doesn't work > with anything they don't make or authorize. A lot of small > cheap FPGA demo boards use an FTDI chip that is compatible > with Digilent's Adept software. It might actually be cheaper > if you can find such a board on eBay and just put wires on > the JTAG lines to go to your own board (you'd have to cut the > TDO connection from the on-board FPGA). > > If you can still get the Chinese clones for $30 that might be > the cheapest way without jumping through a lot of hoops. > > -- > Gabor $59 isn't terribly expensive for something that works with the Xilinx software http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,1298&Prod=JTAG-HS3 -LasseArticle: 157745
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > jackm <jmm385@gmail.com> wrote: > > > > Yes I know that Xilinx software would not work with an Altera > > programmer but my question is what if I used Altera's Quartus II > > software with the Altera programmer? > > I don't know much about JTAG but would it be possible for the > > Quartus II software to detect a Xilinx device in the JTAG chain > > and let me program it with a file of my choosing?? > > I have wondered if the Xilinx software and cable will load or dump > JTAG devices that aren't FPGAs. > > Seems like it is the same question for Altera. Quartus' JTAG programmer will program flash that's hung off an FPGA, but sometimes you need to load a 'programmer' bitfile into the FPGA first - since often flash doesn't have a direct JTAG port. Programming FPGAs themselves is an Altera/Xilinx specific protocol - you don't just throw bitfiles at them. JAM/STAPL is an output format for non-Altera tools/programmers to program Altera FPGAs (eg some a host MCU can program its nextdoor PLD) - looks like Xilinx are similar: http://corelis.com/blog/pld-tools-creating-svf-jam-stapl-and-other-formats/ This is better supported in the CPLD world than the FPGA world however. However this is just about programming - you don't get to interact with the device afterwards without the vendor tools (that means things like logic analysers, debuggers, JTAG UARTs, etc require the vendor cable). TheoArticle: 157746
GaborSzakacs wrote: > If you can still get the Chinese clones for $30 that might be > the cheapest way without jumping through a lot of hoops. > They are still showing up on eBay for $30 - 45, quite a few listings of new units. Probably all unofficial clones, I'm guessing. JonArticle: 157747
jackm wrote: > >> Forget the Altera cable, because Xilinx software doesn't work >> with anything they don't make or authorize. > > Yes I know that Xilinx software would not work with an Altera programmer > but my question is what if I used Altera's Quartus II software with the > Altera programmer? I don't know much about JTAG but would it be possible > for the Quartus II software to detect a Xilinx device in the JTAG chain > and let me program it with a file of my choosing?? Pretty unlikely. i think the FPGAs have the memory divided into blocks, and each block has a CRC that has to match a live one that is calculated as it is loading for the load to be accepted. I guess the CRC is actually present in the .bit file, but there still needs to be a bunch of hand-shaking for it to all work. The standardisation of the JTAG only goes as far as having several JTAG ports connected in a serial string, and getting a device type ID from each device. So, it would be EXTREMELY unlikely that Altera software would accept a Xilinx .bit file, or know how to set up the internal state of a Xilinx CPLD for programming/downloading. Now, a Xilinx CPLD is a bit different, they look a lot more like a generic memory, and the programming file is in JEDEC format. So, I think programming them might be a bit more generic. JonArticle: 157748
On Wed, 25 Feb 2015 16:38:46 -0800, jackm wrote: >> Forget the Altera cable, because Xilinx software doesn't work with >> anything they don't make or authorize. > > Yes I know that Xilinx software would not work with an Altera programmer > but my question is what if I used Altera's Quartus II software with the > Altera programmer? > I don't know much about JTAG but would it be possible for the Quartus II > software to detect a Xilinx device in the JTAG chain and let me program > it with a file of my choosing?? You may wanna try Lattice's software, provided you have hardware at hand you can use with it. Of the many different programming schemes, they have what they call "JTAG full VME embedded" system. It consists of a small program that is supposed to be uploaded to a dedicated programmer and which takes as input VME files. VME files are a 1:1 binary format of SVF files. This program can also be used on a PC equipped with random peripherals. You will need to teach it how to use your hardware and you will probably need to severely optimize the program to account for very high latencies of a PC system, but it can be done. If your Xilinx software can produce SVF files, the Lattice embedded programmer is supposed to be able to program devices with it. It even has special provisions for Xilinx devices written into the source (the programmer is open source).Article: 157749
glen herrmannsfeldt <gah@ugcs.caltech.edu> writes: > I have wondered if the Xilinx software and cable will load or dump > JTAG devices that aren't FPGAs. By generating SVF files I've programmed Altera FPGA's using Xilinx impact and cable (or the other way around, can't remember). I would expect it to work both ways as long as you can generate and play a SVF file. //Petter -- .sig removed by request.
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