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Has anybody tried to get rid of the Xilinx SPROMS ? They are immoral expensive ! Could be a small CPLD + Flash memory a cheaper solution ? - ManfredArticle: 39951
In article <a55nj2$4t1hd$1@ID-22088.news.dfncis.de>, newsreply@cesys.com says... > Has anybody tried to get rid of the Xilinx SPROMS ? > They are immoral expensive ! > Could be a small CPLD + Flash memory a cheaper solution ? Sure. There are many ways to skin that cat. I use an 8051 derivative and EPROM/Flash/SRAM depending on the application. ---- KeithArticle: 39952
<snip question about adding pins assignments to Quartus files> You can use the TCL scripting functionality of Quartus for this. It makes things very simple when starting new projects based on the same design. The basic syntax for adding pin assignments is: cmp start_batch cmp add_assignment "nios_system_module" "" "clk2p" "LOCATION" "Pin_N8" cmp add_assignment "nios_system_module" "" "e_ad\[38\]" "LOCATION" "Pin_V25" cmp end_batch Here we're performing the assignments in batch mode (much faster) and are assigning pin N8 to clk2p and pin V25 to e_ad[38]. Note the \ to escape the []s and the top level design entity in this case is nios_system_module. Once you've created the tcl file for your board (e.g. using Notepad), open the Quartus TCL console and type "source APEX_PCI.tcl" where APEX_PCI.tcl is replaced by the name of your tcl file. You can do lots more complicated things with the TCL scripting, let me know if you want examples. It's much easier than using the dialog box or hacking the .csf by hand (which you have to do with Quartus closed else it'll get overwritten) Hope this helps, JamesArticle: 39953
Yes, that is the top of the line for now. The timing for the QPRO is the
same as for the XCVxxx-4. We have used a number of QPRO devices for
satellite as well as high altitude aircraft sensor (eg radar)
applications. I'm not sure if any are actually in space yet, but I do
know that several have flown on high altitude aircraft. If it is a space
application, make sure you put a mechanism to detect and correct upsets
both in the data and in the device configuration. They will happen.
Depending on the criticality of your system, this may mean periodic
reprogramming, scrubbing the configuration (not possible for BRAMs or
columns containing CLB RAM or SRL16's ), TMR, periodic test vectors, and
duplicated hardware. You'll probably also need to watch power
dissipation, especially if your circuit power is cycled frequently.
Antonio wrote:
> For my Thesis I'm interested to propose a FPGA to use for a QPSK
> modulator instead of an ASIC, I would want to know if the V1000
> BG560-4 is the top for the QPRO series or there are QPRO version of
> VIRTEX_E or VIRTEX_2, another question is to know if the performance I
> can obtain on standard V1000 BG560-4 are the same I can obtain on the
> QPRO version. The last question is if do you know of FPGA already
> mounted on a Satellite for a critical service like modulation. Thanks
>
> Antonio
>
> P.S. Another question, there are available board to test the QPRO
> VIRTEX or is the same to test on a board with a standard V1000 BG560-4
> ?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39954Peter's point is that after the chip is configured, the INIT pin is not driven by the internal configuration logic anymore. If you are not using it, it should be floating or maybe lightly pulled up internally (although you are likely pulling it up externally). So if it is low, either you are driving the line low from inside the chip or you are driving the line low outside the chip. But either way... the configuration circuit inside the chip is not driving it low. Mark van de Belt wrote: > > That's it. I was not using the pin at all. > Thanks > > "Peter Alfke" <peter.alfke@xilinx.com> wrote in message > news:3C757918.7011049D@xilinx.com... > > The INIT pin description in the data sheet, table 55, says: > > "..After the I/O go active" ( i.e. after the end of configuration) > "INIT is a > > user-programmable I/O pin." > > What are you using this pin for? > > > > Peter Alfke, Xilinx Applications > > ============================= > > Mark van de Belt wrote: > > > > > Hello, > > > > > > I'm trying to configure a XC2S30 FPGA from the ISA bus in a PC > (embedded). > > > The configuration file generation is no problem and I'm following the > > > datasheet and application note for 'Parallel slave' programming: > > > (as seen from the processor) > > > WRITE# = '0' (always) > > > PROGRAM# = '1' > > > INIT# = input with pull up > > > DONE = input with pull up > > > CCLK = IOW# > > > CS# = CS# from ISA bus (0x360) > > > DATA = DATA > > > > > > To start I pulse the PROGRAM# low and wait for INIT# to come high. > > > Then I start writing to addres 0x360. > > > After the last byte the DONE line is high, but the INIT line is low. > > > According to the datasheet this line should be high aswell. The content > of > > > the FPGA is correct, I can access the internal registers. > > > Why is the INIT# pin low? > > > > > > Thanks in advance > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39955
Jim Granville wrote: > > rickman wrote: ...snip... > > The real problem is the lousy support of scan chains by the emulation > > tool vendors. They don't seem to understand that JTAG ports are for > > anything other than emulation. > > What about a SPLD like a 16V8, to klude what's needed ? > > - jg You mean add a PLD to allow me to reprogram my CPLD? Part of the problem is that PLDs are not at all small. This board is already very tight and I have never seen a PLD that came in a small enough package. But I also don't like the idea of adding a PLD for this. How do I in-system reprogram the PLD? I might have to add muxes though... or just forget about using boundary scan chains. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39956
Nice tip James. I have been wondering whether to create some form of forum for Altera tips and tricks just such as this. Any scripts you have available to show different aspects of getting Quartus to work would be gratefully received here, particularly if you gave me permission to post them. I might even get round to setting up some forums :) Paul Baxter Emails to pauljbaxternospam@no.spamhotmail.com removing no spam "James Srinivasan" <James_Srinivasan@nospam.yahoo.com> wrote in message news:a55r78$b3s$1@pegasus.csx.cam.ac.uk... > <snip question about adding pins assignments to Quartus files> > > You can use the TCL scripting functionality of Quartus for this. It makes > things very simple when starting new projects based on the same design. The > basic syntax for adding pin assignments is: > > cmp start_batch > cmp add_assignment "nios_system_module" "" "clk2p" "LOCATION" "Pin_N8" > cmp add_assignment "nios_system_module" "" "e_ad\[38\]" "LOCATION" "Pin_V25" > cmp end_batch > > Here we're performing the assignments in batch mode (much faster) and are > assigning pin N8 to clk2p and pin V25 to e_ad[38]. Note the \ to escape the > []s and the top level design entity in this case is nios_system_module. > Once you've created the tcl file for your board (e.g. using Notepad), open > the Quartus TCL console and type "source APEX_PCI.tcl" where APEX_PCI.tcl is > replaced by the name of your tcl file. You can do lots more complicated > things with the TCL scripting, let me know if you want examples. It's much > easier than using the dialog box or hacking the .csf by hand (which you have > to do with Quartus closed else it'll get overwritten) > > Hope this helps, > > James > > > >Article: 39957
Yes, that is the part I hate the most. TI has all kinds of documentation telling you how to use boundary scan with their DSPs. It would appear that they were one of the early supporters of JTAG for boundary scan. But when you speak with a DSP support person, they tell you "don't". I just don't understand why such a simple thing as JTAG is so complex. I think it is more a matter of "we don't care, it's not our business line". Boundary scan vendors don't sell emulators and emulation vendors don't sell boundary scan support. And of course Atmel claims their chips are boundary scan compatible, but their emulators won't get within a mile of a boundary scan chain. Oddly enough (or maybe not so odd) Xilinx seems to support boundary scan chains and it actually works (or so I hear). Ray Andraka wrote: > > Ayup, I've been on a number of projects where they finally threw up their > hands and said forget trying to put the DSP and FPGA/CPLD JTAG on the same > chain because the emulators had a nasty habit of really screwing up the > FPGA/CPLD. When faced with the question, the emulator vendors said "well, > don't do that". > > rickman wrote: > > > The real problem is the lousy support of scan chains by the emulation > > tool vendors. They don't seem to understand that JTAG ports are for > > anything other than emulation. > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39958
rickman wrote: >That is not the problem. My problem is that the wiring for the JTAG >chain gets very complex. I have two processors and two PLDs in the >chain. I need to run in five different modes; > >1) All four devices in one Boundary Scan chain. > >2) DSP as alone as I can get it for emulation. > >3) MCU totally alone for emulator that does not work in a chain. > >4) CPLD driven by MCU for in-system and in-field change to bit file. > >5) (optional maybe) CPLD in chain driven from header for factory load of >bit file. >This one might be done in mode 1) or in mode 4) > I would use three separate JTAG "chains". I agree that you want only a single device in a chain for emulation. I don't like jumpers either. You can bus TCK/TDI/TDO together and have only three separate TMS's. I was going to suggest connecting the entire chain with resistors and overdriving parts of it, but I think three chains will work better (and not take a performance hit). Alan Nishioka alann@accom.comArticle: 39959
I would suggest that you get a support person to walk you through that flow. It just does not sound right to me. Perhaps the tools understand that the VHDL netlist is just IO and not to be synthesized, but then why is it needed??? The only thing that is needed is a module definition of the IOs to the PCI interface. This should be implicit in the schematic symbol for the PCI core. The other thing that makes no sense is why do you need to synthesize anything if you are entering your design in schematic form? Synthesis is used for HDLs. If the only part that is in HDL is the PCI core (which does not need to be synthesized) then what is being synthesized??? Have you tried skipping the synthesis step and passing the schematic generated EDIF directly to Foundry? I think there is something very wrong with communications here and I am not talking about RS-232. :) Carsten wrote: > > Thanks for your efforts. > I need to include the VHDL netlist (which defines only the I/Os of the > core) to be able to connect my design to the core. This is according to the > FPSC design flow as shown in the documentation. Next step is to export an > EDIF netlist from Viewdraw. This EDIF netlist and the VHDL netlist of the > core are the source files in FPGA Express that I use to synthesize the > design. Following step is to export an EDIF netlist from FPGA Express and > im port it into the Orca Foundry. > > rickman <spamgoeshere4@yahoo.com> wrote in > news:3C72858F.520A6C49@yahoo.com: > > > I am not clear about what you are trying to do. If you want to create a > > bit stream, then why do you need to include VHDL for the embedded > > PCI-Core? This part is already in the silicon and should not be > > represented in the bit stream. > > > > If you are trying to perform simulation, I expect you should do this > > before you synthesize. You will need some form of model for the > > PCi-Core. If you translate the schematic to VHDL, then your VHDL for > > the PCI-Core should be a module in the VHDL that is produced. > > > > But the fact that you are trying to produce an EDIF netlist says to me > > that you are doing the former rather than the later. So why are you > > trying to include the PCI-Core in the bit stream? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39960
> Has anybody tried to get rid of the Xilinx SPROMS ? > They are immoral expensive ! If your system is controlled by PC, you can configure FPGAs from PC. Only one FPGA which implements the communication logic, must be configured by SPROMs, but all other devices don't need any SPROMs. I use a small device for the communication with PC, because it needs only one small SPROM. Then I can store my configuration bit stream on a hard disk drive, which is very cheap and convenient. TadashiArticle: 39961
> I have been wondering whether to create some form of forum for Altera tips > and tricks just such as this. I was wondering the same. I'm subscribed to a few FPGA related Yahoo groups but the only Altera specific one I found (alteraFPGA) is pretty low-traffic, plus the ads are starting to really annoy me. I've got a few documents produced from an Altera-sponsored internship which may be of use to people. I'll check it's ok to release them then see about setting up some sort of forum - any ideas? JamesArticle: 39962
Thanks Pete. I had heard Quartus now supported the low end but it wasn't clear to me if that was only the full version. Sigh. I'll have to go learn that too now :-) Thanks again -- I'll try the registry fix.Article: 39963
Maybe you can use some ideas from Altera's website? They use flash and low cost CPLD. If your system uses flash anyway, this is a cheap solution. "Manfred Kraus" <newsreply@cesys.com> schreef in bericht news:a55nj2$4t1hd$1@ID-22088.news.dfncis.de... > Has anybody tried to get rid of the Xilinx SPROMS ? > They are immoral expensive ! > Could be a small CPLD + Flash memory a cheaper solution ? > > - Manfred > > >Article: 39964
rickman wrote: > > Jim Granville wrote: > > > > rickman wrote: > ...snip... > > > The real problem is the lousy support of scan chains by the emulation > > > tool vendors. They don't seem to understand that JTAG ports are for > > > anything other than emulation. > > > > What about a SPLD like a 16V8, to klude what's needed ? > > > > - jg > > You mean add a PLD to allow me to reprogram my CPLD? Yes. > Part of the problem is that PLDs are not at all small. > This board is already very > tight and I have never seen a PLD that came in a small enough package. Currently smallest is TSSOP20, 6.5mm x 6.5mm. > But I also don't like the idea of adding a PLD for this. How do I > in-system reprogram the PLD? Why would you need to ? > I might have to add muxes though... or > just forget about using boundary scan chains. Agreed, it will be a compromise. SPLD is lower profile, & less error prone than Jumpers, and is a little more 'soft' than a hard wired MUX solution. Since SCAN+DEBUG is off the radar, as you say, future die versions ( or even SW versions :-), may have 'different features' -jgArticle: 39965
"Kumar" <yatiks@yahoo.com> schrieb im Newsbeitrag news:b479edf8.0202212023.45241fd@posting.google.com... > > > > Looks like a driver problem. > > I dont think its a driver problem because when I connected the > printer to this port ,Printer worked properly. The parallel-cable has its own driver (dont ask me why such a simple device needs a "special" driver, always those stupid software guys . . . .:-0 It is installed during the install of Foundation/ISE or Impact-stand alone. -- MfG FalkArticle: 39966
"X. Q." <qijun@okigrp.com.sg> schrieb im Newsbeitrag news:3c759296@news.starhub.net.sg... > Well, the problem is that the group who wants this design knows nothing > about FPGA. I need to make it such that when they plug in the power > supply, the correct signals come out of the board. They need these signals > for testing their chips. So simply take a XC18Vxx and store the FPGA config there. Connect it the right way to the FPGA and use master serial mode to make the FPGA load its configuration after power up. Its easy. > I am still not pretty sure about Actel and QuickLogic. Does it take lot of > time and labor to change my toolset from Xilinx to Actel or QuickLogic? Depends on your design. If you dont use any special feature form Xilinx (BRAM, SelectRAM, DLL etc) the conversion will be easy, otherwise . . . > For EEPROM stuff, what do I need in order to save my configuration files > into a EEPROM? I found that in my iMPACT window I only see the FPGA > device, not so much EEPROM device, even though there is one PROM on the > board. Simply, because the XC18Vxx (they are FLASH, not EEPROM) are programmed via JTAG. Just treat them as an FPGA and programm them. Voala. Ok, there is a minor difference. For programming a XC18Vxx, you need to convert the *.bit file into a *.mcs file using the PROM formater. But this is done within seconds. -- MfG FalkArticle: 39967
"Seb" <no@valid.address.com> schrieb im Newsbeitrag news:aamd8.12498$Wm3.573680@zwoll1.home.nl... > I want to initialise the memory core that i made with CoreGen. This can be > done by making a .coe file before building the core. So if i want to change > the initialisation data, i have to rebuild the core...again and again. > > My question: is it possible to construct the core with a pointer to the .coe > file, so that the content is included in a later stage (by ISE)...this way AFAIK no, because CoreGen creates a EDIF file, that is not changed after the creation. > it would be possible to change the .coe file without having to rebuild the > memory core. A method to achieve the goal is to use the INIT attribute in the VHDL description. Or in the UCF. -- MfG FalkArticle: 39968
I think a better question is: How can I reduce the number of clocks in my design? Unless all your clocks are inherently unrelated and asynchronous to each other, it would make sense to use Clock Enable control, instead of many clocks. Peter Alfke, Xilinx Applications ======================== JHL wrote: > Hello everyone! > > I now program virtex(XCV50-4BG256) using VHDL. > Because I use many clock signal in my design, when I make my VHDL source > synthesized into the chip, I often receive some error messages, which say to > me that it is impossible to map > my source to this chip because of lack of CLK buffer resource. > > How can I disable clock buffer insertion in Xilinx Foundation F3.1i?Article: 39969
"JHL" <jaehwanida@orgio.net> schrieb im Newsbeitrag news:jyqd8.135$Az6.595@news.hananet.net... > Hello everyone! > > I now program virtex(XCV50-4BG256) using VHDL. > Because I use many clock signal in my design, when I make my VHDL source At first, try to use as less clock signals as possible. Forget about all those old coding styles from the TTL aera, they dont work well with FPGAs. Use clock enables instead. Read the coding style guide from Xilinx. Or the actuall Tech-exclusive on the homepage. > synthesized into the chip, I often receive some error messages, which say to > me that it is impossible to map > my source to this chip because of lack of CLK buffer resource. If you really need more clock, you can disable the BUFG usage in the synthesis constraints. Switch to the versions view, then click right on your version, in the pop-up you will find a point synthesis constraint. In the next window you will find a tab called "port", there you can select the BUFG insertion or not. -- MfG FalkArticle: 39970
"Yoram Rovner" <yoram@puc.cl> schrieb im Newsbeitrag news:62ef4351.0202220559.132a1553@posting.google.com... > Hi: > > I am a newbie on fpga issues and I need some recomendations. I am > planning to develop a cpu in a cpld. I have XESS XS95 board v.1.3 and Uhhh, I think you are on the wrong road. The ressources of CPLDs are VERY limited, even if you have 512 macrocells. You better drop the board and go for a FPGA, Spatan-II is very niche, fast and has much ressources for such projects. www.nuhorizon.com www.burched.com www.fpgacpu.org > the student edition of Xilinx Foundation 1.5. I had some experiences > in programing with verilog so i will like to do this cpu in that > language. I have heard that Xilinx foundation student edition do not > provide a good tool for developing with verilog (i mean error reports, > etc). Would be better to use Webpack ise?, is there another > software(maybe free or low cost) that is recommended to use? Hmm, I dont know, I only use VHDL. -- MfG Falk P.S. YES, you can build a CPU in a CPLD, but this is much a thing of optimization, not realy learning.Article: 39971
--------------64663F8BDAB240A50494A9AB Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit click on http://support.xilinx.com/support/techxclusives/fifo-techX18.htm The best Gray-code counter implementation actually starts with a binary counter and converts it, bit by bit, to Gray. Therefore, you can subtract the two binary count values, and then clean up the result with techniques described in my another paper http://support.xilinx.com/support/techxclusives/MovingData-techX16.htm Peter Alfke, Xilinx Applications ====================== starpanda wrote: > Hi, > Right now I am developing a design which has to use a Asyn FIFO. Due > to resource limitation, I have to use a dual port RAM to implement > this Asyn FIFO (Read in one clock domain, write in another clock > domain). I have to implement my own "Full" and "Empty" signals, but > both signals involves signals in both clock domain (head and tail > pointers). What should I do to avoid metastability problem when I try > to calculate the data size of the FIFO? > Thanks! > > JaiphenArticle: 39972
I guess I should have worded my posting a little more carefully.
The PCI Local Bus Specification Revision 2.2 Appendix B's target and
initiator state machine diagram should be a starting point of a PCI
interface's state machine, but what I found with those state machines is
that a few additional states may be have to be added to simplify the
actual implementation.
Besides that all the books I have seen only explains the PCI bus
protocol.
However, if someone is interested in developing a PCI IP core, I
recommend downloading a copy of Xilinx LogiCORE PCI Design Guide from
Xilinx, Altera PCI MegaCore Function User Guide from Altera, and
Synopsys DWPCI (a PCI IP core for ASICs) Data Book from Synopsys.
Of course, those documents won't (will never) discuss the inner workings
of their PCI IP cores, but it should give some clue on how a PCI IP
core's backend interface should be designed.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Eric Smith wrote:
>
> Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com> writes:
> > Since there are almost no good books available on the implementation
> > side of a PCI IP core,
>
> Is that "almost no", or just "no"? If you know of one, by all means please
> let us know. :-)
Article: 39973
"X. Q." wrote:
>
> Well, the problem is that the group who wants this design knows nothing
> about FPGA. I need to make it such that when they plug in the power
> supply, the correct signals come out of the board. They need these signals
> for testing their chips.
>
Why not send a board to that group which already have a
Spartan-II and a Configuration PROM (like XC18V01 or XC18V02) on it?
Assuming that the Configuration PROM is wired up correctly to the FPGA,
when the board is powered up, the FPGA will be active typically in less
than 100ms.
> I am still not pretty sure about Actel and QuickLogic. Does it take lot of
> time and labor to change my toolset from Xilinx to Actel or QuickLogic?
>
Although anti-fuse FPGAs have its advantage that prevents
bitstream piracy and it is active instantly, I think it is costly during
development because once you burn the anti-fuse FPGA chip, you cannot
reprogram it again like an SRAM FPGA from Xilinx or Altera.
Well, it looks like you work for a company, so burning a few buggy
anti-fuse FPGAs won't cost you anything (It will cost the company
something.).
Actel's Flash-based FPGA, ProASIC sounds interesting since it can be
reprogrammed, but I don't hear much about it (Yes, it is shipping in
volume, but I don't see too many people at news:comp.arch.fpga using
it.).
If your design doesn't use Xilinx specific features like DLL or
BlockRAM, the porting to a different FPGA should not be too difficult.
> For EEPROM stuff, what do I need in order to save my configuration files
> into a EEPROM? I found that in my iMPACT window I only see the FPGA
> device, not so much EEPROM device, even though there is one PROM on the
> board.
>
> Thanks.
> XQ.
>
That is because your board doesn't have the Configuration PROM
attached to the FPGA.
If you wire up the Xilinx Configuration PROM correctly, it should show
up on the screen.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 39974
I recommend using the latest ISE WebPACK 4.1 instead of whatever design
software you got right now.
ISE WebPACK 4.1 also comes with a speed limited version of ModelSim
called ModelSim XE-Starter, which slows down the simulation after
500-lines of code, but won't stop simulating.
Both of them are free, not there is nothing to lose.
Also, consider using FPGAs like Xilinx Spartan-II or Spartan-IIE
because it is much bigger than most CPLDs.
In general, use the latest devices available (In this case, Spartan-IIE)
because they tend to be cheaper than the older devices (Spartan-II) of
the same density or speed, but if you have to interface to a 5V
interfaces like TTL or 5V PCI, use Spartan-II because Spartan-IIE won't
support it without external voltage level conversion chips.
You may also want to look at Insight Electronics in addition to the URLs
Falk gave you.
http://208.129.228.206/solutions/kits/xilinx/
(Note: I am not paid (I wish I was paid . . .) to provide this URL.
Although I am a happy customer of Insight Electronics' Spartan-II PCI
Development Kit.)
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Yoram Rovner wrote:
>
> Hi:
>
> I am a newbie on fpga issues and I need some recomendations. I am
> planning to develop a cpu in a cpld. I have XESS XS95 board v.1.3 and
> the student edition of Xilinx Foundation 1.5. I had some experiences
> in programing with verilog so i will like to do this cpu in that
> language. I have heard that Xilinx foundation student edition do not
> provide a good tool for developing with verilog (i mean error reports,
> etc). Would be better to use Webpack ise?, is there another
> software(maybe free or low cost) that is recommended to use?
>
> Thanks,
>
> Yoram Rovner
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